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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 45 of 148
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Patent #:	7612371	Issue Dt:	11/03/2009	Application #:	11306944	Filing Dt:	01/17/2006
Publication #:	US20070164421	Pub Dt:	07/19/2007
Title:	STRUCTURE TO MONITOR ARCING IN THE PROCESSING STEPS OF METAL LAYER BUILD ON SILICON-ON-INSULATOR SEMICONDUCTORS

Patent #:	NONE	Issue Dt:		Application #:	11306982	Filing Dt:	01/18/2006
Publication #:	US20070164426	Pub Dt:	07/19/2007
Title:	APPARATUS AND METHOD FOR INTEGRATED CIRCUIT COOLING DURING TESTING AND IMAGE BASED ANALYSIS

Patent #:	7863183	Issue Dt:	01/04/2011	Application #:	11306983	Filing Dt:	01/18/2006
Publication #:	US20070166992	Pub Dt:	07/19/2007
Title:	METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION WITH INTERFACIAL CAP STRUCTURE

Patent #:	7446859	Issue Dt:	11/04/2008	Application #:	11307230	Filing Dt:	01/27/2006
Publication #:	US20070177124	Pub Dt:	08/02/2007
Title:	APPARATUS AND METHOD FOR REDUCING CONTAMINATION IN IMMERSION LITHOGRAPHY

Patent #:	7426420	Issue Dt:	09/16/2008	Application #:	11307288	Filing Dt:	01/31/2006
Publication #:	US20060282187	Pub Dt:	12/14/2006
Title:	SYSTEM FOR DISPATCHING SEMICONDUCTORS LOTS

Patent #:	7407736	Issue Dt:	08/05/2008	Application #:	11307289	Filing Dt:	01/31/2006
Publication #:	US20080057443	Pub Dt:	03/06/2008
Title:	METHODS OF IMPROVING SINGLE LAYER RESIST PATTERNING SCHEME

Patent #:	7786588	Issue Dt:	08/31/2010	Application #:	11307291	Filing Dt:	01/31/2006
Publication #:	US20070178625	Pub Dt:	08/02/2007
Title:	COMPOSITE INTERCONNECT STRUCTURE USING INJECTION MOLDED SOLDER TECHNIQUE

Patent #:	7510939	Issue Dt:	03/31/2009	Application #:	11307294	Filing Dt:	01/31/2006
Publication #:	US20080001225	Pub Dt:	01/03/2008
Title:	MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION

Patent #:	7375371	Issue Dt:	05/20/2008	Application #:	11307324	Filing Dt:	02/01/2006
Publication #:	US20070235769	Pub Dt:	10/11/2007
Title:	STRUCTURE AND METHOD FOR THERMALLY STRESSING OR TESTING A SEMICONDUCTOR DEVICE

Patent #:	7394110	Issue Dt:	07/01/2008	Application #:	11307404	Filing Dt:	02/06/2006
Publication #:	US20070181974	Pub Dt:	08/09/2007
Title:	PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR

Patent #:	7456450	Issue Dt:	11/25/2008	Application #:	11307481	Filing Dt:	02/09/2006
Publication #:	US20070181980	Pub Dt:	08/09/2007
Title:	CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME

Patent #:	NONE	Issue Dt:		Application #:	11307600	Filing Dt:	02/14/2006
Publication #:	US20070187828	Pub Dt:	08/16/2007
Title:	ILD LAYER WITH INTERMEDIATE DIELECTRIC CONSTANT MATERIAL IMMEDIATELY BELOW SILICON DIOXIDE BASED ILD LAYER

Patent #:	7305320	Issue Dt:	12/04/2007	Application #:	11307640	Filing Dt:	02/15/2006
Publication #:	US20070192056	Pub Dt:	08/16/2007
Title:	METROLOGY TOOL RECIPE VALIDATOR USING BEST KNOWN METHODS

Patent #:	7517736	Issue Dt:	04/14/2009	Application #:	11307642	Filing Dt:	02/15/2006
Publication #:	US20080012142	Pub Dt:	01/17/2008
Title:	STRUCTURE AND METHOD OF CHEMICALLY FORMED ANCHORED METALLIC VIAS

Patent #:	NONE	Issue Dt:		Application #:	11307664	Filing Dt:	02/16/2006
Publication #:	US20060120144	Pub Dt:	06/08/2006
Title:	APPARATUS AND METHOD FOR SMALL SIGNAL SENSING IN AN SRAM CELL UTILIZING PFET ACCESS DEVICES

Patent #:	7787101	Issue Dt:	08/31/2010	Application #:	11307669	Filing Dt:	02/16/2006
Publication #:	US20070188731	Pub Dt:	08/16/2007
Title:	APPARATUS AND METHOD FOR REDUCING CONTAMINATION IN IMMERSION LITHOGRAPHY

Patent #:	7439144	Issue Dt:	10/21/2008	Application #:	11307671	Filing Dt:	02/16/2006
Publication #:	US20070190713	Pub Dt:	08/16/2007
Title:	CMOS GATE STRUCTURES FABRICATED BY SELECTIVE OXIDATION

Patent #:	7488660	Issue Dt:	02/10/2009	Application #:	11307759	Filing Dt:	02/21/2006
Publication #:	US20070194387	Pub Dt:	08/23/2007
Title:	EXTENDED RAISED SOURCE/DRAIN STRUCTURE FOR ENHANCED CONTACT AREA AND METHOD FOR FORMING EXTENDED RAISED SOURCE/DRAIN STRUCTURE

Patent #:	7358172	Issue Dt:	04/15/2008	Application #:	11307762	Filing Dt:	02/21/2006
Publication #:	US20070196963	Pub Dt:	08/23/2007
Title:	POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE

Patent #:	7254078	Issue Dt:	08/07/2007	Application #:	11307785	Filing Dt:	02/22/2006
Publication #:	US20070195629	Pub Dt:	08/23/2007
Title:	SYSTEM AND METHOD FOR INCREASING RELIABILITY OF ELECTRICAL FUSE PROGRAMMING

Patent #:	7982475	Issue Dt:	07/19/2011	Application #:	11307828	Filing Dt:	02/24/2006
Publication #:	US20070202616	Pub Dt:	08/30/2007
Title:	STRUCTURE AND METHOD FOR RELIABILITY EVALUATION OF FCPBGA SUBSTRATES FOR HIGH POWER SEMICONDUCTOR PACKAGING APPLICATIONS

Patent #:	7441213	Issue Dt:	10/21/2008	Application #:	11307894	Filing Dt:	02/27/2006
Publication #:	US20070204244	Pub Dt:	08/30/2007
Title:	METHOD FOR TESTING THE VALIDITY OF INITIAL-CONDITION STATEMENTS IN CIRCUIT SIMULATION, AND CORRECTING INCONSISTENCIES THEREOF

Patent #:	7491604	Issue Dt:	02/17/2009	Application #:	11308103	Filing Dt:	03/07/2006
Publication #:	US20070212830	Pub Dt:	09/13/2007
Title:	TRENCH MEMORY WITH MONOLITHIC CONDUCTING MATERIAL AND METHODS FOR FORMING SAME

Patent #:	7795661	Issue Dt:	09/14/2010	Application #:	11308105	Filing Dt:	03/07/2006
Publication #:	US20070210363	Pub Dt:	09/13/2007
Title:	VERTICAL SOI TRANSISTOR MEMORY CELL

Patent #:	7473648	Issue Dt:	01/06/2009	Application #:	11308106	Filing Dt:	03/07/2006
Publication #:	US20070212863	Pub Dt:	09/13/2007
Title:	DOUBLE EXPOSURE DOUBLE RESIST LAYER PROCESS FOR FORMING GATE PATTERNS

Patent #:	NONE	Issue Dt:		Application #:	11308108	Filing Dt:	03/07/2006
Publication #:	US20070212861	Pub Dt:	09/13/2007
Title:	LASER SURFACE ANNEALING OF ANTIMONY DOPED AMORPHIZED SEMICONDUCTOR REGION

Patent #:	7381590	Issue Dt:	06/03/2008	Application #:	11308167	Filing Dt:	03/09/2006
Publication #:	US20070212820	Pub Dt:	09/13/2007
Title:	METHOD AND DEVICE INCLUDING REWORKABLE ALPHA PARTICLE BARRIER AND CORROSION BARRIER

Patent #:	7348648	Issue Dt:	03/25/2008	Application #:	11308220	Filing Dt:	03/13/2006
Publication #:	US20070212870	Pub Dt:	09/13/2007
Title:	INTERCONNECT STRUCTURE WITH A BARRIER-REDUNDANCY FEATURE

Patent #:	7276796	Issue Dt:	10/02/2007	Application #:	11308284	Filing Dt:	03/15/2006
Publication #:	US20070216031	Pub Dt:	09/20/2007
Title:	FORMATION OF OXIDATION-RESISTANT SEED LAYER FOR INTERCONNECT APPLICATIONS

Patent #:	7666721	Issue Dt:	02/23/2010	Application #:	11308292	Filing Dt:	03/15/2006
Publication #:	US20070218603	Pub Dt:	09/20/2007
Title:	IMPROVED SOI SUBSTRATES AND SOI DEVICES, AND METHODS FOR FORMING THE SAME

Patent #:	7375034	Issue Dt:	05/20/2008	Application #:	11308394	Filing Dt:	03/21/2006
Publication #:	US20070221619	Pub Dt:	09/27/2007
Title:	RECESSING TRENCH TO TARGET DEPTH USING FEED FORWARD DATA

Patent #:	8367543	Issue Dt:	02/05/2013	Application #:	11308396	Filing Dt:	03/21/2006
Publication #:	US20070222073	Pub Dt:	09/27/2007
Title:	STRUCTURE AND METHOD TO IMPROVE CURRENT-CARRYING CAPABILITIES OF C4 JOINTS

Patent #:	7294543	Issue Dt:	11/13/2007	Application #:	11308404	Filing Dt:	03/22/2006
Publication #:	US20070222020	Pub Dt:	09/27/2007
Title:	DRAM (DYNAMIC RANDOM ACCESS MEMORY) CELLS

Patent #:	7474107	Issue Dt:	01/06/2009	Application #:	11308407	Filing Dt:	03/22/2006
Publication #:	US20070222470	Pub Dt:	09/27/2007
Title:	BURIED SHORT LOCATION DETERMINATION USING VOLTAGE CONTRAST INSPECTION

Patent #:	7518190	Issue Dt:	04/14/2009	Application #:	11308408	Filing Dt:	03/22/2006
Publication #:	US20070221990	Pub Dt:	09/27/2007
Title:	GROUNDING FRONT-END-OF-LINE STRUCTURES ON A SOI SUBSTRATE

Patent #:	7816253	Issue Dt:	10/19/2010	Application #:	11308422	Filing Dt:	03/23/2006
Publication #:	US20070222081	Pub Dt:	09/27/2007
Title:	SURFACE TREATMENT OF INTER-LAYER DIELECTRIC

Patent #:	7459382	Issue Dt:	12/02/2008	Application #:	11308432	Filing Dt:	03/24/2006
Publication #:	US20070221964	Pub Dt:	09/27/2007
Title:	METHOD OF MAKING FIELD TRANSISTOR WITH REDUCED THICKNESS GATE

Patent #:	7405154	Issue Dt:	07/29/2008	Application #:	11308433	Filing Dt:	03/24/2006
Publication #:	US20070222066	Pub Dt:	09/27/2007
Title:	STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS

Patent #:	NONE	Issue Dt:		Application #:	11308463	Filing Dt:	03/28/2006
Publication #:	US20070238267	Pub Dt:	10/11/2007
Title:	Epitaxy of Silicon-Carbon Substitutional Solid Solutions by Ultra-Fast Annealing of Amorphous Material

Patent #:	7378324	Issue Dt:	05/27/2008	Application #:	11308503	Filing Dt:	03/30/2006
Publication #:	US20070238258	Pub Dt:	10/11/2007
Title:	SELECTIVE LINKS IN SILICON HETERO-JUNCTION BIPOLAR TRANSISTORS USING CARBON DOPING AND METHOD OF FORMING SAME

Patent #:	7492016	Issue Dt:	02/17/2009	Application #:	11308513	Filing Dt:	03/31/2006
Publication #:	US20070228479	Pub Dt:	10/04/2007
Title:	PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS

Patent #:	7442586	Issue Dt:	10/28/2008	Application #:	11308516	Filing Dt:	03/31/2006
Publication #:	US20070228465	Pub Dt:	10/04/2007
Title:	IMPROVED SOI SUBSTRATE AND SOI DEVICE, AND METHOD FOR FORMING THE SAME

Patent #:	7375021	Issue Dt:	05/20/2008	Application #:	11308539	Filing Dt:	04/04/2006
Publication #:	US20070232049	Pub Dt:	10/04/2007
Title:	METHOD AND STRUCTURE FOR ELIMINATING ALUMINUM TERMINAL PAD MATERIAL IN SEMICONDUCTOR DEVICES

Patent #:	7294869	Issue Dt:	11/13/2007	Application #:	11308541	Filing Dt:	04/04/2006
Publication #:	US20070235762	Pub Dt:	10/11/2007
Title:	SILICON GERMANIUM EMITTER

Patent #:	7439135	Issue Dt:	10/21/2008	Application #:	11308542	Filing Dt:	04/04/2006
Publication #:	US20070235801	Pub Dt:	10/11/2007
Title:	SELF-ALIGNED BODY CONTACT FOR SEMICONDCTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME

Patent #:	NONE	Issue Dt:		Application #:	11308604	Filing Dt:	04/11/2006
Publication #:	US20070249133	Pub Dt:	10/25/2007
Title:	CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING

Patent #:	7368393	Issue Dt:	05/06/2008	Application #:	11308672	Filing Dt:	04/20/2006
Publication #:	US20070246442	Pub Dt:	10/25/2007
Title:	CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS

Patent #:	7534667	Issue Dt:	05/19/2009	Application #:	11308685	Filing Dt:	04/21/2006
Publication #:	US20070249126	Pub Dt:	10/25/2007
Title:	A STRUCTURE AND METHOD FOR FABRICATION OF DEEP JUNCTION SILICON-ON-INSULATOR TRANSISTORS

Patent #:	8589949	Issue Dt:	11/19/2013	Application #:	11308768	Filing Dt:	05/01/2006
Publication #:	US20070255529	Pub Dt:	11/01/2007
Title:	PROCESSING MULTIPLE HETEROGENEOUS EVENT TYPES IN A COMPLEX EVENT PROCESSING ENGINE

Patent #:	7436034	Issue Dt:	10/14/2008	Application #:	11311455	Filing Dt:	12/19/2005
Publication #:	US20070138578	Pub Dt:	06/21/2007
Title:	METAL OXYNITRIDE AS A PFET MATERIAL

Patent #:	7417288	Issue Dt:	08/26/2008	Application #:	11311462	Filing Dt:	12/19/2005
Publication #:	US20070138533	Pub Dt:	06/21/2007
Title:	SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES

Patent #:	7594200	Issue Dt:	09/22/2009	Application #:	11311756	Filing Dt:	12/19/2005
Publication #:	US20070157130	Pub Dt:	07/05/2007
Title:	METHOD FOR FINDING MULTI-CYCLE CLOCK GATING

Patent #:	7306853	Issue Dt:	12/11/2007	Application #:	11314307	Filing Dt:	12/21/2005
Publication #:	US20060105181	Pub Dt:	05/18/2006
Title:	PATTERNABLE LOW DIELECTRIC CONSTANT MATERIALS AND THEIR USE IN ULSI INTERCONNECTION

Patent #:	7534710	Issue Dt:	05/19/2009	Application #:	11315691	Filing Dt:	12/22/2005
Publication #:	US20070145347	Pub Dt:	06/28/2007
Title:	COUPLED QUANTUM WELL DEVICES (CQWD) CONTAINING TWO OR MORE DIRECT SELECTIVE CONTACTS AND METHODS OF MAKING SAME

Patent #:	7335577	Issue Dt:	02/26/2008	Application #:	11317042	Filing Dt:	12/22/2005
Publication #:	US20060099775	Pub Dt:	05/11/2006
Title:	CRACK STOP FOR LOW K DIELECTRICS

Patent #:	NONE	Issue Dt:		Application #:	11317285	Filing Dt:	12/22/2005
Publication #:	US20070148939	Pub Dt:	06/28/2007
Title:	Low leakage heterojunction vertical transistors and high performance devices thereof

Patent #:	7170164	Issue Dt:	01/30/2007	Application #:	11317298	Filing Dt:	12/23/2005
Publication #:	US20060099815	Pub Dt:	05/11/2006
Title:	COOLING SYSTEM FOR A SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

Patent #:	7475380	Issue Dt:	01/06/2009	Application #:	11318893	Filing Dt:	12/27/2005
Publication #:	US20060107248	Pub Dt:	05/18/2006
Title:	GENERATING MASK PATTERNS FOR ALTERNATING PHASE-SHIFT MASK LITHOGRAPHY

Patent #:	7432567	Issue Dt:	10/07/2008	Application #:	11320330	Filing Dt:	12/28/2005
Publication #:	US20070148838	Pub Dt:	06/28/2007
Title:	METAL GATE CMOS WITH AT LEAST A SINGLE GATE METAL AND DUAL GATE DIELECTRICS

Patent #:	7638406	Issue Dt:	12/29/2009	Application #:	11320375	Filing Dt:	12/28/2005
Publication #:	US20060105534	Pub Dt:	05/18/2006
Title:	METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR

Patent #:	7430698	Issue Dt:	09/30/2008	Application #:	11323449	Filing Dt:	12/30/2005
Publication #:	US20060242509	Pub Dt:	10/26/2006
Title:	METHOD AND SYSTEM FOR AN ON-CHIP AC SELF-TEST CONTROLLER

Patent #:	7833849	Issue Dt:	11/16/2010	Application #:	11323564	Filing Dt:	12/30/2005
Publication #:	US20070152273	Pub Dt:	07/05/2007
Title:	A METHOD OF FABRICATING A SEMICONDUCTOR STRUCTURE INCLUDING ONE DEVICE REGION HAVING A METAL GATE ELECTRODE LOCATED ATOP A THINNED POLYGATE ELECTRODE

Patent #:	NONE	Issue Dt:		Application #:	11323578	Filing Dt:	12/30/2005
Publication #:	US20070152276	Pub Dt:	07/05/2007
Title:	High performance CMOS circuits, and methods for fabricating the same

Patent #:	8859048	Issue Dt:	10/14/2014	Application #:	11324441	Filing Dt:	01/03/2006
Publication #:	US20080102213	Pub Dt:	05/01/2008
Title:	SELECTIVE PLACEMENT OF CARBON NANOTUBES THROUGH FUNCTIONALIZATION

Patent #:	7489025	Issue Dt:	02/10/2009	Application #:	11325105	Filing Dt:	01/04/2006
Publication #:	US20060113598	Pub Dt:	06/01/2006
Title:	DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH OPTICAL THROUGH VIA CONNECTIONS

Patent #:	7342429	Issue Dt:	03/11/2008	Application #:	11325786	Filing Dt:	01/05/2006
Publication #:	US20060109947	Pub Dt:	05/25/2006
Title:	PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER

Patent #:	7656505	Issue Dt:	02/02/2010	Application #:	11326968	Filing Dt:	01/06/2006
Publication #:	US20060114434	Pub Dt:	06/01/2006
Title:	APPARATUS TO EASILY MEASURE RETICLE BLIND POSITIONING WITH AN EXPOSURE APPARATUS

Patent #:	NONE	Issue Dt:		Application #:	11327256	Filing Dt:	01/06/2006
Publication #:	US20070158739	Pub Dt:	07/12/2007
Title:	Higher performance CMOS on (110) wafers

Patent #:	NONE	Issue Dt:		Application #:	11327675	Filing Dt:	01/06/2006
Publication #:	US20070161214	Pub Dt:	07/12/2007
Title:	High k gate stack on III-V compound semiconductors

Patent #:	7364958	Issue Dt:	04/29/2008	Application #:	11327966	Filing Dt:	01/09/2006
Publication #:	US20060108643	Pub Dt:	05/25/2006
Title:	CMOS ON HYBRID SUBSTRATE WITH DIFFERENT CRYSTAL ORIENTATIONS USING SILICON-TO-SILICON DIRECT WAFER BONDING

Patent #:	7421674	Issue Dt:	09/02/2008	Application #:	11328708	Filing Dt:	01/10/2006
Publication #:	US20060190884	Pub Dt:	08/24/2006
Title:	APPARATUS AND METHOD FOR ANALYZING POST-LAYOUT TIMING CRITICAL PATHS

Patent #:	7435676	Issue Dt:	10/14/2008	Application #:	11328981	Filing Dt:	01/10/2006
Publication #:	US20070161226	Pub Dt:	07/12/2007
Title:	DUAL DAMASCENE PROCESS FLOW ENABLING MINIMAL ULK FILM MODIFICATION AND ENHANCED STACK INTEGRITY

Patent #:	7301183	Issue Dt:	11/27/2007	Application #:	11329072	Filing Dt:	01/11/2006
Publication #:	US20060108582	Pub Dt:	05/25/2006
Title:	ORGANIC FIELD-EFFECT TRANSISTOR AND METHOD OF MAKING SAME BASED ON POLYMERIZABLE SELF-ASSEMBLED MONOLAYERS

Patent #:	7161220	Issue Dt:	01/09/2007	Application #:	11329185	Filing Dt:	01/11/2006
Publication #:	US20060118894	Pub Dt:	06/08/2006
Title:	HIGH SPEED PHOTODIODE WITH A BARRIER LAYER FOR BLOCKING OR ELIMINATING SLOW PHOTONIC CARRIERS AND METHOD FOR FORMING SAME

Patent #:	7821301	Issue Dt:	10/26/2010	Application #:	11329458	Filing Dt:	01/11/2006
Publication #:	US20070159213	Pub Dt:	07/12/2007
Title:	METHOD AND APPARATUS FOR MEASURING AND COMPENSATING FOR STATIC PHASE ERROR IN PHASE LOCKED LOOPS

Patent #:	7101782	Issue Dt:	09/05/2006	Application #:	11329550	Filing Dt:	01/11/2006
Publication #:	US20060115974	Pub Dt:	06/01/2006
Title:	METHOD OF MAKING A CIRCUITIZED SUBSTRATE

Patent #:	7521377	Issue Dt:	04/21/2009	Application #:	11329560	Filing Dt:	01/11/2006
Publication #:	US20070161256	Pub Dt:	07/12/2007
Title:	SICOH FILM PREPARATION USING PRECURSORS WITH BUILT-IN POROGEN FUNCTIONALITY

Patent #:	7479418	Issue Dt:	01/20/2009	Application #:	11329643	Filing Dt:	01/11/2006
Publication #:	US20070158747	Pub Dt:	07/12/2007
Title:	METHODS OF APPLYING SUBSTRATE BIAS TO SOI CMOS CIRCUITS

Patent #:	7479701	Issue Dt:	01/20/2009	Application #:	11330203	Filing Dt:	01/12/2006
Publication #:	US20060118960	Pub Dt:	06/08/2006
Title:	DUMMY METAL FILL SHAPES FOR IMPROVED RELIABILITY OF HYBRID OXIDE/LOW-K DIELECTRICS

Patent #:	7517718	Issue Dt:	04/14/2009	Application #:	11330291	Filing Dt:	01/12/2006
Publication #:	US20070160747	Pub Dt:	07/12/2007
Title:	METHOD FOR FABRICATING AN INORGANIC NANOCOMPOSITE

Patent #:	7446040	Issue Dt:	11/04/2008	Application #:	11330537	Filing Dt:	01/12/2006
Publication #:	US20070161239	Pub Dt:	07/12/2007
Title:	STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING

Patent #:	7257042	Issue Dt:	08/14/2007	Application #:	11330539	Filing Dt:	01/12/2006
Publication #:	US20070159902	Pub Dt:	07/12/2007
Title:	ENHANCED SENSING IN A HIERARCHICAL MEMORY ARCHITECTURE

Patent #:	7135595	Issue Dt:	11/14/2006	Application #:	11330659	Filing Dt:	01/12/2006
Publication #:	US20060128914	Pub Dt:	06/15/2006
Title:	PHOTORESIST COMPOSITION

Patent #:	NONE	Issue Dt:		Application #:	11330688	Filing Dt:	01/12/2006
Publication #:	US20070158779	Pub Dt:	07/12/2007
Title:	Methods and semiconductor structures for latch-up suppression using a buried damage layer

Patent #:	7305325	Issue Dt:	12/04/2007	Application #:	11330823	Filing Dt:	01/12/2006
Publication #:	US20070162257	Pub Dt:	07/12/2007
Title:	METHOD TO IMPROVE REQUIREMENTS, DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING INDUSTRIES THROUGH ANALYSIS OF DEFECT DATA

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100

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Title:	DEFLECTION ANALYSIS SYSTEM AND METHOD FOR CIRCUIT DESIGN

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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