|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11472774
|
Filing Dt:
|
06/22/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11472775
|
Filing Dt:
|
06/22/2006
|
Publication #:
|
|
Pub Dt:
|
04/05/2007
| | | | |
Title:
|
Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11472776
|
Filing Dt:
|
06/22/2006
|
Publication #:
|
|
Pub Dt:
|
05/17/2007
| | | | |
Title:
|
Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11472959
|
Filing Dt:
|
06/22/2006
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
Title:
|
Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11472982
|
Filing Dt:
|
06/22/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
Patterns of electrically conducting polymers and their application as electrodes or electrical contacts
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
11473338
|
Filing Dt:
|
06/23/2006
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
GRADED SPIN-ON ORGANIC ANTIREFLECTIVE COATING FOR PHOTOLITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
11473757
|
Filing Dt:
|
06/23/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
ULTRA THIN BODY FULLY-DEPLETED SOI MOSFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11473835
|
Filing Dt:
|
06/23/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
STRUCTURE FOR PLANAR SOI SUBSTRATE WITH MULTIPLE ORIENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
11474678
|
Filing Dt:
|
06/26/2006
|
Publication #:
|
|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
METHOD FOR HIGH DENSITY DATA STORAGE AND READ-BACK
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11474774
|
Filing Dt:
|
06/26/2006
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
Title:
|
SUBSTRATE ENGINEERING FOR OPTIMUM CMOS DEVICE PERFORMANCE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11475496
|
Filing Dt:
|
06/27/2006
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
CONTROLLING COMPUTER STORAGE SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
11477664
|
Filing Dt:
|
06/30/2006
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
METHOD OF PREPARING AN EXTENED CONJUGATED MOLECULAR ASSEMBLY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11477707
|
Filing Dt:
|
06/29/2006
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
Semiconductor device structures (gate stacks) with charge compositions
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
11478201
|
Filing Dt:
|
06/29/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
SEEDLESS WIREBOND PAD PLATING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11479485
|
Filing Dt:
|
06/30/2006
|
Publication #:
|
|
Pub Dt:
|
01/03/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR AUTOMATIC UNCERTAINTY-BASED MANAGEMENT FEEDBACK CONTROLLER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11481019
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
Methods to form SiCOH or SiCNH dielectrics and structures including the same
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11481020
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
A METHOD FOR RECONFIGURING CACHE MEMORY BASED ON AT LEAST ANALYSIS OF HEAT GENERATED DURING RUNTIME, AT LEAST BY ASSOCIATING AN ACCESS BIT WITH A CACHE LINE AND ASSOCIATING A GRANULARITY BIT WITH A CACHE LINE IN LEVEL-2 CACHE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11481070
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH MINIMIZED PARASITICS AND METHOD OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11481120
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
CONCURRENT FIN-FET AND THICK BODY DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11481514
|
Filing Dt:
|
07/06/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
TRENCH TYPE BURIED ON-CHIP PRECISION PROGRAMMABLE RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11481525
|
Filing Dt:
|
07/06/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
METHOD FOR FABRICATING SIGE-ON-INSULATOR (SGOI) AND GE-ON-INSULATOR (GOI) SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11481532
|
Filing Dt:
|
07/06/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
NITRIDE-ENCAPSULATED FET (NNCFET)
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
11482688
|
Filing Dt:
|
07/07/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
METHOD OF FORMING A HIGH IMPEDANCE ANTIFUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11483117
|
Filing Dt:
|
07/06/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
RANDOM ACCESS MEMORY WITH STABILITY ENHANCEMENT AND EARLY READY ELIMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
11485390
|
Filing Dt:
|
07/13/2006
|
Title:
|
INTEGRATED CMOS SPECTRUM ANALYZER FOR ON-CHIP DIAGNOSTICS USING DIGITAL AUTOCORRELATION OF COARSELY QUANTIZED SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11485599
|
Filing Dt:
|
07/12/2006
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
METHOD OF FORMING AN INTEGRATED SOI FINGERED DECOUPLING CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11487196
|
Filing Dt:
|
07/14/2006
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
WRITE FILTER CACHE METHOD AND APPARATUS FOR PROTECTING THE MICROPROCESSOR CORE FROM SOFT ERRORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11488242
|
Filing Dt:
|
07/18/2006
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING HIGH-Q WAFER BACKSIDE INDUCTORS AND METHODS OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11490248
|
Filing Dt:
|
07/21/2006
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11490326
|
Filing Dt:
|
07/20/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD OF FABRICATING A VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BICMOS WITH REDUCED BURIED OXIDE THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11491216
|
Filing Dt:
|
07/21/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
PACKAGING RELIABILITY SUPER CHIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
11491701
|
Filing Dt:
|
07/24/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
HIGH SPEED LATCH CIRCUITS USING GATED DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11491721
|
Filing Dt:
|
07/24/2006
|
Publication #:
|
|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
FUSE/ANTI-FUSE STRUCTURE AND METHODS OF MAKING AND PROGRAMMING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11491816
|
Filing Dt:
|
07/24/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
LINE LEVEL AIR GAPS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11492271
|
Filing Dt:
|
07/25/2006
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2009
|
Application #:
|
11492276
|
Filing Dt:
|
07/25/2006
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
Title:
|
BILAYER FILM INCLUDING AN UNDERLAYER HAVING VERTICAL ACID TRANSPORT PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11492455
|
Filing Dt:
|
07/25/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD OF FABRICATING STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING UNDERLAPPED DUAL LINERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11492456
|
Filing Dt:
|
07/25/2006
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
Title:
|
METHOD OF FORMING CONTACT FOR DUAL LINER PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11493724
|
Filing Dt:
|
07/26/2006
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
NEW FLUX COMPOSITION AND PROCESS FOR USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
11494195
|
Filing Dt:
|
07/27/2006
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
TECHNIQUES FOR USE OF NANOTECHNOLOGY IN PHOTOVOLTAICS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11495038
|
Filing Dt:
|
07/28/2006
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
METHOD FOR USING COMPOSITIONS CONTAINING FLUOROCARBINOLS IN LITHOGRAPHIC PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11495335
|
Filing Dt:
|
07/28/2006
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
DISPENSER SYSTEM FOR ATOMIC BEAM ASSISTED METAL ORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD)
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11495336
|
Filing Dt:
|
07/28/2006
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
Title:
|
SYSTEM AND METHODS FOR QUANTITATIVELY EVALUATING COMPLEXITY OF COMPUTING SYSTEM CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
11495518
|
Filing Dt:
|
07/31/2006
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11496120
|
Filing Dt:
|
07/31/2006
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
THREE-DIMENSIONAL CASCADED POWER DISTRIBUTION IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11496153
|
Filing Dt:
|
07/31/2006
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
PIN GRID ARRAY ZERO INSERTION FORCE CONNECTORS CONFIGURABLE FOR SUPPORTING LARGE PIN COUNTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
11496383
|
Filing Dt:
|
07/31/2006
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
Title:
|
ULTRA-SENSITIVE DETECTION TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11496542
|
Filing Dt:
|
08/01/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11498009
|
Filing Dt:
|
08/01/2006
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
Title:
|
POWER GATING TECHNIQUES ABLE TO HAVE DATA RETENTION AND VARIABILITY IMMUNITY PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11498689
|
Filing Dt:
|
08/03/2006
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
VERSATILE SI-BASED PACKAGING WITH INTEGRATED PASSIVE COMPONENTS FOR MMWAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2009
|
Application #:
|
11499132
|
Filing Dt:
|
08/03/2006
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
DIELECTRIC NANOSTRUCTURE AND METHOD FOR ITS MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11499220
|
Filing Dt:
|
08/04/2006
|
Publication #:
|
|
Pub Dt:
|
06/28/2007
| | | | |
Title:
|
STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2008
|
Application #:
|
11500254
|
Filing Dt:
|
08/07/2006
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
SELECTIVE IMPLEMENTATION OF BARRIER LAYERS TO ACHIEVE THRESHOLD VOLTAGE CONTROL IN CMOS DEVICE FABRICATION WITH HIGH K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
11501186
|
Filing Dt:
|
08/07/2006
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
FLUORINATED VINYL ETHERS, COPOLYMERS THEREOF, AND USE IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
11502132
|
Filing Dt:
|
08/09/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
IMPLANT DAMAGE CONTROL BY IN-SITU C DOPING DURING SIGE EPITAXY FOR DEVICE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11502196
|
Filing Dt:
|
08/10/2006
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
STRUCTURE FOR DETERMINING THERMAL CYCLE RELIABILITY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11502380
|
Filing Dt:
|
08/10/2006
|
Publication #:
|
|
Pub Dt:
|
02/14/2008
| | | | |
Title:
|
Multipath soldered thermal interface between a chip and its heat sink
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2009
|
Application #:
|
11503200
|
Filing Dt:
|
08/11/2006
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR INCREMENTAL STATISTICAL TIMING ANALYSIS OF DIGITAL CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11503259
|
Filing Dt:
|
08/14/2006
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
INTERCONNECT STRUCTURES WITH ENCASING CAP AND METHODS OF MAKING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11503356
|
Filing Dt:
|
08/10/2006
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
FLUORINATED VINYL ETHERS, COPOLYMERS THEREOF, AND USE IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11505224
|
Filing Dt:
|
08/16/2006
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
FINFET drive strength de-quantization using multiple orientation fins
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11506227
|
Filing Dt:
|
08/18/2006
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
TRILAYER RESIST SCHEME FOR GATE ETCHING APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11506827
|
Filing Dt:
|
08/21/2006
|
Publication #:
|
|
Pub Dt:
|
05/03/2007
| | | | |
Title:
|
HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11507308
|
Filing Dt:
|
08/21/2006
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
LOW LATENCY COUNTER EVENT INDICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11510039
|
Filing Dt:
|
08/25/2006
|
Publication #:
|
|
Pub Dt:
|
04/19/2007
| | | | |
Title:
|
Stability enhancement of opto-electronic devices
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2009
|
Application #:
|
11511680
|
Filing Dt:
|
08/29/2006
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
THIN FILM PHASE CHANGE MEMORY CELL FORMED ON SILICON-ON-INSULATOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
11511815
|
Filing Dt:
|
08/29/2006
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
THROUGH BOARD STACKING OF MULTIPLE LGA-CONNECTED COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11512014
|
Filing Dt:
|
08/29/2006
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
ELECTRICAL COMPONENT TUNED BY CONDUCTIVE LAYER DELETION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11513101
|
Filing Dt:
|
08/30/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
Method of forming metal/high-k gate stacks with high mobility
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
11513786
|
Filing Dt:
|
08/31/2006
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
COMPLIANT VAPOR CHAMBER CHIP PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11513862
|
Filing Dt:
|
08/31/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
FIELD EFFECT DEVICE WITH A CHANNEL WITH A SWITCHABLE CONDUCTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11514605
|
Filing Dt:
|
09/01/2006
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
METHOD OF FORMING SELF-ALIGNED LOW-K GATE CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11515910
|
Filing Dt:
|
09/06/2006
|
Publication #:
|
|
Pub Dt:
|
03/29/2007
| | | | |
Title:
|
SERVO SYSTEM FOR A TWO-DIMENSIONAL MICRO-ELECTROMECHANICAL SYSTEM (MEMS)-BASED SCANNER AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
11516208
|
Filing Dt:
|
09/06/2006
|
Publication #:
|
|
Pub Dt:
|
03/06/2008
| | | | |
Title:
|
VERTICAL FIELD EFFECT TRANSISTOR ARRAYS AND METHODS FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
11518110
|
Filing Dt:
|
09/08/2006
|
Publication #:
|
|
Pub Dt:
|
03/22/2007
| | | | |
Title:
|
DEVICE AND METHOD FOR SENSING TOPOGRAPHICAL VARIATIONS ON A SURFACE USING A PROBE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11518773
|
Filing Dt:
|
09/11/2006
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
METHOD TO GENERATE AIRGAPS WITH A TEMPLATE FIRST SCHEME AND A SELF ALIGNED BLOCKOUT MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
11519176
|
Filing Dt:
|
09/11/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
11519393
|
Filing Dt:
|
09/12/2006
|
Publication #:
|
|
Pub Dt:
|
04/17/2008
| | | | |
Title:
|
THERMALLY EXCITED NEAR-FIELD SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11519617
|
Filing Dt:
|
09/12/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR EMPLOYING PATTERNING PROCESS STATISTICS FOR GROUND RULES WAIVERS AND OPTIMIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11519680
|
Filing Dt:
|
09/12/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
CHARGE MODULATION NETWORK FOR MULTIPLE POWER DOMAINS FOR SILICON-ON-INSULATOR TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11521917
|
Filing Dt:
|
09/16/2006
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR PRE-COMPILE PROCESSING OF HARDWARE DESIGN LANGUAGE (HDL) SOURCE FILES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
11522036
|
Filing Dt:
|
09/16/2006
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
SYNTHESIZING VHDL MULTIPLE WAIT BEHAVIORAL FSMS INTO RT LEVEL FSMS BY PREPROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11522623
|
Filing Dt:
|
09/18/2006
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11522873
|
Filing Dt:
|
09/18/2006
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
CIRCUITS AND METHODS FOR HIGH-EFFICIENCY ON-CHIP POWER DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2008
|
Application #:
|
11522905
|
Filing Dt:
|
09/19/2006
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11524598
|
Filing Dt:
|
09/21/2006
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
Title:
|
INTEGRATED SPECTRUM ANALYZER CIRCUITS AND METHODS FOR PROVIDING ON-CHIP DIAGNOSTICS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11526943
|
Filing Dt:
|
09/26/2006
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
Title:
|
HETERO DIELS-ALDER ADDUCTS OF PENTACENE AS SOLUBLE PRECURSORS OF PENTACENE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11527343
|
Filing Dt:
|
09/26/2006
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
Title:
|
ANTIFUSE STRUCTURE AND SYSTEM FOR CLOSING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11530038
|
Filing Dt:
|
09/08/2006
|
Publication #:
|
|
Pub Dt:
|
04/12/2007
| | | | |
Title:
|
METHOD AND PLACEMENT TOOL FOR DESIGNING THE LAYOUT OF AN ELECTRONIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11530100
|
Filing Dt:
|
09/08/2006
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11530544
|
Filing Dt:
|
09/11/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
ASSIGNING CLOCK ARRIVAL TIME FOR NOISE REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2009
|
Application #:
|
11530981
|
Filing Dt:
|
09/12/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11531050
|
Filing Dt:
|
09/12/2006
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11531298
|
Filing Dt:
|
09/13/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
METHOD AND STRUCTURE FOR INTEGRATING MIM CAPACITORS WITHIN DUAL DAMASCENE PROCESSING TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11531372
|
Filing Dt:
|
09/13/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
STRESSED SEMICONDUCTOR DEVICE STRUCTURES HAVING GRANULAR SEMICONDUCTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11531398
|
Filing Dt:
|
09/13/2006
|
Publication #:
|
|
Pub Dt:
|
03/13/2008
| | | | |
Title:
|
SEMI-FLATTENED PIN OPTIMIZATION PROCESS FOR HIERARCHICAL PHYSICAL DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11531708
|
Filing Dt:
|
09/14/2006
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR IMPROVED LOGIC SIMULATION USING A NEGATIVE UNKNOWN BOOLEAN STATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11531714
|
Filing Dt:
|
09/14/2006
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
11532207
|
Filing Dt:
|
09/15/2006
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11532216
|
Filing Dt:
|
09/15/2006
|
Publication #:
|
|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
UNROLLING HARDWARE DESIGN GENERATE STATEMENTS IN A SOURCE WINDOW DEBUGGER
|
|