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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 60 of 148
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Patent #:	NONE	Issue Dt:		Application #:	11846294	Filing Dt:	08/28/2007
Publication #:	US20090064075	Pub Dt:	03/05/2009
Title:	SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR SCHEMATIC EDITOR MULIT-WINDOW ENHANCEMENT OF HIERARCHICAL INTEGRATED CIRCUIT DESIGN

Patent #:	7763531	Issue Dt:	07/27/2010	Application #:	11846544	Filing Dt:	08/29/2007
Publication #:	US20070292996	Pub Dt:	12/20/2007
Title:	METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING

Patent #:	7831935	Issue Dt:	11/09/2010	Application #:	11846578	Filing Dt:	08/29/2007
Publication #:	US20080024197	Pub Dt:	01/31/2008
Title:	METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE

Patent #:	7382055	Issue Dt:	06/03/2008	Application #:	11846595	Filing Dt:	08/29/2007
Publication #:	US20070290272	Pub Dt:	12/20/2007
Title:	INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT

Patent #:	7888736	Issue Dt:	02/15/2011	Application #:	11846825	Filing Dt:	08/29/2007
Publication #:	US20090057781	Pub Dt:	03/05/2009
Title:	MUGFET WITH OPTIMIZED FILL STRUCTURES

Patent #:	7925614	Issue Dt:	04/12/2011	Application #:	11847203	Filing Dt:	08/29/2007
Publication #:	US20070295954	Pub Dt:	12/27/2007
Title:	METHOD AND STRUCTURE TO ISOLATE A QUBIT FROM THE ENVIRONMENT

Patent #:	7705626	Issue Dt:	04/27/2010	Application #:	11847362	Filing Dt:	08/30/2007
Publication #:	US20080030254	Pub Dt:	02/07/2008
Title:	DESIGN STRUCTURE TO ELIMINATE STEP RESPONSE POWER SUPPLY PERTURBATION

Patent #:	7851885	Issue Dt:	12/14/2010	Application #:	11847379	Filing Dt:	08/30/2007
Publication #:	US20100237460	Pub Dt:	09/23/2010
Title:	METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES

Patent #:	7465649	Issue Dt:	12/16/2008	Application #:	11847384	Filing Dt:	08/30/2007
Publication #:	US20070293031	Pub Dt:	12/20/2007
Title:	A METHOD OF FORMING A SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK

Patent #:	7853443	Issue Dt:	12/14/2010	Application #:	11847391	Filing Dt:	08/30/2007
Publication #:	US20080004854	Pub Dt:	01/03/2008
Title:	TRANSIENT SIMULATION USING ADAPTIVE PIECEWISE CONSTANT MODEL

Patent #:	7795724	Issue Dt:	09/14/2010	Application #:	11847606	Filing Dt:	08/30/2007
Publication #:	US20090057865	Pub Dt:	03/05/2009
Title:	SANDWICHED ORGANIC LGA STRUCTURE

Patent #:	NONE	Issue Dt:		Application #:	11847608	Filing Dt:	08/30/2007
Publication #:	US20080042140	Pub Dt:	02/21/2008
Title:	THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN

Patent #:	7704876	Issue Dt:	04/27/2010	Application #:	11847657	Filing Dt:	08/30/2007
Publication #:	US20080026566	Pub Dt:	01/31/2008
Title:	DUAL DAMASCENE INTERCONNECT STRUCTURES HAVING DIFFERENT MATERIALS FOR LINE AND VIA CONDUCTORS

Patent #:	7714452	Issue Dt:	05/11/2010	Application #:	11847776	Filing Dt:	08/30/2007
Publication #:	US20070290345	Pub Dt:	12/20/2007
Title:	STRUCTURE AND METHOD FOR PRODUCING MULTIPLE SIZE INTERCONNECTIONS

Patent #:	8901566	Issue Dt:	12/02/2014	Application #:	11848268	Filing Dt:	08/31/2007
Publication #:	US20070296038	Pub Dt:	12/27/2007
Title:	HIGH PERFORMANCE STRESS-ENHANCED MOSFETS USING SI:C AND SIGE EPITAXIAL SOURCE/DRAIN AND METHOD OF MANUFACTURE

Patent #:	7429877	Issue Dt:	09/30/2008	Application #:	11848470	Filing Dt:	08/31/2007
Publication #:	US20080186054	Pub Dt:	08/07/2008
Title:	DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH

Patent #:	7769577	Issue Dt:	08/03/2010	Application #:	11848489	Filing Dt:	08/31/2007
Publication #:	US20070294071	Pub Dt:	12/20/2007
Title:	HARDWARE ACCELERATOR WITH A SINGLE PARATITION FOR LATCHES AND COMBINATIONAL LOGIC

Patent #:	7711784	Issue Dt:	05/04/2010	Application #:	11848585	Filing Dt:	08/31/2007
Publication #:	US20070294358	Pub Dt:	12/20/2007
Title:	AUTONOMIC E-MAIL PROCESSING SYSTEM AND METHOD

Patent #:	8039888	Issue Dt:	10/18/2011	Application #:	11848597	Filing Dt:	08/31/2007
Publication #:	US20080272398	Pub Dt:	11/06/2008
Title:	CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING

Patent #:	7885365	Issue Dt:	02/08/2011	Application #:	11848599	Filing Dt:	08/31/2007
Publication #:	US20090060091	Pub Dt:	03/05/2009
Title:	LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE

Patent #:	7592685	Issue Dt:	09/22/2009	Application #:	11849048	Filing Dt:	08/31/2007
Publication #:	US20080038915	Pub Dt:	02/14/2008
Title:	DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES

Patent #:	7827514	Issue Dt:	11/02/2010	Application #:	11849346	Filing Dt:	09/03/2007
Publication #:	US20070300191	Pub Dt:	12/27/2007
Title:	EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES

Patent #:	7843069	Issue Dt:	11/30/2010	Application #:	11849409	Filing Dt:	09/04/2007
Publication #:	US20090057908	Pub Dt:	03/05/2009
Title:	WIRE BOND PADS

Patent #:	7984329	Issue Dt:	07/19/2011	Application #:	11849452	Filing Dt:	09/04/2007
Publication #:	US20090063896	Pub Dt:	03/05/2009
Title:	SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE

Patent #:	7707535	Issue Dt:	04/27/2010	Application #:	11849461	Filing Dt:	09/04/2007
Publication #:	US20080209382	Pub Dt:	08/28/2008
Title:	STITCHED IC CHIP LAYOUT DESIGN STRUCTURE

Patent #:	7631154	Issue Dt:	12/08/2009	Application #:	11849548	Filing Dt:	09/04/2007
Publication #:	US20080046620	Pub Dt:	02/21/2008
Title:	HANDLING OF THE TRANSMIT ENABLE SIGNAL IN A DYNAMIC RANDOM ACCESS MEMORY CONTROLLER

Patent #:	NONE	Issue Dt:		Application #:	11849550	Filing Dt:	09/04/2007
Publication #:	US20080229269	Pub Dt:	09/18/2008
Title:	DESIGN STRUCTURE FOR INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES

Patent #:	7784012	Issue Dt:	08/24/2010	Application #:	11849908	Filing Dt:	09/04/2007
Publication #:	US20080010626	Pub Dt:	01/10/2008
Title:	SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR USE IN CIRCUIT DESIGNS

Patent #:	7816219	Issue Dt:	10/19/2010	Application #:	11850076	Filing Dt:	09/05/2007
Publication #:	US20070298572	Pub Dt:	12/27/2007
Title:	FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE AND/OR STAIRCASE SILICIDE

Patent #:	NONE	Issue Dt:		Application #:	11850347	Filing Dt:	09/05/2007
Publication #:	US20090058473	Pub Dt:	03/05/2009
Title:	ACTIVE PRE-EMPHASIS FOR PASSIVE RC NETWORKS

Patent #:	7825000	Issue Dt:	11/02/2010	Application #:	11850427	Filing Dt:	09/05/2007
Publication #:	US20090059656	Pub Dt:	03/05/2009
Title:	METHOD FOR INTEGRATION OF MAGNETIC RANDOM ACCESS MEMORIES WITH IMPROVED LITHOGRAPHIC ALIGNMENT TO MAGNETIC TUNNEL JUNCTIONS

Patent #:	7791972	Issue Dt:	09/07/2010	Application #:	11850477	Filing Dt:	09/05/2007
Publication #:	US20080104551	Pub Dt:	05/01/2008
Title:	DESIGN STRUCTURE FOR PROVIDING OPTIMAL FIELD PROGRAMMING OF ELECTRONIC FUSES

Patent #:	7825469	Issue Dt:	11/02/2010	Application #:	11850488	Filing Dt:	09/05/2007
Publication #:	US20090057804	Pub Dt:	03/05/2009
Title:	THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS

Patent #:	7795677	Issue Dt:	09/14/2010	Application #:	11850608	Filing Dt:	09/05/2007
Publication #:	US20090057762	Pub Dt:	03/05/2009
Title:	NANOWIRE FIELD-EFFECT TRANSISTORS

Patent #:	7534675	Issue Dt:	05/19/2009	Application #:	11850644	Filing Dt:	09/05/2007
Publication #:	US20090061568	Pub Dt:	03/05/2009
Title:	TECHNIQUES FOR FABRICATING NANOWIRE FIELD-EFFECT TRANSISTORS

Patent #:	7716619	Issue Dt:	05/11/2010	Application #:	11850691	Filing Dt:	09/06/2007
Publication #:	US20080022243	Pub Dt:	01/24/2008
Title:	DESIGN STRUCTURE FOR IMPLEMENTING DYNAMIC DATA PATH WITH INTERLOCKED KEEPER AND RESTORE DEVICES

Patent #:	7639046	Issue Dt:	12/29/2009	Application #:	11850736	Filing Dt:	09/06/2007
Publication #:	US20080169841	Pub Dt:	07/17/2008
Title:	METHOD TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT

Patent #:	7633079	Issue Dt:	12/15/2009	Application #:	11850742	Filing Dt:	09/06/2007
Publication #:	US20090065761	Pub Dt:	03/12/2009
Title:	PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL

Patent #:	7735038	Issue Dt:	06/08/2010	Application #:	11850745	Filing Dt:	09/06/2007
Publication #:	US20080169842	Pub Dt:	07/17/2008
Title:	DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS CIRCUIT AND CLOCK GATED SYNCHRONOUS CIRCUIT

Patent #:	7464217	Issue Dt:	12/09/2008	Application #:	11850840	Filing Dt:	09/06/2007
Publication #:	US20080055956	Pub Dt:	03/06/2008
Title:	DESIGN STRUCTURE FOR CONTENT ADDRESSABLE MEMORY

Patent #:	7884018	Issue Dt:	02/08/2011	Application #:	11850916	Filing Dt:	09/06/2007
Publication #:	US20080315429	Pub Dt:	12/25/2008
Title:	METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS

Patent #:	7525162	Issue Dt:	04/28/2009	Application #:	11850933	Filing Dt:	09/06/2007
Publication #:	US20090065867	Pub Dt:	03/12/2009
Title:	ORIENTATION-OPTIMIZED PFETS IN CMOS DEVICES EMPLOYING DUAL STRESS LINERS

Patent #:	7928571	Issue Dt:	04/19/2011	Application #:	11850968	Filing Dt:	09/06/2007
Publication #:	US20070296044	Pub Dt:	12/27/2007
Title:	DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS

Patent #:	7724565	Issue Dt:	05/25/2010	Application #:	11850992	Filing Dt:	09/06/2007
Publication #:	US20080002497	Pub Dt:	01/03/2008
Title:	APPARATUS AND METHOD FOR SMALL SIGNAL SENSING IN AN SRAM CELL UTILIZING PFET ACCESS DEVICES

Patent #:	7892940	Issue Dt:	02/22/2011	Application #:	11851123	Filing Dt:	09/06/2007
Publication #:	US20080038923	Pub Dt:	02/14/2008
Title:	DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES

Patent #:	7904658	Issue Dt:	03/08/2011	Application #:	11851128	Filing Dt:	09/06/2007
Publication #:	US20080040547	Pub Dt:	02/14/2008
Title:	STRUCTURE FOR POWER-EFFICIENT CACHE MEMORY

Patent #:	7471114	Issue Dt:	12/30/2008	Application #:	11851133	Filing Dt:	09/06/2007
Publication #:	US20080169839	Pub Dt:	07/17/2008
Title:	A DESIGN STRUCTURE FOR A CURRENT CONTROL MECHANISM FOR POWER NETWORKS AND DYNAMIC LOGIC KEEPER CIRCUITS

Patent #:	7839206	Issue Dt:	11/23/2010	Application #:	11851138	Filing Dt:	09/06/2007
Publication #:	US20080169867	Pub Dt:	07/17/2008
Title:	DESIGN STRUCTURE FOR LOW VOLTAGE APPLICATIONS IN AN INTEGRATED CIRCUIT

Patent #:	7531386	Issue Dt:	05/12/2009	Application #:	11851169	Filing Dt:	09/06/2007
Publication #:	US20080142952	Pub Dt:	06/19/2008
Title:	SEMICONDUCTOR PACKAGE

Patent #:	NONE	Issue Dt:		Application #:	11851408	Filing Dt:	09/07/2007
Publication #:	US20080273366	Pub Dt:	11/06/2008
Title:	DESIGN STRUCTURE FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY

Patent #:	7569489	Issue Dt:	08/04/2009	Application #:	11851464	Filing Dt:	09/07/2007
Publication #:	US20070298552	Pub Dt:	12/27/2007
Title:	HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING

Patent #:	7457187	Issue Dt:	11/25/2008	Application #:	11851613	Filing Dt:	09/07/2007
Publication #:	US20080062783	Pub Dt:	03/13/2008
Title:	DESIGN STRUCTURE FOR REDUNDANT ARRAY REPAIR IN INTEGRATED CIRCUITS DURING OPERATION

Patent #:	8053810	Issue Dt:	11/08/2011	Application #:	11851858	Filing Dt:	09/07/2007
Publication #:	US20090067463	Pub Dt:	03/12/2009
Title:	STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME

Patent #:	7713789	Issue Dt:	05/11/2010	Application #:	11852317	Filing Dt:	09/09/2007
Publication #:	US20080017978	Pub Dt:	01/24/2008
Title:	SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY

Patent #:	7939823	Issue Dt:	05/10/2011	Application #:	11852353	Filing Dt:	09/10/2007
Publication #:	US20090065955	Pub Dt:	03/12/2009
Title:	METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING

Patent #:	7776732	Issue Dt:	08/17/2010	Application #:	11852359	Filing Dt:	09/10/2007
Publication #:	US20090065876	Pub Dt:	03/12/2009
Title:	METAL HIGH-K TRANSISTOR HAVING SILICON SIDEWALL FOR REDUCED PARASITIC CAPACITANCE, AND PROCESS TO FABRICATE SAME

Patent #:	7989229	Issue Dt:	08/02/2011	Application #:	11852493	Filing Dt:	09/10/2007
Publication #:	US20090068770	Pub Dt:	03/12/2009
Title:	TACTILE SURFACE INSPECTION DURING DEVICE FABRICATION OR ASSEMBLY

Patent #:	NONE	Issue Dt:		Application #:	11852507	Filing Dt:	09/10/2007
Publication #:	US20090065804	Pub Dt:	03/12/2009
Title:	BIPOLAR TRANSISTOR WITH LOW RESISTANCE BASE CONTACT AND METHOD OF MAKING THE SAME

Patent #:	7919379	Issue Dt:	04/05/2011	Application #:	11852906	Filing Dt:	09/10/2007
Publication #:	US20090065817	Pub Dt:	03/12/2009
Title:	DIELECTRIC SPACER REMOVAL

Patent #:	7388261	Issue Dt:	06/17/2008	Application #:	11853040	Filing Dt:	09/11/2007
Publication #:	US20070296011	Pub Dt:	12/27/2007
Title:	STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT

Patent #:	7408229	Issue Dt:	08/05/2008	Application #:	11853045	Filing Dt:	09/11/2007
Publication #:	US20070296012	Pub Dt:	12/27/2007
Title:	STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT

Patent #:	7723851	Issue Dt:	05/25/2010	Application #:	11853118	Filing Dt:	09/11/2007
Publication #:	US20090065941	Pub Dt:	03/12/2009
Title:	METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS

Patent #:	7704869	Issue Dt:	04/27/2010	Application #:	11853139	Filing Dt:	09/11/2007
Publication #:	US20090068835	Pub Dt:	03/12/2009
Title:	METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS

Patent #:	8006221	Issue Dt:	08/23/2011	Application #:	11853170	Filing Dt:	09/11/2007
Publication #:	US20090070629	Pub Dt:	03/12/2009
Title:	SYSTEM AND METHOD FOR TESTING MULTIPLE PROCESSOR MODES FOR PROCESSOR DESIGN VERIFICATION AND VALIDATION

Patent #:	7955921	Issue Dt:	06/07/2011	Application #:	11853284	Filing Dt:	09/11/2007
Publication #:	US20090065872	Pub Dt:	03/12/2009
Title:	FULL SILICIDE GATE FOR CMOS

Patent #:	7725864	Issue Dt:	05/25/2010	Application #:	11854000	Filing Dt:	09/12/2007
Publication #:	US20080059918	Pub Dt:	03/06/2008
Title:	SYSTEMATIC YIELD IN SEMICONDUCTOR MANUFACTURE

Patent #:	7847683	Issue Dt:	12/07/2010	Application #:	11854035	Filing Dt:	09/12/2007
Publication #:	US20090066502	Pub Dt:	03/12/2009
Title:	EMERGENCY MACHINE OFF FEATURE WITH SAFETY CONTROL INTERFACE

Patent #:	7550338	Issue Dt:	06/23/2009	Application #:	11854829	Filing Dt:	09/13/2007
Publication #:	US20080003735	Pub Dt:	01/03/2008
Title:	METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES

Patent #:	7863089	Issue Dt:	01/04/2011	Application #:	11855325	Filing Dt:	09/14/2007
Publication #:	US20080045052	Pub Dt:	02/21/2008
Title:	PLANAR ARRAY CONTACT MEMORY CARDS

Patent #:	7904286	Issue Dt:	03/08/2011	Application #:	11855345	Filing Dt:	09/14/2007
Publication #:	US20090077441	Pub Dt:	03/19/2009
Title:	METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT

Patent #:	7566959	Issue Dt:	07/28/2009	Application #:	11855356	Filing Dt:	09/14/2007
Publication #:	US20080001275	Pub Dt:	01/03/2008
Title:	PLANAR ARRAY CONTACT MEMORY CARDS

Patent #:	7425256	Issue Dt:	09/16/2008	Application #:	11855507	Filing Dt:	09/14/2007
Publication #:	US20080000777	Pub Dt:	01/03/2008
Title:	SELECTIVE SHIELD/MATERIAL FLOW MECHANISM

Patent #:	7642125	Issue Dt:	01/05/2010	Application #:	11855979	Filing Dt:	09/14/2007
Publication #:	US20090072215	Pub Dt:	03/19/2009
Title:	PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING

Patent #:	8178386	Issue Dt:	05/15/2012	Application #:	11855983	Filing Dt:	09/14/2007
Publication #:	US20090072216	Pub Dt:	03/19/2009
Title:	PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING

Patent #:	NONE	Issue Dt:		Application #:	11856084	Filing Dt:	09/17/2007
Publication #:	US20080000080	Pub Dt:	01/03/2008
Title:	COMPLIANT ELECTRICAL CONTACTS

Patent #:	7918984	Issue Dt:	04/05/2011	Application #:	11856335	Filing Dt:	09/17/2007
Publication #:	US20090071836	Pub Dt:	03/19/2009
Title:	METHOD OF ELECTRODEPOSITING GERMANIUM COMPOUND MATERIALS ON A SUBSTRATE

Patent #:	NONE	Issue Dt:		Application #:	11856819	Filing Dt:	09/18/2007
Publication #:	US20090077518	Pub Dt:	03/19/2009
Title:	DERIVED LEVEL RECOGNITION IN A LAYOUT EDITOR

Patent #:	8148255	Issue Dt:	04/03/2012	Application #:	11856831	Filing Dt:	09/18/2007
Publication #:	US20090072392	Pub Dt:	03/19/2009
Title:	TECHNIQUES FOR FORMING SOLDER BUMP INTERCONNECTS

Patent #:	NONE	Issue Dt:		Application #:	11856839	Filing Dt:	09/18/2007
Publication #:	US20090072400	Pub Dt:	03/19/2009
Title:	CONTACT FORMING IN TWO PORTIONS AND CONTACT SO FORMED

Patent #:	NONE	Issue Dt:		Application #:	11856919	Filing Dt:	09/18/2007
Publication #:	US20080009142	Pub Dt:	01/10/2008
Title:	EVAPORATION CONTROL USING COATING

Patent #:	7764533	Issue Dt:	07/27/2010	Application #:	11857321	Filing Dt:	09/18/2007
Publication #:	US20090073783	Pub Dt:	03/19/2009
Title:	MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION

Patent #:	7567473	Issue Dt:	07/28/2009	Application #:	11857332	Filing Dt:	09/18/2007
Publication #:	US20090073790	Pub Dt:	03/19/2009
Title:	MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION

Patent #:	NONE	Issue Dt:		Application #:	11857569	Filing Dt:	09/19/2007
Publication #:	US20090072313	Pub Dt:	03/19/2009
Title:	HARDENED TRANSISTORS IN SOI DEVICES

Patent #:	7888959	Issue Dt:	02/15/2011	Application #:	11857596	Filing Dt:	09/19/2007
Publication #:	US20090134925	Pub Dt:	05/28/2009
Title:	APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

Patent #:	7378890	Issue Dt:	05/27/2008	Application #:	11857632	Filing Dt:	09/19/2007
Publication #:	US20080007310	Pub Dt:	01/10/2008
Title:	PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER

Patent #:	8481423	Issue Dt:	07/09/2013	Application #:	11857760	Filing Dt:	09/19/2007
Publication #:	US20090075472	Pub Dt:	03/19/2009
Title:	METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS

Patent #:	7750479	Issue Dt:	07/06/2010	Application #:	11857797	Filing Dt:	09/19/2007
Publication #:	US20080042283	Pub Dt:	02/21/2008
Title:	TREATMENT OF PLASMA DAMAGED LAYER FOR CRITICAL DIMENSION RETENTION, PORE SEALING AND REPAIR

Patent #:	7781332	Issue Dt:	08/24/2010	Application #:	11857805	Filing Dt:	09/19/2007
Publication #:	US20090072401	Pub Dt:	03/19/2009
Title:	METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS USING A PROTECTIVE SIDEWALL SPACER

Patent #:	8963294	Issue Dt:	02/24/2015	Application #:	11857806	Filing Dt:	09/19/2007
Publication #:	US20080006852	Pub Dt:	01/10/2008
Title:	DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME

Patent #:	NONE	Issue Dt:		Application #:	11858148	Filing Dt:	09/20/2007
Publication #:	US20090078999	Pub Dt:	03/26/2009
Title:	SEMICONDUCTOR DEVICE STRUCTURES WITH FLOATING BODY CHARGE STORAGE AND METHODS FOR FORMING SUCH SEMICONDUCTOR DEVICE STRUCTURES.

Patent #:	7867895	Issue Dt:	01/11/2011	Application #:	11858166	Filing Dt:	09/20/2007
Publication #:	US20090079077	Pub Dt:	03/26/2009
Title:	METHOD OF FABRICATING IMPROVED INTERCONNECT STRUCTURE WITH A VIA GOUGING FEATURE ABSENT PROFILE DAMAGE TO THE INTERCONNECT DIELECTRIC

Patent #:	7709370	Issue Dt:	05/04/2010	Application #:	11858615	Filing Dt:	09/20/2007
Publication #:	US20090081418	Pub Dt:	03/26/2009
Title:	SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES

Patent #:	8084862	Issue Dt:	12/27/2011	Application #:	11858624	Filing Dt:	09/20/2007
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Title:	INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME

Patent #:	8618663	Issue Dt:	12/31/2013	Application #:	11858636	Filing Dt:	09/20/2007
Publication #:	US20090079076	Pub Dt:	03/26/2009
Title:	PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME

Patent #:	7765509	Issue Dt:	07/27/2010	Application #:	11858995	Filing Dt:	09/21/2007
Publication #:	US20080010625	Pub Dt:	01/10/2008
Title:	AUTO CONNECTION ASSIGNMENT SYSTEM AND METHOD

Patent #:	7876131	Issue Dt:	01/25/2011	Application #:	11859351	Filing Dt:	09/21/2007
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Title:	DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC

Patent #:	7711212	Issue Dt:	05/04/2010	Application #:	11859665	Filing Dt:	09/21/2007
Publication #:	US20090080826	Pub Dt:	03/26/2009
Title:	JUNCTION FIELD EFFECT TRANSISTOR GEOMETRY FOR OPTICAL MODULATORS

Patent #:	NONE	Issue Dt:		Application #:	11859804	Filing Dt:	09/24/2007
Publication #:	US20090081598	Pub Dt:	03/26/2009
Title:	FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME

Patent #:	NONE	Issue Dt:		Application #:	11859805	Filing Dt:	09/24/2007
Publication #:	US20090081579	Pub Dt:	03/26/2009
Title:	FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME

100

Patent #:	7434129	Issue Dt:	10/07/2008	Application #:	11859834	Filing Dt:	09/24/2007
Publication #:	US20080010571	Pub Dt:	01/10/2008
Title:	PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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