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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14793
Page 64 of 148
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1
Patent #:
NONE
Issue Dt:
Application #:
11929968
Filing Dt:
10/30/2007
Publication #:
US20080112147
Pub Dt:
05/15/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
2
Patent #:
NONE
Issue Dt:
Application #:
11929976
Filing Dt:
10/30/2007
Publication #:
US20080106283
Pub Dt:
05/08/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
3
Patent #:
NONE
Issue Dt:
Application #:
11929982
Filing Dt:
10/30/2007
Publication #:
US20080106284
Pub Dt:
05/08/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
4
Patent #:
NONE
Issue Dt:
Application #:
11929991
Filing Dt:
10/30/2007
Publication #:
US20080117612
Pub Dt:
05/22/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
5
Patent #:
NONE
Issue Dt:
Application #:
11929999
Filing Dt:
10/30/2007
Publication #:
US20080112148
Pub Dt:
05/15/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
6
Patent #:
NONE
Issue Dt:
Application #:
11930005
Filing Dt:
02/01/2008
Publication #:
US20080117613
Pub Dt:
05/22/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
7
Patent #:
NONE
Issue Dt:
Application #:
11930010
Filing Dt:
10/30/2007
Publication #:
US20080048691
Pub Dt:
02/28/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
8
Patent #:
NONE
Issue Dt:
Application #:
11930016
Filing Dt:
10/30/2007
Publication #:
US20080112149
Pub Dt:
05/15/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
9
Patent #:
NONE
Issue Dt:
Application #:
11930019
Filing Dt:
10/30/2007
Publication #:
US20080106285
Pub Dt:
05/08/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
10
Patent #:
NONE
Issue Dt:
Application #:
11930026
Filing Dt:
10/30/2007
Publication #:
US20080047741
Pub Dt:
02/28/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
11
Patent #:
NONE
Issue Dt:
Application #:
11930033
Filing Dt:
10/30/2007
Publication #:
US20080129319
Pub Dt:
06/05/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
12
Patent #:
NONE
Issue Dt:
Application #:
11930039
Filing Dt:
10/30/2007
Publication #:
US20080132094
Pub Dt:
06/05/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
13
Patent #:
NONE
Issue Dt:
Application #:
11930045
Filing Dt:
10/30/2007
Publication #:
US20080106872
Pub Dt:
05/08/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
14
Patent #:
NONE
Issue Dt:
Application #:
11930231
Filing Dt:
10/31/2007
Publication #:
US20080050282
Pub Dt:
02/28/2008
Title:
METHOD AND APPARATUS FOR POINT OF CARE OSMOLARITY TESTING
15
Patent #:
8328892
Issue Dt:
12/11/2012
Application #:
11930236
Filing Dt:
10/31/2007
Publication #:
US20080053002
Pub Dt:
03/06/2008
Title:
SOLUTION FOR FORMING POLISHING SLURRY, POLISHING SLURRY AND RELATED METHODS
16
Patent #:
NONE
Issue Dt:
Application #:
11930270
Filing Dt:
10/31/2007
Publication #:
US20080053206
Pub Dt:
03/06/2008
Title:
METHOD AND APPARATUS FOR POINT OF CARE OSMOLARITY TESTING
17
Patent #:
7748895
Issue Dt:
07/06/2010
Application #:
11930633
Filing Dt:
10/31/2007
Publication #:
US20080059111
Pub Dt:
03/06/2008
Title:
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
18
Patent #:
NONE
Issue Dt:
Application #:
11930638
Filing Dt:
10/31/2007
Publication #:
US20080106291
Pub Dt:
05/08/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
19
Patent #:
NONE
Issue Dt:
Application #:
11930654
Filing Dt:
10/31/2007
Publication #:
US20080121879
Pub Dt:
05/29/2008
Title:
HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF
20
Patent #:
7729877
Issue Dt:
06/01/2010
Application #:
11930820
Filing Dt:
10/31/2007
Publication #:
US20080222583
Pub Dt:
09/11/2008
Title:
METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE
21
Patent #:
7716616
Issue Dt:
05/11/2010
Application #:
11930924
Filing Dt:
10/31/2007
Publication #:
US20080052656
Pub Dt:
02/28/2008
Title:
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
22
Patent #:
7995660
Issue Dt:
08/09/2011
Application #:
11930975
Filing Dt:
10/31/2007
Publication #:
US20090110084
Pub Dt:
04/30/2009
Title:
RECEIVER TERMINATION CIRCUIT FOR A HIGH SPEED DIRECT CURRENT (DC) SERIAL LINK
23
Patent #:
7648868
Issue Dt:
01/19/2010
Application #:
11931033
Filing Dt:
10/31/2007
Publication #:
US20090108352
Pub Dt:
04/30/2009
Title:
METAL-GATED MOSFET DEVICES HAVING SCALED GATE STACK THICKNESS
24
Patent #:
8297222
Issue Dt:
10/30/2012
Application #:
11931096
Filing Dt:
10/31/2007
Publication #:
US20080054023
Pub Dt:
03/06/2008
Title:
FULLY AUTOMATED PASTE DISPENSE SYSTEM FOR DISPENSING SMALL DOTS AND LINES
25
Patent #:
7833872
Issue Dt:
11/16/2010
Application #:
11931112
Filing Dt:
10/31/2007
Publication #:
US20090108306
Pub Dt:
04/30/2009
Title:
UNIFORM RECESS OF A MATERIAL IN A TRENCH INDEPENDENT OF INCOMING TOPOGRAPHY
26
Patent #:
7849426
Issue Dt:
12/07/2010
Application #:
11931144
Filing Dt:
10/31/2007
Publication #:
US20090113358
Pub Dt:
04/30/2009
Title:
MECHANISM FOR DETECTION AND COMPENSATION OF NBTI INDUCED THRESHOLD DEGRADATION
27
Patent #:
7887874
Issue Dt:
02/15/2011
Application #:
11931153
Filing Dt:
10/31/2007
Publication #:
US20080057180
Pub Dt:
03/06/2008
Title:
FULLY AUTOMATED PASTE DISPENSE SYSTEM FOR DISPENSING SMALL DOTS AND LINES
28
Patent #:
7521336
Issue Dt:
04/21/2009
Application #:
11931194
Filing Dt:
10/31/2007
Publication #:
US20080064189
Pub Dt:
03/13/2008
Title:
CRACK STOP FOR LOW K DIELECTRICS
29
Patent #:
7696573
Issue Dt:
04/13/2010
Application #:
11931209
Filing Dt:
10/31/2007
Publication #:
US20090108302
Pub Dt:
04/30/2009
Title:
MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
30
Patent #:
7894919
Issue Dt:
02/22/2011
Application #:
11931217
Filing Dt:
10/31/2007
Publication #:
US20080058976
Pub Dt:
03/06/2008
Title:
FULLY AUTOMATED PASTE DISPENSE SYSTEM FOR DISPENSING SMALL DOTS AND LINES
31
Patent #:
NONE
Issue Dt:
Application #:
11931230
Filing Dt:
10/31/2007
Publication #:
US20080236745
Pub Dt:
10/02/2008
Title:
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
32
Patent #:
7759191
Issue Dt:
07/20/2010
Application #:
11931238
Filing Dt:
10/31/2007
Publication #:
US20080064162
Pub Dt:
03/13/2008
Title:
VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME
33
Patent #:
8181594
Issue Dt:
05/22/2012
Application #:
11931242
Filing Dt:
10/31/2007
Publication #:
US20080057719
Pub Dt:
03/06/2008
Title:
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
34
Patent #:
8135546
Issue Dt:
03/13/2012
Application #:
11931296
Filing Dt:
10/31/2007
Publication #:
US20080071510
Pub Dt:
03/20/2008
Title:
MOMENT ANALYSIS OF TERTIARY PROTEIN STRUCTURES
35
Patent #:
7883990
Issue Dt:
02/08/2011
Application #:
11931371
Filing Dt:
10/31/2007
Publication #:
US20090110898
Pub Dt:
04/30/2009
Title:
HIGH RESISTIVITY SOI BASE WAFER USING THERMALLY ANNEALED SUBSTRATE
36
Patent #:
7476580
Issue Dt:
01/13/2009
Application #:
11931387
Filing Dt:
10/31/2007
Publication #:
US20080064197
Pub Dt:
03/13/2008
Title:
STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI CMOS DEVICES BY GATE STRESS ENGINEERING WITH SIGE AND/OR SI:C
37
Patent #:
7770139
Issue Dt:
08/03/2010
Application #:
11931626
Filing Dt:
10/31/2007
Publication #:
US20090108869
Pub Dt:
04/30/2009
Title:
DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH
38
Patent #:
NONE
Issue Dt:
Application #:
11931634
Filing Dt:
10/31/2007
Publication #:
US20080050880
Pub Dt:
02/28/2008
Title:
STRUCTURE FOR UNIFORM TRIGGERING OF MULTIFINGER SEMICONDUCTOR DEVICES WITH TUNABLE TRIGGER VOLTAGE
39
Patent #:
7682859
Issue Dt:
03/23/2010
Application #:
11931836
Filing Dt:
10/31/2007
Publication #:
US20080061317
Pub Dt:
03/13/2008
Title:
PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE
40
Patent #:
7556979
Issue Dt:
07/07/2009
Application #:
11932385
Filing Dt:
10/31/2007
Publication #:
US20080048305
Pub Dt:
02/28/2008
Title:
NEGATIVE THERMAL EXPANSION SYSTEM (NTES) DEVICE FOR TCE COMPENSATION IN ELASTOMER COMPOSITES AND CONDUCTIVE ELASTOMER INTERCONNECTS IN MICROELECTRONIC PACKAGING
41
Patent #:
7820488
Issue Dt:
10/26/2010
Application #:
11932793
Filing Dt:
10/31/2007
Publication #:
US20080064143
Pub Dt:
03/13/2008
Title:
MICROELECTRONIC DEVICES AND METHODS
42
Patent #:
7492628
Issue Dt:
02/17/2009
Application #:
11933505
Filing Dt:
11/01/2007
Publication #:
US20080084733
Pub Dt:
04/10/2008
Title:
COMPUTER-READABLE MEDIUM ENCODING A MEMORY USING A BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL
43
Patent #:
7714079
Issue Dt:
05/11/2010
Application #:
11933530
Filing Dt:
11/01/2007
Publication #:
US20080063880
Pub Dt:
03/13/2008
Title:
PATTERNABLE LOW DIELECTRIC CONSTANT MATERIALS AND THEIR USE IN ULSI INTERCONNECTION
44
Patent #:
7741672
Issue Dt:
06/22/2010
Application #:
11933571
Filing Dt:
11/01/2007
Publication #:
US20090140328
Pub Dt:
06/04/2009
Title:
BRIDGED GATE FINFET
45
Patent #:
NONE
Issue Dt:
Application #:
11933760
Filing Dt:
11/01/2007
Publication #:
US20090117360
Pub Dt:
05/07/2009
Title:
SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT
46
Patent #:
7833884
Issue Dt:
11/16/2010
Application #:
11934479
Filing Dt:
11/02/2007
Publication #:
US20090117720
Pub Dt:
05/07/2009
Title:
STRAINED SEMICONDUCTOR-ON-INSULATOR BY SI:C COMBINED WITH POROUS PROCESS
47
Patent #:
7949978
Issue Dt:
05/24/2011
Application #:
11934804
Filing Dt:
11/05/2007
Publication #:
US20090119625
Pub Dt:
05/07/2009
Title:
STRUCTURE FOR SYSTEM ARCHITECTURES FOR AND METHODS OF SCHEDULING ON-CHIP AND ACROSS-CHIP NOISE EVENTS IN AN INTEGRATED CIRCUIT
48
Patent #:
7823108
Issue Dt:
10/26/2010
Application #:
11934995
Filing Dt:
11/05/2007
Publication #:
US20080066036
Pub Dt:
03/13/2008
Title:
CHIP HAVING TIMING ANALYSIS OF PATHS PERFORMED WITHIN THE CHIP DURING THE DESIGN PROCESS
49
Patent #:
7700993
Issue Dt:
04/20/2010
Application #:
11935143
Filing Dt:
11/05/2007
Publication #:
US20090114971
Pub Dt:
05/07/2009
Title:
CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS
50
Patent #:
7668037
Issue Dt:
02/23/2010
Application #:
11935566
Filing Dt:
11/06/2007
Publication #:
US20090116312
Pub Dt:
05/07/2009
Title:
STORAGE ARRAY INCLUDING A LOCAL CLOCK BUFFER WITH PROGRAMMABLE TIMING
51
Patent #:
7937675
Issue Dt:
05/03/2011
Application #:
11935612
Filing Dt:
11/06/2007
Publication #:
US20090119626
Pub Dt:
05/07/2009
Title:
DESIGN STRUCTURE INCLUDING TRANSISTOR HAVING GATE AND BODY IN DIRECT SELF-ALIGNED CONTACT
52
Patent #:
7683416
Issue Dt:
03/23/2010
Application #:
11935698
Filing Dt:
11/06/2007
Publication #:
US20080173918
Pub Dt:
07/24/2008
Title:
POST STI TRENCH CAPACITOR
53
Patent #:
7465615
Issue Dt:
12/16/2008
Application #:
11935714
Filing Dt:
11/06/2007
Title:
POLYCONDUCTOR LINE END FORMATION AND RELATED MASK
54
Patent #:
7710796
Issue Dt:
05/04/2010
Application #:
11935741
Filing Dt:
11/06/2007
Publication #:
US20090116307
Pub Dt:
05/07/2009
Title:
LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE
55
Patent #:
7759787
Issue Dt:
07/20/2010
Application #:
11935834
Filing Dt:
11/06/2007
Publication #:
US20090114429
Pub Dt:
05/07/2009
Title:
PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
56
Patent #:
7921390
Issue Dt:
04/05/2011
Application #:
11935865
Filing Dt:
11/06/2007
Publication #:
US20080066042
Pub Dt:
03/13/2008
Title:
METHOD AND SYSTEM FOR CREATING, VIEWING, EDITING, AND SHARING OUTPUT FROM A DESIGN CHECKING SYSTEM
57
Patent #:
7782691
Issue Dt:
08/24/2010
Application #:
11936139
Filing Dt:
11/07/2007
Publication #:
US20090116324
Pub Dt:
05/07/2009
Title:
APPARATUS FOR GUARANTEED WRITE THROUGH IN DOMINO READ SRAM'S
58
Patent #:
7873933
Issue Dt:
01/18/2011
Application #:
11936673
Filing Dt:
11/07/2007
Publication #:
US20080059919
Pub Dt:
03/06/2008
Title:
COMPUTER PROGRAM FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD
59
Patent #:
7865853
Issue Dt:
01/04/2011
Application #:
11936775
Filing Dt:
11/07/2007
Publication #:
US20080066030
Pub Dt:
03/13/2008
Title:
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
60
Patent #:
7787102
Issue Dt:
08/31/2010
Application #:
11936782
Filing Dt:
11/07/2007
Publication #:
US20080151208
Pub Dt:
06/26/2008
Title:
REAL-TIME CONFIGURABLE MASKING
61
Patent #:
NONE
Issue Dt:
Application #:
11936785
Filing Dt:
11/07/2007
Publication #:
US20080107976
Pub Dt:
05/08/2008
Title:
REAL-TIME CONFIGURABLE MASKING
62
Patent #:
7907410
Issue Dt:
03/15/2011
Application #:
11936887
Filing Dt:
11/08/2007
Publication #:
US20090122491
Pub Dt:
05/14/2009
Title:
UNIVERSAL PATTERNED METAL THERMAL INTERFACE
63
Patent #:
7716009
Issue Dt:
05/11/2010
Application #:
11936971
Filing Dt:
11/08/2007
Publication #:
US20080065696
Pub Dt:
03/13/2008
Title:
METROLOGY TOOL RECIPE VALIDATOR USING BEST KNOWN METHODS
64
Patent #:
7846791
Issue Dt:
12/07/2010
Application #:
11937088
Filing Dt:
11/08/2007
Publication #:
US20090121270
Pub Dt:
05/14/2009
Title:
DESIGN STRUCTURE FOR A TRENCH CAPACITOR
65
Patent #:
NONE
Issue Dt:
Application #:
11937105
Filing Dt:
11/08/2007
Publication #:
US20090121357
Pub Dt:
05/14/2009
Title:
DESIGN STRUCTURE FOR BRIDGE OF A SEMINCONDUCTOR INTERNAL NODE
66
Patent #:
7865862
Issue Dt:
01/04/2011
Application #:
11937106
Filing Dt:
11/08/2007
Publication #:
US20090125704
Pub Dt:
05/14/2009
Title:
DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS
67
Patent #:
8132136
Issue Dt:
03/06/2012
Application #:
11937111
Filing Dt:
11/08/2007
Publication #:
US20090044160
Pub Dt:
02/12/2009
Title:
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
68
Patent #:
7538004
Issue Dt:
05/26/2009
Application #:
11937534
Filing Dt:
11/09/2007
Publication #:
US20080124882
Pub Dt:
05/29/2008
Title:
METHOD OF FABRICATION FOR SIGE HETEROJUNCTION BIPOLAR TRANSISTOR (HBT)
69
Patent #:
7463083
Issue Dt:
12/09/2008
Application #:
11937559
Filing Dt:
11/09/2007
Publication #:
US20080068073
Pub Dt:
03/20/2008
Title:
NOISE REDUCTION IN DIGITAL SYSTEMS WHEN THE NOISE IS CAUSED BY SIMULTANEOUSLY CLOCKING DATA REGISTERS
70
Patent #:
7572689
Issue Dt:
08/11/2009
Application #:
11937637
Filing Dt:
11/09/2007
Publication #:
US20090121295
Pub Dt:
05/14/2009
Title:
METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
71
Patent #:
7897059
Issue Dt:
03/01/2011
Application #:
11937646
Filing Dt:
11/09/2007
Publication #:
US20090120999
Pub Dt:
05/14/2009
Title:
HIGH TIN SOLDER ETCHING SOLUTION
72
Patent #:
7904289
Issue Dt:
03/08/2011
Application #:
11938532
Filing Dt:
11/12/2007
Publication #:
US20090125292
Pub Dt:
05/14/2009
Title:
METHOD AND SYSTEM FOR TESTING FUNCTIONALITY OF A CHIP CHECKER
73
Patent #:
7788615
Issue Dt:
08/31/2010
Application #:
11938612
Filing Dt:
11/12/2007
Publication #:
US20080052650
Pub Dt:
02/28/2008
Title:
COMPUTER PROGRAM PRODUCT FOR VERIFICATION USING REACHABILITY OVERAPPROXIMATION
74
Patent #:
7475370
Issue Dt:
01/06/2009
Application #:
11938656
Filing Dt:
11/12/2007
Publication #:
US20080066031
Pub Dt:
03/13/2008
Title:
SYSTEM FOR VERIFICATION USING REACHABILITY OVERAPPROXIMATION
75
Patent #:
7895459
Issue Dt:
02/22/2011
Application #:
11938899
Filing Dt:
11/13/2007
Publication #:
US20090125744
Pub Dt:
05/14/2009
Title:
STRUCTURE FOR A SYSTEM AND METHOD OF PREDICTING POWER EVENTS IN AN INTERMITTENT POWER ENVIRONMENT AND DISPATCHING COMPUTATIONAL OPERATIONS OF AN INTEGRATED CIRCUIT ACCORDINGLY
76
Patent #:
7936042
Issue Dt:
05/03/2011
Application #:
11939017
Filing Dt:
11/13/2007
Publication #:
US20090121258
Pub Dt:
05/14/2009
Title:
FIELD EFFECT TRANSISTOR CONTAINING A WIDE BAND GAP SEMICONDUCTOR MATERIAL IN A DRAIN
77
Patent #:
7847320
Issue Dt:
12/07/2010
Application #:
11939574
Filing Dt:
11/14/2007
Publication #:
US20090121291
Pub Dt:
05/14/2009
Title:
DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD
78
Patent #:
8039376
Issue Dt:
10/18/2011
Application #:
11939578
Filing Dt:
11/14/2007
Publication #:
US20090124069
Pub Dt:
05/14/2009
Title:
METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION
79
Patent #:
NONE
Issue Dt:
Application #:
11939582
Filing Dt:
11/14/2007
Publication #:
US20090121287
Pub Dt:
05/14/2009
Title:
DUAL WIRED INTEGRATED CIRCUIT CHIPS
80
Patent #:
8299605
Issue Dt:
10/30/2012
Application #:
11939599
Filing Dt:
11/14/2007
Publication #:
US20090121343
Pub Dt:
05/14/2009
Title:
CARBON NANOTUBE STRUCTURES FOR ENHANCEMENT OF THERMAL DISSIPATION FROM SEMICONDUCTOR MODULES
81
Patent #:
8013342
Issue Dt:
09/06/2011
Application #:
11939612
Filing Dt:
11/14/2007
Publication #:
US20090121260
Pub Dt:
05/14/2009
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
82
Patent #:
7768130
Issue Dt:
08/03/2010
Application #:
11939671
Filing Dt:
11/14/2007
Publication #:
US20080079172
Pub Dt:
04/03/2008
Title:
BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS HIGH-K AND LOW-K DIELECTRIC REGIONS
83
Patent #:
NONE
Issue Dt:
Application #:
11940487
Filing Dt:
11/15/2007
Publication #:
US20090127711
Pub Dt:
05/21/2009
Title:
INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME
84
Patent #:
8492846
Issue Dt:
07/23/2013
Application #:
11940531
Filing Dt:
11/15/2007
Publication #:
US20090127626
Pub Dt:
05/21/2009
Title:
STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION
85
Patent #:
7793242
Issue Dt:
09/07/2010
Application #:
11940711
Filing Dt:
11/15/2007
Publication #:
US20080066033
Pub Dt:
03/13/2008
Title:
METHOD AND SYSTEM FOR PERFORMING HEURISTIC CONSTRAINT SIMPLIFICATION
86
Patent #:
8551313
Issue Dt:
10/08/2013
Application #:
11940720
Filing Dt:
11/15/2007
Publication #:
US20090127121
Pub Dt:
05/21/2009
Title:
METHOD AND APPARATUS FOR ELECTROPLATING ON SOI AND BULK SEMICONDUCTOR WAFERS
87
Patent #:
7788616
Issue Dt:
08/31/2010
Application #:
11940755
Filing Dt:
11/15/2007
Publication #:
US20080066034
Pub Dt:
03/13/2008
Title:
METHOD AND SYSTEM FOR PERFORMING HEURISTIC CONSTRAINT SIMPLIFICATION
88
Patent #:
8015538
Issue Dt:
09/06/2011
Application #:
11941104
Filing Dt:
11/16/2007
Publication #:
US20080092094
Pub Dt:
04/17/2008
Title:
A DESIGN STRUCTURE WITH A DEEP SUB-COLLECTOR, A REACH-THROUGH STRUCTURE AND TRENCH ISOLATION
89
Patent #:
7733720
Issue Dt:
06/08/2010
Application #:
11941161
Filing Dt:
11/16/2007
Publication #:
US20090132873
Pub Dt:
05/21/2009
Title:
METHOD AND SYSTEM FOR DETERMINING ELEMENT VOLTAGE SELECTION CONTROL VALUES FOR A STORAGE DEVICE
90
Patent #:
7459785
Issue Dt:
12/02/2008
Application #:
11941165
Filing Dt:
11/16/2007
Publication #:
US20080067676
Pub Dt:
03/20/2008
Title:
ELECTRICAL INTERCONNECTION STRUCTURE FORMATION
91
Patent #:
7551508
Issue Dt:
06/23/2009
Application #:
11941168
Filing Dt:
11/16/2007
Publication #:
US20090129193
Pub Dt:
05/21/2009
Title:
ENERGY EFFICIENT STORAGE DEVICE USING PER-ELEMENT SELECTABLE POWER SUPPLY VOLTAGES
92
Patent #:
7757200
Issue Dt:
07/13/2010
Application #:
11941308
Filing Dt:
11/16/2007
Publication #:
US20090128225
Pub Dt:
05/21/2009
Title:
STRUCTURE OF AN APPARATUS FOR PROGRAMMING AN ELECTRONICALLY PROGRAMMABLE SEMICONDUCTOR FUSE
93
Patent #:
7696811
Issue Dt:
04/13/2010
Application #:
11941342
Filing Dt:
11/16/2007
Publication #:
US20080086706
Pub Dt:
04/10/2008
Title:
METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS
94
Patent #:
7609569
Issue Dt:
10/27/2009
Application #:
11941994
Filing Dt:
11/19/2007
Publication #:
US20090129181
Pub Dt:
05/21/2009
Title:
SYSTEM AND METHOD FOR IMPLEMENTING ROW REDUNDANCY WITH REDUCED ACCESS TIME AND REDUCED DEVICE AREA
95
Patent #:
7743355
Issue Dt:
06/22/2010
Application #:
11942034
Filing Dt:
11/19/2007
Publication #:
US20080072184
Pub Dt:
03/20/2008
Title:
METHOD OF ACHIEVING TIMING CLOSURE IN DIGITAL INTEGRATED CIRCUITS BY OPTIMIZING INDIVIDUAL MACROS
96
Patent #:
8440917
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05/14/2013
Application #:
11942061
Filing Dt:
11/19/2007
Publication #:
US20090126983
Pub Dt:
05/21/2009
Title:
REDUCING IMPEDANCE DISCONTINUITY IN PACKAGES
97
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7900181
Issue Dt:
03/01/2011
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11942148
Filing Dt:
11/19/2007
Publication #:
US20080072196
Pub Dt:
03/20/2008
Title:
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
98
Patent #:
7844435
Issue Dt:
11/30/2010
Application #:
11942270
Filing Dt:
11/19/2007
Publication #:
US20080072189
Pub Dt:
03/20/2008
Title:
INTEGRATED CIRCUIT CHIP HAVING ON-CHIP SIGNAL INTEGRITY AND NOISE VERIFICATION USING FREQUENCY DEPENDENT RLC EXTRACTION AND MODELING TECHNIQUES
99
Patent #:
7860701
Issue Dt:
12/28/2010
Application #:
11942309
Filing Dt:
11/19/2007
Publication #:
US20080071512
Pub Dt:
03/20/2008
Title:
METHODOLOGY FOR IMAGE FIDELITY VERIFICATION
100
Patent #:
NONE
Issue Dt:
Application #:
11942393
Filing Dt:
11/19/2007
Publication #:
US20090130845
Pub Dt:
05/21/2009
Title:
DIRECT ELECTRODEPOSITION OF COPPER ONTO TA-ALLOY BARRIERS
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
06/29/2015
Assignee
1
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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