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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14793
Page 72 of 148
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
1
Patent #:
7865861
Issue Dt:
01/04/2011
Application #:
12107158
Filing Dt:
04/22/2008
Publication #:
US20080195993
Pub Dt:
08/14/2008
Title:
METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION
2
Patent #:
7989358
Issue Dt:
08/02/2011
Application #:
12107303
Filing Dt:
04/22/2008
Publication #:
US20080191322
Pub Dt:
08/14/2008
Title:
PREVENTION OF BACKSIDE CRACKS IN SEMICONDUCTOR CHIPS OR WAFERS USING BACKSIDE FILM OR BACKSIDE WET ETCH
3
Patent #:
7791057
Issue Dt:
09/07/2010
Application #:
12107573
Filing Dt:
04/22/2008
Publication #:
US20090261313
Pub Dt:
10/22/2009
Title:
MEMORY CELL HAVING A BURIED PHASE CHANGE REGION AND METHOD FOR FABRICATING THE SAME
4
Patent #:
8077240
Issue Dt:
12/13/2011
Application #:
12107825
Filing Dt:
04/23/2008
Publication #:
US20090268063
Pub Dt:
10/29/2009
Title:
METHODS FOR ENHANCING QUALITY OF PIXEL SENSOR IMAGE FRAMES FOR GLOBAL SHUTTER IMAGING
5
Patent #:
7768325
Issue Dt:
08/03/2010
Application #:
12107847
Filing Dt:
04/23/2008
Publication #:
US20090267660
Pub Dt:
10/29/2009
Title:
CIRCUIT AND DESIGN STRUCTURE FOR SYNCHRONIZING MULTIPLE DIGITAL SIGNALS
6
Patent #:
8119322
Issue Dt:
02/21/2012
Application #:
12107889
Filing Dt:
04/23/2008
Publication #:
US20080220615
Pub Dt:
09/11/2008
Title:
METHOD FOR PRODUCING SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITION FOR SAME
7
Patent #:
7849428
Issue Dt:
12/07/2010
Application #:
12107940
Filing Dt:
04/23/2008
Publication #:
US20080288901
Pub Dt:
11/20/2008
Title:
FORMALLY DERIVING A MINIMAL CLOCK-GATING SCHEME
8
Patent #:
7833907
Issue Dt:
11/16/2010
Application #:
12107980
Filing Dt:
04/23/2008
Publication #:
US20090267192
Pub Dt:
10/29/2009
Title:
CMP METHODS AVOIDING EDGE EROSION AND RELATED WAFER
9
Patent #:
8154130
Issue Dt:
04/10/2012
Application #:
12107992
Filing Dt:
04/23/2008
Publication #:
US20080220606
Pub Dt:
09/11/2008
Title:
SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY
10
Patent #:
7682968
Issue Dt:
03/23/2010
Application #:
12108001
Filing Dt:
04/23/2008
Publication #:
US20080227283
Pub Dt:
09/18/2008
Title:
SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY
11
Patent #:
7871935
Issue Dt:
01/18/2011
Application #:
12108119
Filing Dt:
04/23/2008
Publication #:
US20090269929
Pub Dt:
10/29/2009
Title:
NON-PLASMA CAPPING LAYER FOR INTERCONNECT APPLICATIONS
12
Patent #:
8015518
Issue Dt:
09/06/2011
Application #:
12108165
Filing Dt:
04/23/2008
Publication #:
US20090154037
Pub Dt:
06/18/2009
Title:
DESIGN STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION FOR BIPOLAR SEMICONDUCTOR CIRCUITRY
13
Patent #:
7514290
Issue Dt:
04/07/2009
Application #:
12108512
Filing Dt:
04/24/2008
Title:
CHIP-TO-WAFER INTEGRATION TECHNOLOGY FOR THREE-DIMENSIONAL CHIP STACKING
14
Patent #:
7823115
Issue Dt:
10/26/2010
Application #:
12108629
Filing Dt:
04/24/2008
Publication #:
US20080201683
Pub Dt:
08/21/2008
Title:
METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION
15
Patent #:
7790564
Issue Dt:
09/07/2010
Application #:
12108851
Filing Dt:
04/24/2008
Publication #:
US20090269903
Pub Dt:
10/29/2009
Title:
METHODS FOR FABRICATING ACTIVE DEVICES ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE UTILIZING MULTIPLE DEPTH SHALLOW TRENCH ISOLATIONS
16
Patent #:
NONE
Issue Dt:
Application #:
12108905
Filing Dt:
04/24/2008
Publication #:
US20090267179
Pub Dt:
10/29/2009
Title:
SYSTEM FOR POWER PERFORMANCE OPTIMIZATION OF MULTICORE PROCESSOR CHIP
17
Patent #:
7709926
Issue Dt:
05/04/2010
Application #:
12108924
Filing Dt:
04/24/2008
Publication #:
US20090267178
Pub Dt:
10/29/2009
Title:
DEVICE STRUCTURES FOR ACTIVE DEVICES FABRICATED USING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
18
Patent #:
7932136
Issue Dt:
04/26/2011
Application #:
12109025
Filing Dt:
04/24/2008
Publication #:
US20090267149
Pub Dt:
10/29/2009
Title:
SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS
19
Patent #:
7443194
Issue Dt:
10/28/2008
Application #:
12109285
Filing Dt:
04/24/2008
Title:
I/O DRIVER FOR INTEGRATED CIRCUIT WITH OUTPUT IMPEDANCE CONTROL
20
Patent #:
7903493
Issue Dt:
03/08/2011
Application #:
12109379
Filing Dt:
04/25/2008
Publication #:
US20090268541
Pub Dt:
10/29/2009
Title:
DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF
21
Patent #:
7859878
Issue Dt:
12/28/2010
Application #:
12110375
Filing Dt:
04/28/2008
Publication #:
US20090141529
Pub Dt:
06/04/2009
Title:
DESIGN STRUCTURE FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES
22
Patent #:
8117567
Issue Dt:
02/14/2012
Application #:
12110456
Filing Dt:
04/28/2008
Publication #:
US20090141566
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY
23
Patent #:
7875550
Issue Dt:
01/25/2011
Application #:
12110465
Filing Dt:
04/28/2008
Publication #:
US20080233743
Pub Dt:
09/25/2008
Title:
METHOD AND STRUCTURE FOR SELF-ALIGNED DEVICE CONTACTS
24
Patent #:
NONE
Issue Dt:
Application #:
12110512
Filing Dt:
04/28/2008
Publication #:
US20080230741
Pub Dt:
09/25/2008
Title:
POLISHING INHIBITING LAYER FORMING ADDITIVE
25
Patent #:
8008764
Issue Dt:
08/30/2011
Application #:
12110579
Filing Dt:
04/28/2008
Publication #:
US20090267238
Pub Dt:
10/29/2009
Title:
BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CIRCUITS
26
Patent #:
NONE
Issue Dt:
Application #:
12110582
Filing Dt:
04/28/2008
Publication #:
US20090141530
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR IMPLEMENTING ENHANCED CONTENT ADDRESSABLE MEMORY PERFORMANCE CAPABILITY
27
Patent #:
7816760
Issue Dt:
10/19/2010
Application #:
12110633
Filing Dt:
06/20/2008
Publication #:
US20080246112
Pub Dt:
10/09/2008
Title:
SEMICONDUCTOR STRUCTURE INCLUDING LAMINATED ISOLATION REGION
28
Patent #:
8027797
Issue Dt:
09/27/2011
Application #:
12110639
Filing Dt:
04/28/2008
Publication #:
US20090271134
Pub Dt:
10/29/2009
Title:
METHODS AND APPARATUS FOR DETERMINING A SWITCHING HISTORY TIME CONSTANT IN AN INTEGRATED CIRCUIT DEVICE
29
Patent #:
8203873
Issue Dt:
06/19/2012
Application #:
12110644
Filing Dt:
04/28/2008
Publication #:
US20080232160
Pub Dt:
09/25/2008
Title:
RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE
30
Patent #:
7756667
Issue Dt:
07/13/2010
Application #:
12110698
Filing Dt:
04/28/2008
Publication #:
US20080281551
Pub Dt:
11/13/2008
Title:
APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS OF PHYSICAL CHARACTERISTICS WITHIN A DATA CENTER
31
Patent #:
7739073
Issue Dt:
06/15/2010
Application #:
12110732
Filing Dt:
04/28/2008
Publication #:
US20080239539
Pub Dt:
10/02/2008
Title:
METHOD AND APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS OF PHYSICAL CHARACTERISTICS WITHIN A DATA CENTER
32
Patent #:
NONE
Issue Dt:
Application #:
12110753
Filing Dt:
04/28/2008
Publication #:
US20090267130
Pub Dt:
10/29/2009
Title:
STRUCTURE AND PROCESS INTEGRATION FOR FLASH STORAGE ELEMENT AND DUAL CONDUCTOR COMPLEMENTARY MOSFETS
33
Patent #:
8028257
Issue Dt:
09/27/2011
Application #:
12110765
Filing Dt:
04/28/2008
Publication #:
US20080215783
Pub Dt:
09/04/2008
Title:
STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE
34
Patent #:
7836356
Issue Dt:
11/16/2010
Application #:
12110851
Filing Dt:
04/28/2008
Publication #:
US20090271664
Pub Dt:
10/29/2009
Title:
METHOD FOR MONITORING DEPENDENT METRIC STREAMS FOR ANOMALIES
35
Patent #:
7482180
Issue Dt:
01/27/2009
Application #:
12111196
Filing Dt:
04/29/2008
Title:
METHOD FOR DETERMINING THE IMPACT OF LAYER THICKNESSES ON LAMINATE WARPAGE
36
Patent #:
NONE
Issue Dt:
Application #:
12111266
Filing Dt:
04/29/2008
Publication #:
US20090269897
Pub Dt:
10/29/2009
Title:
METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL
37
Patent #:
8210904
Issue Dt:
07/03/2012
Application #:
12111276
Filing Dt:
04/29/2008
Publication #:
US20090270017
Pub Dt:
10/29/2009
Title:
SLURRYLESS MECHANICAL PLANARIZATION FOR SUBSTRATE RECLAMATION
38
Patent #:
NONE
Issue Dt:
Application #:
12111285
Filing Dt:
04/29/2008
Publication #:
US20090267156
Pub Dt:
10/29/2009
Title:
DEVICE STRUCTURES INCLUDING DUAL-DEPTH TRENCH ISOLATION REGIONS AND DESIGN STRUCTURES FOR A STATIC RANDOM ACCESS MEMORY
39
Patent #:
7877716
Issue Dt:
01/25/2011
Application #:
12111529
Filing Dt:
04/29/2008
Publication #:
US20080201681
Pub Dt:
08/21/2008
Title:
COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE
40
Patent #:
7930663
Issue Dt:
04/19/2011
Application #:
12111609
Filing Dt:
04/29/2008
Publication #:
US20080201675
Pub Dt:
08/21/2008
Title:
STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH ELEMENT
41
Patent #:
NONE
Issue Dt:
Application #:
12111915
Filing Dt:
04/29/2008
Publication #:
US20090266480
Pub Dt:
10/29/2009
Title:
PROCESS FOR PREPARING A SOLDER STAND-OFF
42
Patent #:
7958482
Issue Dt:
06/07/2011
Application #:
12112329
Filing Dt:
04/30/2008
Publication #:
US20090276748
Pub Dt:
11/05/2009
Title:
STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT
43
Patent #:
8006211
Issue Dt:
08/23/2011
Application #:
12112336
Filing Dt:
04/30/2008
Publication #:
US20090276739
Pub Dt:
11/05/2009
Title:
IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION
44
Patent #:
7652523
Issue Dt:
01/26/2010
Application #:
12112356
Filing Dt:
04/30/2008
Publication #:
US20080191793
Pub Dt:
08/14/2008
Title:
RATIOED FEEDBACK BODY VOLTAGE BIAS GENERATOR
45
Patent #:
7952944
Issue Dt:
05/31/2011
Application #:
12112391
Filing Dt:
04/30/2008
Publication #:
US20090273960
Pub Dt:
11/05/2009
Title:
SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS
46
Patent #:
7660152
Issue Dt:
02/09/2010
Application #:
12112454
Filing Dt:
04/30/2008
Publication #:
US20090273968
Pub Dt:
11/05/2009
Title:
METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES
47
Patent #:
NONE
Issue Dt:
Application #:
12112549
Filing Dt:
04/30/2008
Publication #:
US20080197448
Pub Dt:
08/21/2008
Title:
SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SIO2
48
Patent #:
8598569
Issue Dt:
12/03/2013
Application #:
12113064
Filing Dt:
04/30/2008
Publication #:
US20090272967
Pub Dt:
11/05/2009
Title:
PENTACENE-CARBON NANOTUBE COMPOSITE, METHOD OF FORMING THE COMPOSITE, AND SEMICONDUCTOR DEVICE INCLUDING THE COMPOSITE
49
Patent #:
8809182
Issue Dt:
08/19/2014
Application #:
12113230
Filing Dt:
05/01/2008
Publication #:
US20090273081
Pub Dt:
11/05/2009
Title:
PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR PB-FREE C4 INTEGRATED CIRCUIT CHIP JOINING
50
Patent #:
7844933
Issue Dt:
11/30/2010
Application #:
12113288
Filing Dt:
05/01/2008
Publication #:
US20090276743
Pub Dt:
11/05/2009
Title:
METHODS OF OPTIMIZING TIMING OF SIGNALS IN AN INTEGRATED CIRCUIT DESIGN USING PROXY SLACK VALUES
51
Patent #:
7895547
Issue Dt:
02/22/2011
Application #:
12113374
Filing Dt:
05/01/2008
Publication #:
US20090276736
Pub Dt:
11/05/2009
Title:
TEST PATTERN BASED PROCESS MODEL CALIBRATION
52
Patent #:
7966723
Issue Dt:
06/28/2011
Application #:
12113457
Filing Dt:
05/01/2008
Publication #:
US20080212290
Pub Dt:
09/04/2008
Title:
METHOD FOR FACILITATING ACCESS TO ELECTRONIC COMPONENTS
53
Patent #:
7863143
Issue Dt:
01/04/2011
Application #:
12113462
Filing Dt:
05/01/2008
Publication #:
US20090273040
Pub Dt:
11/05/2009
Title:
HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS
54
Patent #:
7454098
Issue Dt:
11/18/2008
Application #:
12113480
Filing Dt:
05/01/2008
Title:
MECHANICALLY DECOUPLED OPTO-MECHANICAL CONNECTOR FOR FLEXIBLE OPTICAL WAVEGUIDES EMBEDDED AND/OR ATTACHED TO A PRINTED CIRCUIT BOARD
55
Patent #:
8232604
Issue Dt:
07/31/2012
Application #:
12113510
Filing Dt:
05/01/2008
Publication #:
US20090273041
Pub Dt:
11/05/2009
Title:
TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER
56
Patent #:
7736981
Issue Dt:
06/15/2010
Application #:
12113527
Filing Dt:
05/01/2008
Publication #:
US20090273042
Pub Dt:
11/05/2009
Title:
METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE
57
Patent #:
NONE
Issue Dt:
Application #:
12113557
Filing Dt:
05/01/2008
Publication #:
US20090275182
Pub Dt:
11/05/2009
Title:
METHOD FOR FABRICATING A METAL HIGH DIELECTRIC CONSTANT TRANSISTOR WITH REVERSE-T GATE
58
Patent #:
8010815
Issue Dt:
08/30/2011
Application #:
12113663
Filing Dt:
05/01/2008
Publication #:
US20090276649
Pub Dt:
11/05/2009
Title:
COMPUTATIONAL DEVICE POWER-SAVINGS
59
Patent #:
NONE
Issue Dt:
Application #:
12114036
Filing Dt:
05/02/2008
Publication #:
US20090140297
Pub Dt:
06/04/2009
Title:
SELF-ALIGNMENT SCHEME FOR A HETEROJUNCTION BIPOLAR TRANSISTOR
60
Patent #:
8028195
Issue Dt:
09/27/2011
Application #:
12114070
Filing Dt:
05/02/2008
Publication #:
US20090153172
Pub Dt:
06/18/2009
Title:
STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM
61
Patent #:
7679121
Issue Dt:
03/16/2010
Application #:
12114168
Filing Dt:
05/02/2008
Publication #:
US20080237637
Pub Dt:
10/02/2008
Title:
ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL N-CHANNEL MISFETS AND METHODS THEREOF
62
Patent #:
7560347
Issue Dt:
07/14/2009
Application #:
12114180
Filing Dt:
05/02/2008
Publication #:
US20080206937
Pub Dt:
08/28/2008
Title:
METHODS FOR FORMING A WRAP-AROUND GATE FIELD EFFECT TRANSISTOR
63
Patent #:
7478301
Issue Dt:
01/13/2009
Application #:
12114198
Filing Dt:
05/02/2008
Publication #:
US20080209289
Pub Dt:
08/28/2008
Title:
PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME
64
Patent #:
8015525
Issue Dt:
09/06/2011
Application #:
12114203
Filing Dt:
05/02/2008
Publication #:
US20080201676
Pub Dt:
08/21/2008
Title:
SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS
65
Patent #:
7741919
Issue Dt:
06/22/2010
Application #:
12114285
Filing Dt:
05/02/2008
Publication #:
US20090273405
Pub Dt:
11/05/2009
Title:
ARCHITECTURE FOR MAINTAINING CONSTANT VOLTAGE-CONTROLLED OSCILLATOR GAIN
66
Patent #:
7598097
Issue Dt:
10/06/2009
Application #:
12114636
Filing Dt:
05/02/2008
Publication #:
US20080241369
Pub Dt:
10/02/2008
Title:
METHOD OF FABRICATING A MAGNETIC SHIFT REGISTER
67
Patent #:
7873891
Issue Dt:
01/18/2011
Application #:
12114853
Filing Dt:
05/05/2008
Publication #:
US20080203980
Pub Dt:
08/28/2008
Title:
PROGRAMMABLE VOLTAGE DIVIDER
68
Patent #:
7829926
Issue Dt:
11/09/2010
Application #:
12114857
Filing Dt:
05/05/2008
Publication #:
US20080203438
Pub Dt:
08/28/2008
Title:
DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS
69
Patent #:
7745256
Issue Dt:
06/29/2010
Application #:
12114867
Filing Dt:
05/05/2008
Publication #:
US20090273095
Pub Dt:
11/05/2009
Title:
RECTANGULAR-SHAPED CONTROLLED COLLAPSE CHIP CONNECTION
70
Patent #:
7522000
Issue Dt:
04/21/2009
Application #:
12114984
Filing Dt:
05/05/2008
Publication #:
US20080204137
Pub Dt:
08/28/2008
Title:
DESIGN STRUCTURE FOR A SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER
71
Patent #:
NONE
Issue Dt:
Application #:
12115051
Filing Dt:
05/05/2008
Publication #:
US20080203546
Pub Dt:
08/28/2008
Title:
QUAD FLAT NO-LEAD CHIP CARRIER WITH STAND-OFF
72
Patent #:
8017514
Issue Dt:
09/13/2011
Application #:
12115056
Filing Dt:
05/05/2008
Publication #:
US20090273084
Pub Dt:
11/05/2009
Title:
OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME
73
Patent #:
7834425
Issue Dt:
11/16/2010
Application #:
12115065
Filing Dt:
05/05/2008
Publication #:
US20080203442
Pub Dt:
08/28/2008
Title:
HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME
74
Patent #:
7528050
Issue Dt:
05/05/2009
Application #:
12115106
Filing Dt:
05/05/2008
Publication #:
US20080206951
Pub Dt:
08/28/2008
Title:
HIGH PERFORMANCE FIELD EFFECT TRANSISTORS ON SOI SUBSTRATE WITH STRESS-INDUCING MATERIAL AS BURIED INSULATOR AND METHODS
75
Patent #:
7890294
Issue Dt:
02/15/2011
Application #:
12115166
Filing Dt:
05/05/2008
Publication #:
US20090327185
Pub Dt:
12/31/2009
Title:
SYSTEMS FOR STRUCTURAL CLUSTERING OF TIME SEQUENCES
76
Patent #:
8004841
Issue Dt:
08/23/2011
Application #:
12115618
Filing Dt:
05/06/2008
Publication #:
US20090277616
Pub Dt:
11/12/2009
Title:
METHOD AND APPARATUS OF WATER COOLING SEVERAL PARALLEL CIRCUIT CARDS EACH CONTAINING SEVERAL CHIP PACKAGES
77
Patent #:
7704854
Issue Dt:
04/27/2010
Application #:
12115690
Filing Dt:
05/06/2008
Publication #:
US20090280619
Pub Dt:
11/12/2009
Title:
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING CONDUCTIVE LINER FOR RAD HARD TOTAL DOSE IMMUNITY
78
Patent #:
7855428
Issue Dt:
12/21/2010
Application #:
12115699
Filing Dt:
05/06/2008
Publication #:
US20090278226
Pub Dt:
11/12/2009
Title:
CONDUCTIVE LINER AT AN INTERFACE BETWEEN A SHALLOW TRENCH ISOLATION STRUCTURE AND A BURIED OXIDE LAYER
79
Patent #:
7943486
Issue Dt:
05/17/2011
Application #:
12115731
Filing Dt:
05/06/2008
Publication #:
US20080206958
Pub Dt:
08/28/2008
Title:
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> SI UNDER BIAXIAL COMPRESSIVE STRAIN
80
Patent #:
7808099
Issue Dt:
10/05/2010
Application #:
12115809
Filing Dt:
05/06/2008
Publication #:
US20090281254
Pub Dt:
11/12/2009
Title:
LIQUID THERMAL INTERFACE HAVING MIXTURE OF LINEARLY STRUCTURED POLYMER DOPED CROSSLINKED NETWORKS AND RELATED METHOD
81
Patent #:
8138603
Issue Dt:
03/20/2012
Application #:
12115817
Filing Dt:
05/06/2008
Publication #:
US20090278260
Pub Dt:
11/12/2009
Title:
REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY
82
Patent #:
NONE
Issue Dt:
Application #:
12115824
Filing Dt:
05/06/2008
Publication #:
US20080275671
Pub Dt:
11/06/2008
Title:
SYSTEMS AND METHODS FOR STRUCTURAL CLUSTERING OF TIME SEQUENCES
83
Patent #:
7692447
Issue Dt:
04/06/2010
Application #:
12115933
Filing Dt:
05/06/2008
Publication #:
US20080284466
Pub Dt:
11/20/2008
Title:
DRIVER CIRCUIT
84
Patent #:
NONE
Issue Dt:
Application #:
12115977
Filing Dt:
05/06/2008
Publication #:
US20090281781
Pub Dt:
11/12/2009
Title:
METHOD AND APPARATUS FOR GENERATING ADAPTIVE NOISE AND TIMING MODELS FOR VLSI SIGNAL INTEGRITY ANALYSIS
85
Patent #:
8054926
Issue Dt:
11/08/2011
Application #:
12116151
Filing Dt:
05/06/2008
Publication #:
US20080209296
Pub Dt:
08/28/2008
Title:
CLOCK AND DATA RECOVERY SYSTEM AND METHOD FOR CLOCK AND DATA RECOVERY BASED ON A FORWARD ERROR CORRECTION
86
Patent #:
7737498
Issue Dt:
06/15/2010
Application #:
12116237
Filing Dt:
05/07/2008
Publication #:
US20090278201
Pub Dt:
11/12/2009
Title:
ENHANCED STRESS-RETENTION SILICON-ON-INSULATOR DEVICES AND METHODS OF FABRICATING ENHANCED STRESS RETENTION SILICON-ON-INSULATOR DEVICES
87
Patent #:
8438001
Issue Dt:
05/07/2013
Application #:
12116248
Filing Dt:
05/07/2008
Publication #:
US20090281750
Pub Dt:
11/12/2009
Title:
METHOD AND APPARATUS FOR IMPROVING NOISE ANALYSIS PERFORMANCE
88
Patent #:
8191245
Issue Dt:
06/05/2012
Application #:
12116317
Filing Dt:
05/07/2008
Publication #:
US20080235942
Pub Dt:
10/02/2008
Title:
METHOD OF FORMING A LAND GRID ARRAY (LGA) INTERPOSER
89
Patent #:
7478291
Issue Dt:
01/13/2009
Application #:
12116345
Filing Dt:
05/07/2008
Publication #:
US20080209256
Pub Dt:
08/28/2008
Title:
MEMORY ARRAY REPAIR WHERE REPAIR LOGIC CANNOT OPERATE AT SAME OPERATING CONDITION AS ARRAY
90
Patent #:
8178908
Issue Dt:
05/15/2012
Application #:
12116470
Filing Dt:
05/07/2008
Publication #:
US20090278207
Pub Dt:
11/12/2009
Title:
AN ELECTRICAL CONTACT STRUCTURE HAVING MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER.
91
Patent #:
NONE
Issue Dt:
Application #:
12116490
Filing Dt:
05/07/2008
Publication #:
US20080203579
Pub Dt:
08/28/2008
Title:
SACRIFICIAL METAL SPACER DUAL DAMASCENE
92
Patent #:
7550359
Issue Dt:
06/23/2009
Application #:
12116626
Filing Dt:
05/07/2008
Title:
METHODS INVOLVING SILICON-ON-INSULATOR TRENCH MEMORY WITH IMPLANTED PLATE
93
Patent #:
8037594
Issue Dt:
10/18/2011
Application #:
12116655
Filing Dt:
05/07/2008
Publication #:
US20080303021
Pub Dt:
12/11/2008
Title:
METHOD OF FORMING A FLIP-CHIP PACKAGE
94
Patent #:
7986543
Issue Dt:
07/26/2011
Application #:
12116771
Filing Dt:
05/07/2008
Publication #:
US20080209126
Pub Dt:
08/28/2008
Title:
METHOD FOR ACHIEVING VERY HIGH BANDWIDTH BETWEEN THE LEVELS OF A CACHE HIERARCHY IN 3-DIMENSIONAL STRUCTURES, AND A 3-DIMENSIONAL STRUCTURE RESULTING THEREFROM
95
Patent #:
7671678
Issue Dt:
03/02/2010
Application #:
12117098
Filing Dt:
05/08/2008
Publication #:
US20080238554
Pub Dt:
10/02/2008
Title:
SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER AND METHOD
96
Patent #:
NONE
Issue Dt:
Application #:
12117232
Filing Dt:
05/08/2008
Publication #:
US20080242016
Pub Dt:
10/02/2008
Title:
METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS
97
Patent #:
NONE
Issue Dt:
Application #:
12117371
Filing Dt:
05/08/2008
Publication #:
US20080203492
Pub Dt:
08/28/2008
Title:
METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS
98
Patent #:
7781321
Issue Dt:
08/24/2010
Application #:
12117769
Filing Dt:
05/09/2008
Publication #:
US20090280631
Pub Dt:
11/12/2009
Title:
ELECTROLESS METAL DEPOSITION FOR DUAL WORK FUNCTION
99
Patent #:
7882455
Issue Dt:
02/01/2011
Application #:
12117784
Filing Dt:
05/09/2008
Publication #:
US20090282375
Pub Dt:
11/12/2009
Title:
CIRCUIT AND METHOD USING DISTRIBUTED PHASE CHANGE ELEMENTS FOR ACROSS-CHIP TEMPERATURE PROFILING
100
Patent #:
7883277
Issue Dt:
02/08/2011
Application #:
12117803
Filing Dt:
05/09/2008
Publication #:
US20080205817
Pub Dt:
08/28/2008
Title:
INTERCONNECTING (MAPPING) A TWO-DIMENSIONAL OPTOELECTRONIC (OE) DEVICE ARRAY TO A ONE-DIMENSIONAL WAVEGUIDE ARRAY
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
06/29/2015
Assignee
1
GLOBALFOUNDRIES U.S. 2 LLC
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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