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Reel/Frame:	036550/0001			Pages:	983
		Recorded:	09/03/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14793
Page 73 of 148
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Patent #:	7870531	Issue Dt:	01/11/2011	Application #:	12117841	Filing Dt:	05/09/2008
Publication #:	US20080216037	Pub Dt:	09/04/2008
Title:	SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP

Patent #:	7537487	Issue Dt:	05/26/2009	Application #:	12117864	Filing Dt:	05/09/2008
Publication #:	US20080207059	Pub Dt:	08/28/2008
Title:	CROSSTALK REDUCTION IN DUAL INLINE MEMORY MODULE (DIMM) CONNECTORS

Patent #:	NONE	Issue Dt:		Application #:	12117934	Filing Dt:	05/09/2008
Publication #:	US20080247633	Pub Dt:	10/09/2008
Title:	SYSTEM FOR GENERATING A SET OF TEST PATTERNS FOR AN OPTICAL PROXIMITY CORRECTION ALGORITHM

Patent #:	7700428	Issue Dt:	04/20/2010	Application #:	12117950	Filing Dt:	05/09/2008
Publication #:	US20090280607	Pub Dt:	11/12/2009
Title:	METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY

Patent #:	8772156	Issue Dt:	07/08/2014	Application #:	12118161	Filing Dt:	05/09/2008
Publication #:	US20090280636	Pub Dt:	11/12/2009
Title:	METHODS OF FABRICATING INTERCONNECT STRUCTURES CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS

Patent #:	7956466	Issue Dt:	06/07/2011	Application #:	12118186	Filing Dt:	05/09/2008
Publication #:	US20090278228	Pub Dt:	11/12/2009
Title:	DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS

Patent #:	7804124	Issue Dt:	09/28/2010	Application #:	12118241	Filing Dt:	05/09/2008
Publication #:	US20090278185	Pub Dt:	11/12/2009
Title:	DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY

Patent #:	7505308	Issue Dt:	03/17/2009	Application #:	12118441	Filing Dt:	05/09/2008
Title:	SYSTEMS INVOLVING SPIN-TRANSFER MAGNETIC RANDOM ACCESS MEMORY

Patent #:	7492631	Issue Dt:	02/17/2009	Application #:	12118496	Filing Dt:	05/09/2008
Title:	METHODS INVOLVING RESETTING SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY

Patent #:	7790538	Issue Dt:	09/07/2010	Application #:	12118689	Filing Dt:	05/10/2008
Publication #:	US20080248616	Pub Dt:	10/09/2008
Title:	INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY

Patent #:	7741165	Issue Dt:	06/22/2010	Application #:	12118776	Filing Dt:	05/12/2008
Publication #:	US20080248635	Pub Dt:	10/09/2008
Title:	POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES

Patent #:	7821099	Issue Dt:	10/26/2010	Application #:	12118875	Filing Dt:	05/12/2008
Publication #:	US20080251846	Pub Dt:	10/16/2008
Title:	STRUCTURE FOR LOW CAPACITANCE ESD ROBUST DIODES

Patent #:	7893520	Issue Dt:	02/22/2011	Application #:	12119125	Filing Dt:	05/12/2008
Publication #:	US20090278229	Pub Dt:	11/12/2009
Title:	EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS

Patent #:	8159040	Issue Dt:	04/17/2012	Application #:	12119526	Filing Dt:	05/13/2008
Publication #:	US20090283840	Pub Dt:	11/19/2009
Title:	METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR

Patent #:	NONE	Issue Dt:		Application #:	12119590	Filing Dt:	05/13/2008
Publication #:	US20080217778	Pub Dt:	09/11/2008
Title:	METHOD TO CREATE FLEXIBLE CONNECTIONS FOR INTEGRATED CIRCUITS

Patent #:	7759168	Issue Dt:	07/20/2010	Application #:	12119654	Filing Dt:	05/13/2008
Publication #:	US20090283876	Pub Dt:	11/19/2009
Title:	ELECTROMAGNETIC INTERFERENCE SHIELD FOR SEMICONDUCTORS USING A CONTINUOUS OR NEAR-CONTINUOUS PERIPHERAL CONDUCTING SEAL AND A CONDUCTING LID

Patent #:	7672560	Issue Dt:	03/02/2010	Application #:	12119748	Filing Dt:	05/13/2008
Publication #:	US20090284684	Pub Dt:	11/19/2009
Title:	COUPLING DEVICE FOR USE IN OPTICAL WAVEGUIDES

Patent #:	7960790	Issue Dt:	06/14/2011	Application #:	12119765	Filing Dt:	05/13/2008
Publication #:	US20080246090	Pub Dt:	10/09/2008
Title:	SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE

Patent #:	7984204	Issue Dt:	07/19/2011	Application #:	12119924	Filing Dt:	05/13/2008
Publication #:	US20090287860	Pub Dt:	11/19/2009
Title:	PROGRAMMABLE DIRECT MEMORY ACCESS CONTROLLER HAVING PIPELINED AND SEQUENTIALLY CONNECTED STAGES

Patent #:	8271857	Issue Dt:	09/18/2012	Application #:	12119975	Filing Dt:	05/13/2008
Publication #:	US20090287982	Pub Dt:	11/19/2009
Title:	CORRECTING ERRORS IN LONGITUDINAL POSITION (LPOS) WORDS

Patent #:	8115303	Issue Dt:	02/14/2012	Application #:	12120029	Filing Dt:	05/13/2008
Publication #:	US20090283902	Pub Dt:	11/19/2009
Title:	SEMICONDUCTOR PACKAGE STRUCTURES HAVING LIQUID COOLERS INTEGRATED WITH FIRST LEVEL CHIP PACKAGE MODULES

Patent #:	8418751	Issue Dt:	04/16/2013	Application #:	12120069	Filing Dt:	05/13/2008
Publication #:	US20090283244	Pub Dt:	11/19/2009
Title:	STACKED AND REDUNDANT CHIP COOLERS

Patent #:	8039331	Issue Dt:	10/18/2011	Application #:	12120286	Filing Dt:	05/14/2008
Publication #:	US20080220581	Pub Dt:	09/11/2008
Title:	OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS

Patent #:	7737794	Issue Dt:	06/15/2010	Application #:	12120331	Filing Dt:	05/14/2008
Publication #:	US20090285344	Pub Dt:	11/19/2009
Title:	PHASE LOCKED LOOP WITH TEMPERATURE AND PROCESS COMPENSATION

Patent #:	7928436	Issue Dt:	04/19/2011	Application #:	12120455	Filing Dt:	05/14/2008
Publication #:	US20080211054	Pub Dt:	09/04/2008
Title:	METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS

Patent #:	NONE	Issue Dt:		Application #:	12120605	Filing Dt:	05/14/2008
Publication #:	US20080251777	Pub Dt:	10/16/2008
Title:	Field Effect Device with a Channel with a Switchable Conductivity

Patent #:	7863126	Issue Dt:	01/04/2011	Application #:	12120658	Filing Dt:	05/15/2008
Publication #:	US20090283838	Pub Dt:	11/19/2009
Title:	FABRICATION OF A CMOS STRUCTURE WITH A HIGH-K DIELECTRIC LAYER OXIDIZING AN ALUMINUM LAYER IN PFET REGION

Patent #:	8146046	Issue Dt:	03/27/2012	Application #:	12120701	Filing Dt:	05/15/2008
Publication #:	US20080216031	Pub Dt:	09/04/2008
Title:	DESIGN STRUCTURES FOR SEMICONDUCTOR STRUCTURES WITH ERROR DETECTION AND CORRECTION

Patent #:	7936017	Issue Dt:	05/03/2011	Application #:	12120836	Filing Dt:	05/15/2008
Publication #:	US20090283828	Pub Dt:	11/19/2009
Title:	REDUCED FLOATING BODY EFFECT WITHOUT IMPACT ON PERFORMANCE-ENHANCING STRESS

Patent #:	8125082	Issue Dt:	02/28/2012	Application #:	12120854	Filing Dt:	05/15/2008
Publication #:	US20080246120	Pub Dt:	10/09/2008
Title:	REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SIGE CONTAINING SUBSTRATES

Patent #:	8053819	Issue Dt:	11/08/2011	Application #:	12120899	Filing Dt:	05/15/2008
Publication #:	US20080203445	Pub Dt:	08/28/2008
Title:	THREE-DIMENSIONAL CASCADED POWER DISTRIBUTION IN A SEMICONDUCTOR DEVICE

Patent #:	NONE	Issue Dt:		Application #:	12120915	Filing Dt:	05/15/2008
Publication #:	US20080211055	Pub Dt:	09/04/2008
Title:	Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit

Patent #:	7906428	Issue Dt:	03/15/2011	Application #:	12121216	Filing Dt:	05/15/2008
Publication #:	US20080220608	Pub Dt:	09/11/2008
Title:	MODIFIED VIA BOTTOM STRUCTURE FOR RELIABILITY ENHANCEMENT

Patent #:	7791105	Issue Dt:	09/07/2010	Application #:	12121286	Filing Dt:	05/15/2008
Publication #:	US20090256174	Pub Dt:	10/15/2009
Title:	DEVICE STRUCTURES FOR A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR MANUFACTURED USING A HYBRID ORIENTATION TECHNOLOGY WAFER AND DESIGN STRUCTURES FOR A HIGH VOLTAGE INTEGRATED CIRCUIT

Patent #:	7937560	Issue Dt:	05/03/2011	Application #:	12121292	Filing Dt:	05/15/2008
Publication #:	US20090287905	Pub Dt:	11/19/2009
Title:	PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS

Patent #:	7687207	Issue Dt:	03/30/2010	Application #:	12121371	Filing Dt:	05/15/2008
Publication #:	US20080244503	Pub Dt:	10/02/2008
Title:	SYSTEM FOR COLORING A PARTIALLY COLORED DESIGN IN AN ALTERNATING PHASE SHIFT MASK

Patent #:	7470616	Issue Dt:	12/30/2008	Application #:	12121378	Filing Dt:	05/15/2008
Title:	DAMASCENE WIRING FABRICATION METHODS INCORPORATING DIELECTRIC CAP ETCH PROCESS WITH HARD MASK RETENTION

Patent #:	8010925	Issue Dt:	08/30/2011	Application #:	12121397	Filing Dt:	05/15/2008
Publication #:	US20080301612	Pub Dt:	12/04/2008
Title:	METHOD AND SYSTEM FOR PLACEMENT OF ELECTRIC CIRCUIT COMPONENTS IN INTEGRATED CIRCUIT DESIGN

Patent #:	7867820	Issue Dt:	01/11/2011	Application #:	12121468	Filing Dt:	05/15/2008
Publication #:	US20080280399	Pub Dt:	11/13/2008
Title:	METHODS FOR FORMING CO-PLANAR WAFER-SCALE CHIP PACKAGES

Patent #:	7687863	Issue Dt:	03/30/2010	Application #:	12121858	Filing Dt:	05/16/2008
Publication #:	US20080217682	Pub Dt:	09/11/2008
Title:	SELECTIVE INCORPORATION OF CHARGE FOR TRANSISTOR CHANNELS

Patent #:	7811879	Issue Dt:	10/12/2010	Application #:	12121875	Filing Dt:	05/16/2008
Publication #:	US20090286368	Pub Dt:	11/19/2009
Title:	PROCESS FOR PCM INTEGRATION WITH POLY-EMITTER BJT AS ACCESS DEVICE

Patent #:	7960237	Issue Dt:	06/14/2011	Application #:	12121922	Filing Dt:	05/16/2008
Publication #:	US20080261369	Pub Dt:	10/23/2008
Title:	STRUCTURE AND METHOD FOR MOSFET WITH REDUCED EXTENSION RESISTANCE

Patent #:	7865340	Issue Dt:	01/04/2011	Application #:	12121962	Filing Dt:	05/16/2008
Publication #:	US20080255813	Pub Dt:	10/16/2008
Title:	PROBABILISTIC REGRESSION SUITES FOR FUNCTIONAL VERIFICATION

Patent #:	7968946	Issue Dt:	06/28/2011	Application #:	12122227	Filing Dt:	05/16/2008
Publication #:	US20080217691	Pub Dt:	09/11/2008
Title:	HIGHER PERFORMANCE CMOS ON (110) WAFERS

Patent #:	NONE	Issue Dt:		Application #:	12122257	Filing Dt:	05/16/2008
Publication #:	US20090283865	Pub Dt:	11/19/2009
Title:	ELECTROCHEMICAL METHOD TO MAKE HIGH QUALITY DOPED CRYSTALLINE COMPOUND SEMICONDUCTORS

Patent #:	7966597	Issue Dt:	06/21/2011	Application #:	12122259	Filing Dt:	05/16/2008
Publication #:	US20080301618	Pub Dt:	12/04/2008
Title:	METHOD AND SYSTEM FOR ROUTING OF INTEGRATED CIRCUIT DESIGN

Patent #:	7870525	Issue Dt:	01/11/2011	Application #:	12122451	Filing Dt:	05/16/2008
Publication #:	US20080216036	Pub Dt:	09/04/2008
Title:	SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS

Patent #:	7842580	Issue Dt:	11/30/2010	Application #:	12122754	Filing Dt:	05/19/2008
Publication #:	US20090283854	Pub Dt:	11/19/2009
Title:	DESIGN STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS

Patent #:	8001501	Issue Dt:	08/16/2011	Application #:	12122785	Filing Dt:	05/19/2008
Publication #:	US20090288046	Pub Dt:	11/19/2009
Title:	METHOD FOR CIRCUIT DESIGN

Patent #:	8039929	Issue Dt:	10/18/2011	Application #:	12122788	Filing Dt:	05/19/2008
Publication #:	US20080217692	Pub Dt:	09/11/2008
Title:	ASYMMETRICALLY STRESSED CMOS FINFET

Patent #:	9046788	Issue Dt:	06/02/2015	Application #:	12122929	Filing Dt:	05/19/2008
Publication #:	US20090284722	Pub Dt:	11/19/2009
Title:	METHOD FOR MONITORING FOCUS ON AN INTEGRATED WAFER

Patent #:	7652279	Issue Dt:	01/26/2010	Application #:	12122969	Filing Dt:	05/19/2008
Publication #:	US20080210925	Pub Dt:	09/04/2008
Title:	THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS

Patent #:	7951424	Issue Dt:	05/31/2011	Application #:	12122981	Filing Dt:	05/19/2008
Publication #:	US20090117277	Pub Dt:	05/07/2009
Title:	SELECTIVE PLACEMENT OF CARBON NANOTUBES ON OXIDE SURFACES

Patent #:	7923838	Issue Dt:	04/12/2011	Application #:	12122984	Filing Dt:	05/19/2008
Publication #:	US20080211100	Pub Dt:	09/04/2008
Title:	METHOD AND STRUCTURE FOR REDUCING CONTACT RESISTANCE BETWEEN SILICIDE CONTACT AND OVERLYING METALLIZATION

Patent #:	7486107	Issue Dt:	02/03/2009	Application #:	12123487	Filing Dt:	05/20/2008
Title:	METHOD FOR EXTENDING LIFETIME RELIABILITY OF DIGITAL LOGIC DEVICES THROUGH REVERSAL OF AGING MECHANISMS

Patent #:	7489161	Issue Dt:	02/10/2009	Application #:	12123489	Filing Dt:	05/20/2008
Title:	METHOD FOR EXTENDING LIFETIME RELIABILITY OF DIGITAL LOGIC DEVICES THROUGH REMOVAL OF AGING MECHANISMS

Patent #:	8228112	Issue Dt:	07/24/2012	Application #:	12123735	Filing Dt:	05/20/2008
Publication #:	US20090102542	Pub Dt:	04/23/2009
Title:	SWITCH WITH REDUCED INSERTION LOSS

Patent #:	7968456	Issue Dt:	06/28/2011	Application #:	12123799	Filing Dt:	05/20/2008
Publication #:	US20080217777	Pub Dt:	09/11/2008
Title:	METHOD OF FORMING AN EMBEDDED BARRIER LAYER FOR PROTECTION FROM CHEMICAL MECHANICAL POLISHING PROCESS

Patent #:	8130887	Issue Dt:	03/06/2012	Application #:	12124106	Filing Dt:	05/20/2008
Publication #:	US20080285695	Pub Dt:	11/20/2008
Title:	METHOD AND ARRANGEMENTS FOR LINK POWER REDUCTION

Patent #:	7791124	Issue Dt:	09/07/2010	Application #:	12124186	Filing Dt:	05/21/2008
Publication #:	US20090289291	Pub Dt:	11/26/2009
Title:	SOI DEEP TRENCH CAPACITOR EMPLOYING A NON-CONFORMAL INNER SPACER

Patent #:	NONE	Issue Dt:		Application #:	12124275	Filing Dt:	05/21/2008
Publication #:	US20080299720	Pub Dt:	12/04/2008
Title:	STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION

Patent #:	7727505	Issue Dt:	06/01/2010	Application #:	12124278	Filing Dt:	05/21/2008
Publication #:	US20090291041	Pub Dt:	11/26/2009
Title:	METHODS FOR SEPERATING CARBON NANOTUBES BY ENHANCING THE DENSITY DIFFERENTIAL

Patent #:	7541855	Issue Dt:	06/02/2009	Application #:	12124384	Filing Dt:	05/21/2008
Publication #:	US20080218201	Pub Dt:	09/11/2008
Title:	CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING

Patent #:	7765673	Issue Dt:	08/03/2010	Application #:	12124388	Filing Dt:	05/21/2008
Publication #:	US20090044403	Pub Dt:	02/19/2009
Title:	METHOD FOR IMPROVING POWER DISTRIBUTION CURRENT MEASUREMENT ON PRINTED CIRCUIT BOARDS

Patent #:	7646070	Issue Dt:	01/12/2010	Application #:	12124410	Filing Dt:	05/21/2008
Publication #:	US20080217694	Pub Dt:	09/11/2008
Title:	SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS)

Patent #:	8225255	Issue Dt:	07/17/2012	Application #:	12124472	Filing Dt:	05/21/2008
Publication #:	US20090290401	Pub Dt:	11/26/2009
Title:	PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS

Patent #:	7533011	Issue Dt:	05/12/2009	Application #:	12124520	Filing Dt:	05/21/2008
Publication #:	US20080221853	Pub Dt:	09/11/2008
Title:	SIMULATING AND VERIFYING SIGNAL GLITCHING

Patent #:	8108822	Issue Dt:	01/31/2012	Application #:	12124551	Filing Dt:	05/21/2008
Publication #:	US20090070718	Pub Dt:	03/12/2009
Title:	METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY

Patent #:	7480888	Issue Dt:	01/20/2009	Application #:	12124771	Filing Dt:	05/21/2008
Title:	DESIGN STRUCTURE FOR FACILITATING ENGINEERING CHANGES IN INTEGRATED CIRCUITS

Patent #:	8405950	Issue Dt:	03/26/2013	Application #:	12125007	Filing Dt:	05/21/2008
Publication #:	US20090290278	Pub Dt:	11/26/2009
Title:	CABLE HAVING ESD DISSIPATIVE LAYER ELECTRICALLY COUPLED TO LEADS THEREOF

Patent #:	7794561	Issue Dt:	09/14/2010	Application #:	12125081	Filing Dt:	05/22/2008
Publication #:	US20090107630	Pub Dt:	04/30/2009
Title:	MECHANICALLY DECOUPLED OPTO-MECHANICAL CONNECTOR FOR FLEXIBLE OPTICAL WAVEGUIDES EMBEDDED AND/OR ATTACHED TO A PRINTED CIRCUIT BOARD

Patent #:	7927968	Issue Dt:	04/19/2011	Application #:	12125106	Filing Dt:	05/22/2008
Publication #:	US20080220587	Pub Dt:	09/11/2008
Title:	DUAL STRESS STI

Patent #:	8017499	Issue Dt:	09/13/2011	Application #:	12125175	Filing Dt:	05/22/2008
Publication #:	US20080220588	Pub Dt:	09/11/2008
Title:	STRAINED SI MOSFET ON TENSILE-STRAINED SIGE-ON-INSULATOR (SGOI)

Patent #:	7904872	Issue Dt:	03/08/2011	Application #:	12125255	Filing Dt:	05/22/2008
Publication #:	US20090292828	Pub Dt:	11/26/2009
Title:	SYSTEM-ON-CHIP (SOC), DESIGN STRUCTURE AND METHOD

Patent #:	7904873	Issue Dt:	03/08/2011	Application #:	12125269	Filing Dt:	05/22/2008
Publication #:	US20090291533	Pub Dt:	11/26/2009
Title:	SYSTEM-ON-CHIP (SOC), DESIGN STRUCTURE AND METHOD

Patent #:	7655985	Issue Dt:	02/02/2010	Application #:	12125381	Filing Dt:	05/22/2008
Publication #:	US20080217698	Pub Dt:	09/11/2008
Title:	METHODS AND SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION USING A CONDUCTIVE REGION

Patent #:	8003453	Issue Dt:	08/23/2011	Application #:	12125501	Filing Dt:	05/22/2008
Publication #:	US20080227259	Pub Dt:	09/18/2008
Title:	SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS

Patent #:	7750418	Issue Dt:	07/06/2010	Application #:	12125508	Filing Dt:	05/22/2008
Publication #:	US20080217747	Pub Dt:	09/11/2008
Title:	INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES

Patent #:	7826251	Issue Dt:	11/02/2010	Application #:	12125637	Filing Dt:	05/22/2008
Publication #:	US20090290439	Pub Dt:	11/26/2009
Title:	HIGH PERFORMANCE METAL GATE POLYGATE 8 TRANSISTOR SRAM CELL WITH REDUCED VARIABILITY

Patent #:	7595554	Issue Dt:	09/29/2009	Application #:	12125971	Filing Dt:	05/23/2008
Publication #:	US20080217731	Pub Dt:	09/11/2008
Title:	AN INTERCONNECT STRUCTURE WITH DIELECTRIC AIR GAPS

Patent #:	7932514	Issue Dt:	04/26/2011	Application #:	12126015	Filing Dt:	05/23/2008
Publication #:	US20090289638	Pub Dt:	11/26/2009
Title:	MICROWAVE READOUT FOR FLUX-BIASED QUBITS

Patent #:	8563225	Issue Dt:	10/22/2013	Application #:	12126245	Filing Dt:	05/23/2008
Publication #:	US20090291388	Pub Dt:	11/26/2009
Title:	FORMING A SELF-ALIGNED HARD MASK FOR CONTACT TO A TUNNEL JUNCTION

Patent #:	7919225	Issue Dt:	04/05/2011	Application #:	12126287	Filing Dt:	05/23/2008
Publication #:	US20090291389	Pub Dt:	11/26/2009
Title:	PHOTOPATTERNABLE DIELECTRIC MATERIALS FOR BEOL APPLICATIONS AND METHODS FOR USE

Patent #:	8108609	Issue Dt:	01/31/2012	Application #:	12126499	Filing Dt:	05/23/2008
Publication #:	US20090144492	Pub Dt:	06/04/2009
Title:	STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE

Patent #:	7538006	Issue Dt:	05/26/2009	Application #:	12126866	Filing Dt:	05/24/2008
Title:	ANNULAR DAMASCENE VERTICAL NATURAL CAPACITOR

Patent #:	8054736	Issue Dt:	11/08/2011	Application #:	12126967	Filing Dt:	05/26/2008
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Title:	STORAGE DEVICE HAVING FLEXIBLE ARCHITECTURE AND FREE SCALABILITY

Patent #:	7781273	Issue Dt:	08/24/2010	Application #:	12127033	Filing Dt:	05/27/2008
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Title:	SEMICONDUCTOR STRUCTUE WITH MULTIPLE FINS HAVING DIFFERENT CHANNEL REGION HEIGHTS AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE

Patent #:	7911025	Issue Dt:	03/22/2011	Application #:	12127080	Filing Dt:	05/27/2008
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Title:	FUSE/ANTI-FUSE STRUCTURE AND METHODS OF MAKING AND PROGRAMMING SAME

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Title:	SINGLE PASS VARIABLE BIT RATE CONTROL STRATEGY AND ENCODER FOR PROCESSING A VIDEO FRAME OF A SEQUENCE OF VIDEO FRAMES

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Title:	CONTROL OF POLY-SI DEPLETION IN CMOS VIA GAS PHASE DOPING

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Title:	STRUCTURE FOR A STACKED POWER CLAMP HAVING A BIGFET GATE PULL-UP CIRCUIT

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Title:	METALIZED ELASTOMERIC ELECTRICAL CONTACTS

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Title:	METHOD AND APPARATUS FOR END-TO-END NETWORK CONGESTION MANAGEMENT

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Title:	SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE

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Title:	Design Structure for Localized Control Caching Resulting in Power Efficient Control Logic

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Title:	METHOD AND SYSTEM FOR TESTING BIT FAILURES IN ARRAY ELEMENTS OF AN ELECTRONIC CIRCUIT

100

Patent #:	NONE	Issue Dt:		Application #:	12127909	Filing Dt:	05/28/2008
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Title:	PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES USING EXTERNALLY HEATED PHASE CHANGE MATERIAL

Assignor

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt:

06/29/2015

Assignee

GLOBALFOUNDRIES U.S. 2 LLC

2070 ROUTE 52

HOPEWELL JUNCTION, NEW YORK 12533

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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