|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12146798
|
Filing Dt:
|
06/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
SOLDER INTERCONNECTION ARRAY WITH OPTIMAL MECHANICAL INTEGRITY
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|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
12146852
|
Filing Dt:
|
06/26/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
TECHNIQUES FOR THERMAL MODELING OF DATA CENTERS TO IMPROVE ENERGY EFFICIENCY
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|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
|
Application #:
|
12147024
|
Filing Dt:
|
06/26/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES
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|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12147670
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
CIRCUIT STRUCTURE AND METHOD FOR DIGITAL INTEGRATED CIRCUIT PERFORMANCE SCREENING
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|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12147685
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
SMI MEMORY READ DATA CAPTURE MARGIN CHARACTERIZATION CIRCUITS AND METHODS
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|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12154003
|
Filing Dt:
|
05/19/2008
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING
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|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
12154304
|
Filing Dt:
|
05/22/2008
|
Publication #:
|
|
Pub Dt:
|
09/25/2008
| | | | |
Title:
|
STRUCTURE FOR MODELING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS
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|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
12154568
|
Filing Dt:
|
05/23/2008
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
TRANSPARENT HARD COATS FOR OPTICAL ELEMENTS
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|
|
Patent #:
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|
Issue Dt:
|
03/27/2012
|
Application #:
|
12154796
|
Filing Dt:
|
05/27/2008
|
Publication #:
|
|
Pub Dt:
|
12/03/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR OUT OF BAND SIGNALING ENHANCEMENT FOR HIGH SPEED SERIAL DRIVER
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|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12163025
|
Filing Dt:
|
06/27/2008
|
Publication #:
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|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
DESIGN STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
06/21/2011
|
Application #:
|
12163172
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
STRUCTURE TO FACILITATE PLATING INTO HIGH ASPECT RATIO VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12163318
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
Title:
|
CHARGE-BASED CIRCUIT ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
12163389
|
Filing Dt:
|
06/27/2008
|
Publication #:
|
|
Pub Dt:
|
01/29/2009
| | | | |
Title:
|
EPITAXIAL AND POLYCRYSTALLINE GROWTH OF SI1-X-YGEXCY AND SI1-YCY ALLOY LAYERS ON SI BY UHV-CVD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12164152
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
QUAD FLAT NO-LEAD CHIP CARRIER WITH STANDOFF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12164447
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
PRODUCTION OF INTEGRATED CIRCUIT CHIP PACKAGES PROHIBITING FORMATION OF MICRO SOLDER BALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12164478
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12164576
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
Title:
|
METHOD OF OBTAINING ENHANCED LOCALIZED THERMAL INTERFACE REGIONS BY PARTICLE STACKING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
12164580
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
CMOS COMPATIBLE INTEGRATED DIELECTRIC OPTICAL WAVEGUIDE COUPLER AND FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12164599
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
NONLITHOGRAPHIC METHOD TO PRODUCE SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITIONS FOR SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12164603
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
SYSTEM FOR MONITORING MULTI-ORDERABLE MEASUREMENT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12164647
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SELECTIVELY COATED SELF-ALIGNED MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12164690
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
02/05/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12164781
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
Title:
|
USING CONSTRAINTS IN DESIGN VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12164869
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
EFFICIENT MEMORY PRODUCT FOR TEST AND SOFT REPAIR OF SRAM WITH REDUNDANCY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12165009
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR ONLINE SAMPLE INTERVAL DETERMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12165134
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR SENSOR REPLICATION FOR ENSEMBLE AVERAGING IN MICRO-ELECTROMECHANICAL SYSTEM (MEMS)
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
12165355
|
Filing Dt:
|
06/30/2008
|
Title:
|
ERROR DETECTION ENHANCEMENT IN A MICROPROCESSOR THROUGH THE USE OF A SECOND DEPENDENCY MATRIX
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12165530
|
Filing Dt:
|
06/30/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
HIGH DENSITY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12166285
|
Filing Dt:
|
07/01/2008
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
ULTRA THIN CHANNEL (UTC) MOSFET STRUCTURE FORMED ON BOX REGIONS HAVING DIFFERENT DEPTHS AND DIFFERENT THICKNESSES BENEATH THE UTC AND SOURCEDRAIN REGIONS AND METHOD OF MANUFACTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12166311
|
Filing Dt:
|
07/01/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12166362
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
STRUCTURE FOR CHARGE DISSIPATION DURING FABRICATION OF INTEGRATED CIRCUITS AND ISOLATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
12166373
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
TOOL FOR FILLING VIAS IN A GREENSHEET
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12166523
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
SOLDER STANDOFFS FOR INJECTION MOLDING OF SOLDER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12166550
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
SYSTEM AND METHOD FOR MODELING I/O SIMULTANEOUS SWITCHING NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12166571
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
ACCESS TABLE LOOKUP FOR BUS BRIDGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12166623
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
PASSIVE ELECTRICALLY TESTABLE ACCELERATION AND VOLTAGE MEASUREMENT DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12166690
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12166773
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
Title:
|
PLANAR ARRAY CONTACT MEMORY CARDS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12166811
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SYSTEM AND COMPUTER PROGRAM FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12166934
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
PHASE CHANGE MEMORY PROGRAMMING METHOD WITHOUT RESET OVER-WRITE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12166958
|
Filing Dt:
|
07/02/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
SPUTTERING TARGET FIXTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
12167275
|
Filing Dt:
|
07/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
METHOD, SYSTEM, AND STORAGE MEDIUM FOR PROVIDING CONTINUOUS COMMUNICATION BETWEEN PROCESS EQUIPMENT AND AN AUTOMATED MATERIAL HANDLING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
12167300
|
Filing Dt:
|
07/03/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
COLUMN SELECTABLE SELF-BIASING VIRTUAL VOLTAGES FOR SRAM WRITE ASSIST
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12167686
|
Filing Dt:
|
07/03/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12167817
|
Filing Dt:
|
07/03/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12167947
|
Filing Dt:
|
07/03/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
Method, System and Computer Program for Operational-Risk Modeling
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12168153
|
Filing Dt:
|
07/06/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
SLEW CONSTRAINED MINIMUM COST BUFFERING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12168310
|
Filing Dt:
|
07/07/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
SYSTEM AND METHOD FOR PROJECTION LITHOGRAPHY WITH IMMERSED IMAGE-ALIGNED DIFFRACTIVE ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12168328
|
Filing Dt:
|
07/07/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES HAVING CHARACTERISTICS SUITABLE FOR MASS PRODUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12168793
|
Filing Dt:
|
07/07/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR UNFOLDING/REPLICATING LOGIC PATHS TO FACILITATE MODELING OF METASTABLE VALUE PROPAGATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12168945
|
Filing Dt:
|
07/08/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
METHOD FOR IMPROVING SEMICONDUCTOR SURFACES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12169118
|
Filing Dt:
|
07/08/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12169664
|
Filing Dt:
|
07/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12169667
|
Filing Dt:
|
07/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12169668
|
Filing Dt:
|
07/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2009
|
Application #:
|
12169670
|
Filing Dt:
|
07/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
INCREASE PRODUCTIVITY AT WAFER TEST USING PROBE RETEST DATA ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12169674
|
Filing Dt:
|
07/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12169705
|
Filing Dt:
|
07/09/2008
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Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
METHODS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS
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|
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Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12169727
|
Filing Dt:
|
07/09/2008
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Publication #:
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Pub Dt:
|
03/26/2009
| | | | |
Title:
|
FORMING SOI TRENCH MEMORY WITH SINGLE-SIDED BURIED STRAP
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|
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Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12169806
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Filing Dt:
|
07/09/2008
|
Publication #:
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|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
METHODS AND SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION USING A CONDUCTIVE REGION
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|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
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Application #:
|
12169991
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Filing Dt:
|
07/09/2008
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Publication #:
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Pub Dt:
|
11/27/2008
| | | | |
Title:
|
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
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Application #:
|
12170459
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Filing Dt:
|
07/10/2008
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Publication #:
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Pub Dt:
|
01/14/2010
| | | | |
Title:
|
FORMATION OF SOI BY OXIDATION OF SILICON WITH ENGINEERED POROSITY GRADIENT
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|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
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Application #:
|
12170462
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Filing Dt:
|
07/10/2008
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Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
SOFT ERROR CORRECTION IN SLEEPING PROCESSORS
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|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12170634
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Filing Dt:
|
07/10/2008
|
Publication #:
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|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST
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|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12170687
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Filing Dt:
|
07/10/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
METHODS FOR FORMING HIGH PERFORMANCE GATES AND STRUCTURES THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
12170722
|
Filing Dt:
|
07/10/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
FORMING SUB-LITHOGRAPHIC PATTERNS USING DOUBLE EXPOSURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
12170956
|
Filing Dt:
|
07/10/2008
|
Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
Title:
|
METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES USING RIE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
12170993
|
Filing Dt:
|
07/10/2008
|
Title:
|
CIRCUIT FOR IMPROVED SRAM WRITE AROUND WITH REDUCED READ ACCESS PENALTY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
12171602
|
Filing Dt:
|
07/11/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
ELECTRICALLY OPTIMIZED AND STRUCTURALLY PROTECTED VIA STRUCTURE FOR HIGH SPEED SIGNALS
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|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12172233
|
Filing Dt:
|
07/12/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
SELF-SEGREGATING MULTILAYER IMAGING STACK WITH BUILT-IN ANTIREFLECTIVE PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12172300
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
Title:
|
APPARATUS, AND COMPUTER PROGRAM FOR IMPLEMENTING VERTICALLY COUPLED NOISE CONTROL THROUGH A MESH PLANE IN AN ELECTRONIC PACKAGE DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12172452
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
WAFER SCALE MEMBRANE FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12172557
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
METHOD AND SYSTEM FOR CREATING AN IN-MEMORY PHYSICAL DICTIONARY FOR DATA COMPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2009
|
Application #:
|
12172656
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
LIMITED SWITCH DYNAMIC LOGIC CELL BASED REGISTER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12172778
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
Multipath Soldered Thermal Interface Between a Chip and its Heat Sink
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12172876
|
Filing Dt:
|
07/14/2008
|
Publication #:
|
|
Pub Dt:
|
01/14/2010
| | | | |
Title:
|
TRANSMISSION ELECTRON MICROSCOPY SAMPLE ETCHING FIXTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/2010
|
Application #:
|
12173070
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
A METHOD OF CREATING A LOAD BALANCED SPATIAL PARTITIONING OF A STRUCTURED, DIFFUSING SYSTEM OF PARTICLES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
12173093
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
PROCESSOR DEDICATED CODE HANDLING IN A MULTI-PROCESSOR ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
12173098
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12173140
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING PULSEWIDTH MODULATION FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12173159
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
PHASE-LOCKED LOOP CIRCUITS AND METHODS IMPLEMENTING MULTIPLEXER CIRCUIT FOR FINE TUNING CONTROL OF DIGITALLY CONTROLLED OSCILLATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
12173280
|
Filing Dt:
|
07/15/2008
|
Title:
|
SILICON ON INSULATOR DEVICES HAVING BODY-TIED-TO-SOURCE AND METHODS OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12173289
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
LOW PASS METAL POWDER FILTER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12173346
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
CONDUCTIVE BONDING MATERIAL FILL TECHNIQUES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12173406
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
PHASE CHANGE MEMORY ELEMENT WITH PHASE-CHANGE ELECTRODES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12173407
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
INTEGRATED CIRCUITS COMPRISING RESISTORS HAVING DIFFERENT SHEET RESISTANCES AND METHODS OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12173573
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
INHIBITION OF METAL DIFFUSION ARISING FROM LASER DICING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
12173642
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12173651
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
SYSTEM AND METHOD FOR DIGITAL LOGIC TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12173803
|
Filing Dt:
|
07/15/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
PREVENTION AND CONTROL OF INTERMETALLIC ALLOY INCLUSIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12173857
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/29/2009
| | | | |
Title:
|
OPTICAL SPOT GEOMETRIC PARAMETER DETERMINATION USING CALIBRATION TARGETS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12173899
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/22/2009
| | | | |
Title:
|
METHODS FOR FORMING DIELECTRIC INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12174074
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
Title:
|
STRUCTURE AND METHOD FOR ENHANCING RESISTANCE TO FRACTURE OF BONDING PADS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12174198
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12174264
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12174289
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12174312
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
Error Recovery During Execution Of An Application On A Parallel Computer
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12174407
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
01/21/2010
| | | | |
Title:
|
CONSTRUCTING A COMPREHENSIVE SUMMARY OF AN EVENT SEQUENCE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12174543
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
STRUCTURE FOR A LIMITED SWITCH DYNAMIC LOGIC CELL BASED REGISTER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12174572
|
Filing Dt:
|
07/16/2008
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR GLITCHLESS CLOCK MULTIPLEXER OPTIMIZED FOR SYNCHRONOUS AND ASYNCHRONOUS CLOCKS
|
|