|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12317691
|
Filing Dt:
|
12/26/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METHOD OF FABRICATING A PORTABLE COMPUTER APPARATUS WITH THERMAL ENHANCEMENTS AND MULTIPLE POWER MODES OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
12323512
|
Filing Dt:
|
11/26/2008
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
Title:
|
METHODS FOR SELECTIVE REVERSE MASK PLANARIZATION AND INTERCONNECT STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12324151
|
Filing Dt:
|
11/26/2008
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
Title:
|
SEMICONDUCTOR NANOWIRE ELECTROMAGNETIC RADIATION SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12324170
|
Filing Dt:
|
11/26/2008
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
Title:
|
IN-SITU DESIGN METHOD AND SYSTEM FOR IMPROVED MEMORY YIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12324219
|
Filing Dt:
|
11/26/2008
|
Publication #:
|
|
Pub Dt:
|
05/27/2010
| | | | |
Title:
|
SEMICONDUCTOR NANOWIRES CHARGE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12325195
|
Filing Dt:
|
11/29/2008
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
Title:
|
PHOTO DETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12325774
|
Filing Dt:
|
12/01/2008
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
APPARATUS AND COMPUTER PROGRAM PRODUCT FOR SEMICONDUCTOR YIELD ESTIMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12326143
|
Filing Dt:
|
12/02/2008
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
EDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12328026
|
Filing Dt:
|
12/04/2008
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
GROUPS OF LAND GRID INTERPOSERS OF DIFFERENT HEIGHTS HAVING METAL-ON ELASTOMER HEMI-TORUS SHAPES PROVIDING FOR ELECTRICAL CONTACT WITH AT LEAST ONE COMPONENT ON AN OPPOSITE SIDE OF AN ELECTRICALLY INSULATING CARRIER PLATE MOUNTING INTERPOSERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
12328358
|
Filing Dt:
|
12/04/2008
|
Publication #:
|
|
Pub Dt:
|
03/26/2009
| | | | |
Title:
|
METHOD AND STRUCTURE FOR IMPROVING DEVICE PERFORMANCE VARIATION IN DUAL STRESS LINER TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
12329133
|
Filing Dt:
|
12/05/2008
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
MEMORY CIRCUIT WITH DECOUPLED READ AND WRITE BIT LINES AND IMPROVED WRITE STABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12329868
|
Filing Dt:
|
12/08/2008
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
Title:
|
PREDICTING WAFER FAILURE USING LEARNED PROBABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12330664
|
Filing Dt:
|
12/09/2008
|
Publication #:
|
|
Pub Dt:
|
06/10/2010
| | | | |
Title:
|
FAST ROUTING OF CUSTOM MACROS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12330890
|
Filing Dt:
|
12/09/2008
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
IMPLEMENTING A SERIALIZATION CONSTRUCT WITHIN AN ENVIRONMENT OF PARALLEL DATA FLOW GRAPHS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12331158
|
Filing Dt:
|
12/09/2008
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
VARACTOR BANK SWITCHING BASED ON NEGATIVE CONTROL VOLTAGE GENERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12334746
|
Filing Dt:
|
12/15/2008
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
FULLY AND UNIFORMLY SILICIDED GATE STRUCTURE AND METHOD FOR FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12335575
|
Filing Dt:
|
12/16/2008
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
STABILIZATION OF VINYL ETHER MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12335761
|
Filing Dt:
|
12/16/2008
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
BRIDGE FOR SEMICONDUCTOR INTERNAL NODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12335766
|
Filing Dt:
|
12/16/2008
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
Title:
|
MODEL BUILD IN THE PRESENCE OF A NON-BINDING REFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12336904
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
SCANNING PROBE-BASED LITHOGRAPHY METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12336922
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
Title:
|
METHOD FOR USING A TOPCOAT COMPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
12337004
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
|
TOPCOAT COMPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12337061
|
Filing Dt:
|
12/17/2008
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
IDENTIFYING PARASITIC DIODE(S) IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12338092
|
Filing Dt:
|
12/18/2008
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
MICROJET MODULE ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/2010
|
Application #:
|
12338275
|
Filing Dt:
|
12/18/2008
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2013
|
Application #:
|
12338692
|
Filing Dt:
|
12/18/2008
|
Publication #:
|
|
Pub Dt:
|
03/04/2010
| | | | |
Title:
|
NANOPOROUS MEDIA WITH LAMELLAR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2010
|
Application #:
|
12341079
|
Filing Dt:
|
12/22/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
IMPLEMENTING POWER SAVINGS IN HSS CLOCK-GATING CIRCUIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12341856
|
Filing Dt:
|
12/22/2008
|
Publication #:
|
|
Pub Dt:
|
06/04/2009
| | | | |
Title:
|
REDUCED ELECTROMIGRATION AND STRESSED INDUCED MIGRATION OF CU WIRES BY SURFACE COATING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12342194
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
BAND EDGE ENGINEERED VT OFFSET DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12342228
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
DESIGN STRUCTURE AND METHOD FOR AN ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12342335
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
BIAS VOLTAGE GENERATION CIRCUIT FOR AN SOI RADIO FREQUENCY SWITCH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
12342353
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
04/16/2009
| | | | |
Title:
|
IC LAYOUT OPTIMIZATION TO IMPROVE YIELD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12342373
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12342430
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
METHOD FOR FORMING THIN FILM RESISTOR AND TERMINAL BOND PAD SIMULTANEOUSLY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12342488
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
SOI RADIO FREQUENCY SWITCH FOR REDUCING HIGH FREQUENCY HARMONICS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12342527
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
SOI RADIO FREQUENCY SWITCH WITH ENHANCED SIGNAL FIDELITY AND ELECTRICAL ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12342609
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
DEEP TRENCH VARACTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
12342655
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
PROCESS FOR FABRICATION OF FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12342677
|
Filing Dt:
|
12/23/2008
|
Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
|
HIGH PERFORMANCE MOSFET COMPRISING A STRESSED GATE METAL SILICIDE LAYER AND METHOD OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12343528
|
Filing Dt:
|
12/24/2008
|
Publication #:
|
|
Pub Dt:
|
06/24/2010
| | | | |
Title:
|
BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12343686
|
Filing Dt:
|
12/24/2008
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT CHIP DESIGN FLOW METHODOLOGY INCLUDING INSERTION OF ON-CHIP OR SCRIBE LINE WIRELESS PROCESS MONITORING AND FEEDBACK CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
12344052
|
Filing Dt:
|
12/24/2008
|
Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
|
Run-Time Characterization of On-Demand Analytical Model Accuracy
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12344095
|
Filing Dt:
|
12/24/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD AND MANUFACTURE OF SILICON BASED PACKAGE AND DEVICES MANUFACTURED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
12344651
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
METHODS OF OPERATING A NANOPROBER TO ELECTRICALLY PROBE A DEVICE STRUCTURE OF AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
12344697
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
12344711
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12344724
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
EXTRACTING CONSISTENT COMPACT MODEL PARAMETERS FOR RELATED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12344725
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
RANDOM PERSONALIZATION OF CHIPS DURING FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12344733
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
TRENCH FORMING METHOD AND STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2011
|
Application #:
|
12344774
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12344802
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12344838
|
Filing Dt:
|
12/29/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12345906
|
Filing Dt:
|
12/30/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
METHOD OF MIGRATING ELECTRONIC DEVICES OPERATING IN CURRENT MODE TO A TARGET TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12346040
|
Filing Dt:
|
12/30/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
A METHOD OF FORMING AN INTERCONNECT STRUCTURE INCLUDING A METALLIC INTERFACIAL LAYER LOCATED AT A BOTTOM VIA PORTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
12346308
|
Filing Dt:
|
12/30/2008
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
METHOD AND STRUCTURE FOR VARIABLE PITCH MICROWAVE PROBE ASSEMBLY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12347490
|
Filing Dt:
|
12/31/2008
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12347947
|
Filing Dt:
|
12/31/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR AN APPARATUS FOR MONITORING AND CONTROLLING HEAT GENERATION IN A MULTI-CORE PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
12348034
|
Filing Dt:
|
01/02/2009
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
RECONSTRUCTION OF DATA FROM SIMULATION MODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
12348035
|
Filing Dt:
|
01/02/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
RECONSTRUCTION OF DATA FROM SIMULATION MODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12348070
|
Filing Dt:
|
01/02/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
METHOD FOR COMPUTING THE SENSISTIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12348163
|
Filing Dt:
|
01/02/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
REFLECTIVE PHASE SHIFTER AND METHOD OF PHASE SHIFTING USING A HYBRID COUPLER WITH VERTICAL COUPLING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12348344
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12348380
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/23/2009
| | | | |
Title:
|
METHOD FOR OPTIMIZING OF PIPELINE STRUCTURE PLACEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12348391
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SOI CMOS CIRCUITS WITH SUBSTRATE BIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12348404
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
12348434
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
TEST STRUCTURE FOR ELECTROMIGRATION ANALYSIS AND RELATED METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
12348438
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
GROUNDING FRONT-END-OF-LINE STRUCTURES ON A SOI SUBSTRATE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12348549
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
EQUIVALENT GATE COUNT YIELD ESTIMATION FOR INTEGRATED CIRCUIT DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12348707
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING HIGH-Q WAFER BACK-SIDE CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12348779
|
Filing Dt:
|
01/05/2009
|
Title:
|
UNIDIRECTIONAL RACETRACK MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12348934
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12348939
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
TRENCH MEMORY WITH MONOLITHIC CONDUCTING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12349018
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12349094
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
OPC MODEL CALIBRATION PROCESS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12349385
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
CIRCUIT FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12349877
|
Filing Dt:
|
01/07/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
EXECUTING AN OVERALL QUANTITY OF DATA PROCESSING WITHIN AN OVERALL PROCESSING PERIOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12350250
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
SUBSTRATE PLANARIZATION WITH IMPRINT MATERIALS AND PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12350251
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
METHODOLOGY OF PLACING PRINTING ASSIST FEATURE FOR RANDOM MASK LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12350306
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
TEST AND BRING-UP OF AN ENHANCED CASCADE INTERCONNECT MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12350312
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12350329
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
LOGIC ELEMENT, AND INTEGRATED CIRCUIT OR FIELD PROGRAMMABLE GATE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
12350469
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
PROGRAMMABLE ELEMENT, AND MEMORY DEVICE OR LOGIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12350991
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
PHOTO DETECTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12351010
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
AUTOMATED DYNAMIC METROLOGY SAMPLING SYSTEM AND METHOD FOR PROCESS CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12351201
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
SIMULATING AN OPERATION OF A DIGITAL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12351263
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12351272
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
STRUCTURE AND METHOD OF FORMING METAL INTERCONNECT STRUCTURES IN ULTRA LOW-K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12351436
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
STRUCTURE AND METHOD FOR BACK END OF THE LINE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12351738
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
ECC INTERLEAVING FOR MULTI-TRACK RECORDING ON MAGNETIC TAPE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12351872
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
MEMORY ELEMENTS AND METHODS OF USING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
12351908
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12352051
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
METHOD FOR REDUCING TIP-TO-TIP SPACING BETWEEN LINES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12352052
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
12352071
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12352077
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12352135
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SINGLE PASS VARIABLE BIT RATE CONTROL STRATEGY AND ENCODER FOR PROCESSING A VIDEO FRAME OF A SEQUENCE OF VIDEO FRAMES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12352504
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SIGE AND/OR SI:C
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12352718
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
HIGH-YIELD METHOD OF EXPOSING AND CONTACTING THROUGH-SILICON VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12353219
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12353517
|
Filing Dt:
|
01/14/2009
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
ELECTRO-OPTICAL DEVICE
|
|