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|
Patent #:
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|
Issue Dt:
|
01/15/2013
|
Application #:
|
12770792
|
Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES
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Patent #:
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|
Issue Dt:
|
04/01/2014
|
Application #:
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12770948
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Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
THERMAL INTERFACE MATERIAL, TEST STRUCTURE AND METHOD OF USE
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Patent #:
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|
Issue Dt:
|
08/07/2012
|
Application #:
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12770976
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Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
VDD PRE-SET OF DIRECT SENSE DRAM
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12771056
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Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
09/02/2010
| | | | |
Title:
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PLATING APPARATUS AND PLATING METHOD
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|
Patent #:
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|
Issue Dt:
|
09/25/2012
|
Application #:
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12771293
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
NON-VOLATILE MEMORY BASED RELIABILITY AND AVAILABILITY MECHANISMS FOR A COMPUTING DEVICE
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|
Patent #:
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|
Issue Dt:
|
02/26/2013
|
Application #:
|
12771387
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
ON-CHIP NON-VOLATILE STORAGE OF A TEST-TIME PROFILE FOR EFFICIENCY AND PERFORMANCE CONTROL
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|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12771404
|
Filing Dt:
|
04/30/2010
|
Publication #:
|
|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
ENHANCED ANALYSIS OF ARRAY-BASED NETLISTS VIA PHASE ABSTRACTION
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|
|
Patent #:
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|
Issue Dt:
|
07/02/2013
|
Application #:
|
12771479
|
Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
Tracking Array Data Contents Across Three-Valued Read and Write Operations
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|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12771697
|
Filing Dt:
|
04/30/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
High Performance Compliant Wafer Test Probe
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|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12772451
|
Filing Dt:
|
05/03/2010
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES
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|
Patent #:
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|
Issue Dt:
|
05/14/2013
|
Application #:
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12772560
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Filing Dt:
|
05/03/2010
|
Publication #:
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|
Pub Dt:
|
11/03/2011
| | | | |
Title:
|
SESSION LIFE-CYCLE QUALITY-OF-EXPERIENCE ORCHESTRATION FOR VOD FLOWS IN WIRELESS BROADBAND NETWORKS
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
12772774
|
Filing Dt:
|
05/03/2010
|
Publication #:
|
|
Pub Dt:
|
08/19/2010
| | | | |
Title:
|
SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE ADHESIVE
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|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12773306
|
Filing Dt:
|
05/04/2010
|
Publication #:
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|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES HAVING SELF-ALIGNED DIELECTRIC CAPS
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|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12774223
|
Filing Dt:
|
05/20/2010
|
Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
Enhanced Modularity in Heterogeneous 3D Stacks
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|
|
Patent #:
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|
Issue Dt:
|
10/01/2013
|
Application #:
|
12774766
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
Method for Supporting Multiple Libraries Characterized at Different Process, Voltage, and Temperature Points
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|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12775084
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
Title:
|
OPTOELECTRONIC DEVICE WITH GERMANIUM PHOTODETECTOR
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|
|
Patent #:
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|
Issue Dt:
|
11/20/2012
|
Application #:
|
12775107
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ENHANCING INVESTIGATION OF VARIABILITY BY INCLUSION OF SIMILAR OBJECTS WITH KNOWN DIFFERENCES TO THE ORIGINAL ONES
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|
|
Patent #:
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|
Issue Dt:
|
01/15/2013
|
Application #:
|
12775532
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM
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|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
12775607
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MINIMIZING MEMORY ARRAY REPRESENTATIONS FOR ENHANCED SYNTHESIS AND VERIFICATION
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|
|
Patent #:
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|
Issue Dt:
|
12/18/2012
|
Application #:
|
12775622
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ELIMINATING, COALESCING, OR BYPASSING PORTS IN MEMORY ARRAY REPRESENTATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12775939
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
METHOD AND STRUCTURE OF PHOTOVOLTAIC GRID STACKS BY SOLUTION BASED PROCESSES
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|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12775970
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
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|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12776369
|
Filing Dt:
|
05/08/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION
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|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12776444
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MILLIMETER-WAVE SWITCHES AND ATTENUATORS
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|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12776829
|
Filing Dt:
|
05/10/2010
|
Publication #:
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|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
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|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12776861
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12776885
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
METHOD FOR AIR GAP INTERCONNECT INTEGRATION USING PHOTO-PATTERNABLE LOW K MATERIAL
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12777177
|
Filing Dt:
|
05/10/2010
|
Publication #:
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|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
Computer system wafer integrating different dies in stacked master-slave structures
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|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12777715
|
Filing Dt:
|
05/11/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
EFFECTIVE CYCLE TIME MANAGEMENT EMPLOYING A MULTI-HORIZON MODEL
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|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12777881
|
Filing Dt:
|
05/11/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
TFET WITH NANOWIRE SOURCE
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|
|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
12778130
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
CIRCUIT DEVICE WITH SIGNAL LINE TRANSITION ELEMENT
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|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12778315
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12778319
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE
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|
|
Patent #:
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|
Issue Dt:
|
05/06/2014
|
Application #:
|
12778457
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
COMPREHENSIVE ANALYSIS OF QUEUE TIMES IN MICROELECTRONIC MANUFACTURING
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|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12778517
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
GENERATION OF MUTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
08/27/2013
|
Application #:
|
12778526
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
12778897
|
Filing Dt:
|
05/12/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12779079
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHODOLOGY FOR FABRICATING ISOTROPICALLY SOURCE REGIONS OF CMOS TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
04/30/2013
|
Application #:
|
12779087
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS
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|
|
Patent #:
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|
Issue Dt:
|
05/06/2014
|
Application #:
|
12779100
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12779608
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL SHIFTING
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|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12780029
|
Filing Dt:
|
05/14/2010
|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
12780138
|
Filing Dt:
|
05/14/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHOD AND SYSTEM TO PREDICT A NUMBER OF ELECTROMIGRATION CRITICAL ELEMENTS
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|
Patent #:
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|
Issue Dt:
|
02/26/2013
|
Application #:
|
12780193
|
Filing Dt:
|
05/14/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING
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|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12780962
|
Filing Dt:
|
05/17/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
FORMATION OF RAISED SOURCE/DRAIN STRUCTURES IN NFET WITH EMBEDDED SIGE IN PFET
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|
|
Patent #:
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|
Issue Dt:
|
09/09/2014
|
Application #:
|
12781514
|
Filing Dt:
|
05/17/2010
|
Publication #:
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|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
FET Nanopore Sensor
|
|
|
Patent #:
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|
Issue Dt:
|
08/23/2011
|
Application #:
|
12781851
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12782320
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
BODY CONTACT STRUCTURES AND METHODS OF MANUFACTURING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12782337
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
METHODS AND SYSTEMS TO MEET TECHNOLOGY PATTERN DENSITY REQUIREMENTS OF SEMICONDUCTOR FABRICATION PROCESSES
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|
|
Patent #:
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|
Issue Dt:
|
10/30/2012
|
Application #:
|
12782359
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
METHOD AND SYSTEM TO OPTIMIZE SEMICONDUCTOR PRODUCTS FOR POWER, PERFORMANCE, NOISE, AND COST THROUGH USE OF VARIABLE POWER SUPPLY VOLTAGE COMPRESSION
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|
Patent #:
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|
Issue Dt:
|
06/14/2011
|
Application #:
|
12782388
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
PARTIALLY AND FULLY SILICIDED GATE STACKS
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|
|
Patent #:
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|
Issue Dt:
|
01/01/2013
|
Application #:
|
12782407
|
Filing Dt:
|
05/18/2010
|
Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
EQUATION BASED RETARGETING OF DESIGN LAYOUTS
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|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12783676
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
GRAPHENE CHANNEL-BASED DEVICES AND METHODS FOR FABRICATION THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
12783702
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
FOREIGN MATERIAL CONTAMINATION DETECTION
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|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
12783787
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12784150
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
ELECTRICAL DESIGN SPACE EXPLORATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12784583
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
ASYMMETRIC SILICON-ON-INSULATOR (SOI) JUNCTION FIELD EFFECT TRANSISTOR (JFET) AND A METHOD OF FORMING THE ASYMMETRICAL SOI JFET
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|
|
Patent #:
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|
Issue Dt:
|
08/21/2012
|
Application #:
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12784688
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Filing Dt:
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05/21/2010
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Publication #:
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Pub Dt:
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12/09/2010
| | | | |
Title:
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THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SUBSTRATE SPALLING
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Patent #:
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Issue Dt:
|
04/26/2011
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Application #:
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12785007
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Filing Dt:
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05/21/2010
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Publication #:
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Pub Dt:
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11/25/2010
| | | | |
Title:
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ELECTRO-OPTICAL MEMORY CELL
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Patent #:
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Issue Dt:
|
05/17/2011
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Application #:
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12785435
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Filing Dt:
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05/22/2010
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Publication #:
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Pub Dt:
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09/16/2010
| | | | |
Title:
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METHOD TO IMPROVE REQUIREMENTS, DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING INDUSTRIES THROUGH ANALYSIS OF DEFECT DATA
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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12786572
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Filing Dt:
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05/25/2010
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Publication #:
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Pub Dt:
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12/01/2011
| | | | |
Title:
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COMPUTING RESISTANCE SENSITIVITIES WITH RESPECT TO GEOMETRIC PARAMETERS OF CONDUCTORS WITH ARBITRARY SHAPES
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Patent #:
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Issue Dt:
|
04/22/2014
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Application #:
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12786956
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Filing Dt:
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05/25/2010
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Publication #:
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Pub Dt:
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12/01/2011
| | | | |
Title:
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ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF
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Patent #:
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Issue Dt:
|
05/08/2012
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Application #:
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12787167
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Filing Dt:
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05/25/2010
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Publication #:
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Pub Dt:
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09/16/2010
| | | | |
Title:
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POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY
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Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
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12787383
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Filing Dt:
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05/25/2010
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Publication #:
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Pub Dt:
|
12/01/2011
| | | | |
Title:
|
STRAINED FINFET
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|
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Patent #:
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|
Issue Dt:
|
03/20/2012
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Application #:
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12787417
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Filing Dt:
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05/26/2010
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Publication #:
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Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR TONE INVERTING OF RESIDUAL LAYER TOLERANT IMPRINT LITHOGRAPHY
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|
Patent #:
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|
Issue Dt:
|
03/20/2012
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Application #:
|
12787429
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Filing Dt:
|
05/26/2010
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Publication #:
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|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR TONE INVERTING OF RESIDUAL LAYER TOLERANT IMPRINT LITHOGRAPHY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12787919
|
Filing Dt:
|
05/26/2010
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Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
TESTING MEMORY ARRAYS AND LOGIC WITH ABIST CIRCUITRY
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|
|
Patent #:
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|
Issue Dt:
|
05/28/2013
|
Application #:
|
12787988
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Filing Dt:
|
05/26/2010
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Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
SELECTING A DATA RESTORE POINT WITH AN OPTIMAL RECOVERY TIME AND RECOVERY POINT
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|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12788411
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Filing Dt:
|
05/27/2010
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Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE PUMPED ARRAYS
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|
|
Patent #:
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|
Issue Dt:
|
02/08/2011
|
Application #:
|
12788486
|
Filing Dt:
|
05/27/2010
|
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12788521
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
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|
|
Patent #:
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|
Issue Dt:
|
03/05/2013
|
Application #:
|
12788832
|
Filing Dt:
|
05/27/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
HANDLER ATTACHMENT FOR INTEGRATED CIRCUIT FABRICATION
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|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12788839
|
Filing Dt:
|
05/27/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
Laser Ablation of Adhesive for Integrated Circuit Fabrication
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|
|
Patent #:
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|
Issue Dt:
|
04/16/2013
|
Application #:
|
12788843
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
Laser Ablation for Integrated Circuit Fabrication
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|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12788910
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Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
Differential Cross-Coupled Power Combiner or Divider
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|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12788912
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
INTERCONNECT STRUCTURE WITH AN OXYGEN-DOPED SIC ANTIREFLECTIVE COATING AND METHOD OF FABRICATION
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|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12788987
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
SELF-ADJUSTING CRITICAL PATH TIMING OF MULTI-CORE VLSI CHIP
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|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12789013
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR
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|
|
Patent #:
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|
Issue Dt:
|
06/18/2013
|
Application #:
|
12789316
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
THREE DIMENSIONAL STACKED PACKAGE STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12789505
|
Filing Dt:
|
05/28/2010
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12789699
|
Filing Dt:
|
05/28/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR
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|
|
Patent #:
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|
Issue Dt:
|
10/04/2016
|
Application #:
|
12789792
|
Filing Dt:
|
05/28/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
12789839
|
Filing Dt:
|
05/28/2010
|
Publication #:
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|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE
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|
|
Patent #:
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|
Issue Dt:
|
04/02/2013
|
Application #:
|
12791096
|
Filing Dt:
|
06/01/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
SIMULATION SYSTEM, METHOD, AND PROGRAM
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|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
12791372
|
Filing Dt:
|
06/01/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12791942
|
Filing Dt:
|
06/02/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES
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|
Patent #:
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|
Issue Dt:
|
07/23/2013
|
Application #:
|
12792242
|
Filing Dt:
|
06/02/2010
|
Publication #:
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|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK
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|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12792837
|
Filing Dt:
|
06/03/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
NEUTRALIZATION OF TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
12793046
|
Filing Dt:
|
06/03/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
CONTACT RESISTIVITY REDUCTION IN TRANSISTOR DEVICES BY DEEP LEVEL IMPURITY FORMATION
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|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
12793292
|
Filing Dt:
|
06/03/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
FINFET-COMPATIBLE METAL-INSULATOR-METAL CAPACITOR
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|
|
Patent #:
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|
Issue Dt:
|
01/31/2012
|
Application #:
|
12793896
|
Filing Dt:
|
06/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION
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|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12793905
|
Filing Dt:
|
06/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION
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|
|
Patent #:
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|
Issue Dt:
|
02/28/2012
|
Application #:
|
12794208
|
Filing Dt:
|
06/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
METHOD FOR USING COMPOSITIONS CONTAINING FLUOROCARBINOLS IN LITHOGRAPHIC PROCESSES
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|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12794826
|
Filing Dt:
|
06/07/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD OF FORMING MULTI-HIGH-DENSITY MEMORY DEVICES AND ARCHITECTURES
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|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
12794995
|
Filing Dt:
|
06/07/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
LOW VOLTAGE SIGNALING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12795108
|
Filing Dt:
|
06/07/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12795681
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/16/2010
| | | | |
Title:
|
LOCAL METALLIZATION AND USE THEREOF IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12795962
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
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|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12795973
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12796389
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
05/19/2011
| | | | |
Title:
|
BALANCING WORKLOAD IN A MULTIPROCESSOR SYSTEM RESPONSIVE TO PROGRAMMABLE ADJUSTMENTS IN A SYNCRONIZATION INSTRUCTION
|
|