|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
12796411
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
05/19/2011
| | | | |
Title:
|
GENERATION-BASED MEMORY SYNCHRONIZATION IN A MULTIPROCESSOR SYSTEM WITH WEAKLY CONSISTENT MEMORY ACCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12796501
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
DETAILED ROUTABILITY BY CELL PLACEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12796990
|
Filing Dt:
|
06/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
MULTI-PROCESSOR CHIP WITH SHARED FPGA EXECUTION UNIT AND A DESIGN STRUCTURE THEREOF
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12797104
|
Filing Dt:
|
06/09/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
STRAINED-SILICON CMOS DEVICE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12797181
|
Filing Dt:
|
06/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
MEMORY TESTING SYSTEM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12797431
|
Filing Dt:
|
06/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
Scheme to Enable Robust Integration of Band Edge Devices and Alternatives Channels
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12813491
|
Filing Dt:
|
06/10/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12813598
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12813828
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12814142
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
ENCODING DATA INTO CONSTRAINED MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
12814162
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
INTERCONNECT STRUCTURE AND METHOD OF FABRICATING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12814930
|
Filing Dt:
|
06/14/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12814942
|
Filing Dt:
|
06/14/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12815622
|
Filing Dt:
|
06/15/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12815845
|
Filing Dt:
|
06/15/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12815902
|
Filing Dt:
|
06/15/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12816399
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12816605
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
Gate-Last Fabrication of Quarter-Gap MGHK FET
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12816697
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
FIELD EFFECTS TRANSISTOR WITH ASYMMETRIC ABRUPT JUNCTION IMPLANT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
12816825
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12817249
|
Filing Dt:
|
06/17/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12818828
|
Filing Dt:
|
06/18/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
INTERFACE-FREE METAL GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12819440
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12819634
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
METHOD AND STRUCTURE OF FORMING SILICIDE AND DIFFUSION BARRIER LAYER WITH DIRECT DEPOSITED FILM ON SILICON
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12819689
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
STRUCTURE AND METHOD TO REDUCE FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12819697
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
METHOD FOR FORMING AN INDIUM CAP LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12819721
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12819786
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
CONSTRAINT PROGRAMMING FOR REDUCTION OF SYSTEM TEST-CONFIGURATION-MATRIX COMPLEXITY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12820487
|
Filing Dt:
|
06/22/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
FORMING AN ELECTRODE HAVING REDUCED CORROSION AND WATER DECOMPOSITION ON SURFACE USING A CUSTOM OXIDE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12820543
|
Filing Dt:
|
06/22/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
FORMING AN ELECTRODE HAVING REDUCED CORROSION AND WATER DECOMPOSITION ON SURFACE USING AN ORGANIC PROTECTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12820741
|
Filing Dt:
|
06/22/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
Technology Computer-Aided Design (TCAD)-Based Virtual Fabrication
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12820845
|
Filing Dt:
|
06/22/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
DATA CENTER PHYSICAL INFRASTRUCTURE THRESHOLD ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12820870
|
Filing Dt:
|
06/22/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
SELECTIVE ETCH BACK PROCESS FOR CARBON NANOTUBES INTERGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
12820904
|
Filing Dt:
|
06/22/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
METHOD OF PATTERNING PHOTOSENSITIVE MATERIAL ON A SUBSTRATE CONTAINING A LATENT ACID GENERATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12821526
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
PHASE LOCKED LOOP WITH STARTUP OSCILLATOR AND PRIMARY OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12821953
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
METHOD OF PURIFYING NANOPARTICLES IN A COLLOID
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12822021
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12822058
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
INTERNAL BYPASSING OF MEMORY ARRAY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
12822287
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT ARRANGEMENT FOR TEST INPUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
12822426
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICES WITH ASYMMETRIC HALO IMPLANTATION AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12822469
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
RAIM SYSTEM USING DECODING OF VIRTUAL ECC
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
12822492
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
STRUCTURE AND METHOD TO CONTROL BOTTOM CORNER THRESHOLD IN AN SOI DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12822498
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12822503
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
12822507
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
Dual Loop Voltage Regulator with Bias Voltage Capacitor
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
12822508
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12822889
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
HIGH PERFORMANCE CACHE DIRECTORY ERROR CORRECTION CODE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
12822964
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
12822968
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
12823010
|
Filing Dt:
|
06/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
HIERARCHICAL ERROR INJECTION FOR COMPLEX RAIM/ECC DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12823163
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12823168
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
METHOD OF FORMING A SHALLOW TRENCH ISOLATION EMBEDDED POLYSILICON RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12823232
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
12823278
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
PHYSICALLY UNCLONABLE FUNCTION IMPLEMENTED THROUGH THRESHOLD VOLTAGE COMPARISON
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12823728
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12823798
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
FET WITH SELF-ALIGNED BACK GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
12823924
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12823984
|
Filing Dt:
|
06/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
Digital Interface for Fast, Inline, Statistical Characterization of Process, MOS Device and Circuit Variations
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12824293
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Filing Dt:
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06/28/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE
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Patent #:
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Issue Dt:
|
04/01/2014
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Application #:
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12824337
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Filing Dt:
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06/28/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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DYNAMIC MODE NANO-SCALE IMAGING AND POSITION CONTROL USING DEFLECTION SIGNAL DIRECT SAMPLING OF HIGHER MODE-ACTUATED MICROCANTILEVERS
|
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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12825527
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
|
SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR
|
|
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Patent #:
|
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Issue Dt:
|
07/23/2013
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Application #:
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12825791
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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FIELD EFFECT TRANSISTOR DEVICE
|
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Patent #:
|
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Issue Dt:
|
06/05/2012
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Application #:
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12826221
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Filing Dt:
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06/29/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
Title:
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ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET
|
|
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Patent #:
|
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Issue Dt:
|
02/10/2015
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Application #:
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12826958
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Filing Dt:
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06/30/2010
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Publication #:
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Pub Dt:
|
01/05/2012
| | | | |
Title:
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COMPONENT BEHAVIOR MODELING USING SEPARATE BEHAVIOR MODEL
|
|
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Patent #:
|
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Issue Dt:
|
12/25/2012
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Application #:
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12827693
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Filing Dt:
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06/30/2010
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Publication #:
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Pub Dt:
|
01/05/2012
| | | | |
Title:
|
BALL GRID ARRAY WITH IMPROVED SINGLE-ENDED AND DIFFERENTIAL SIGNAL PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
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Application #:
|
12827825
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Filing Dt:
|
06/30/2010
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Publication #:
|
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Pub Dt:
|
01/05/2012
| | | | |
Title:
|
FABRICATING A SEMICONDUCTOR CHIP WITH BACKSIDE OPTICAL VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
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Application #:
|
12828238
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Filing Dt:
|
06/30/2010
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Publication #:
|
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Pub Dt:
|
01/05/2012
| | | | |
Title:
|
VARIABLE GAIN AMPLIFIER WITH REDUCED POWER CONSUMPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
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Application #:
|
12828608
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Filing Dt:
|
07/01/2010
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Publication #:
|
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Pub Dt:
|
10/21/2010
| | | | |
Title:
|
CHEMICAL VAPOR DEPOSITION METHOD FOR THE INCORPORATION OF NITROGEN INTO MATERIALS INCLUDING GERMANIUM AND ANTIMONY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12830275
|
Filing Dt:
|
07/02/2010
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Publication #:
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Pub Dt:
|
10/21/2010
| | | | |
Title:
|
MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12830510
|
Filing Dt:
|
07/06/2010
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Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
Title:
|
METHOD OF MAKING INTEGRATED CIRCUIT CHIP UTILIZING ORIENTED CARBON NANOTUBE CONDUCTIVE LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
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Application #:
|
12830514
|
Filing Dt:
|
07/06/2010
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Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
PROCESS FOR FORMING A SURROUNDING GATE FOR A NANOWIRE USING A SACRIFICIAL PATTERNABLE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12830626
|
Filing Dt:
|
07/06/2010
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Publication #:
|
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Pub Dt:
|
01/12/2012
| | | | |
Title:
|
STRAINED SEMICONDUCTOR-ON-INSULATOR BY ADDITION AND REMOVAL OF ATOMS IN A SEMICONDUCTOR-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12830774
|
Filing Dt:
|
07/06/2010
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Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
Title:
|
ELECTRONIC COMPONENT FOR AN ELECTRONIC CARRIER SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12831303
|
Filing Dt:
|
07/07/2010
|
Publication #:
|
|
Pub Dt:
|
02/10/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR REPARTITIONING A HIERARCHICAL CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12831306
|
Filing Dt:
|
07/07/2010
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Publication #:
|
|
Pub Dt:
|
02/10/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR PLACEMENT OF ELECTRONIC CIRCUIT COMPONENTS IN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12831656
|
Filing Dt:
|
07/07/2010
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
METHOD TO FABRICATE HIGH PERFORMANCE CARBON NANOTUBE TRANSISTOR INTEGRATED CIRCUITS BY THREE-DIMENSIONAL INTEGRATION TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
12832180
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
MULTIPLE THRESHOLD VOLTAGE CELL FAMILIES BASED INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
12832206
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
DESIGN-DEPENDENT INTEGRATED CIRCUIT DISPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12832224
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
SELF-ALIGNED CONTACTS IN CARBON DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
12832375
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
METHOD TO EVALUATE EFFECTIVENESS OF SUBSTRATE CLEANNESS AND QUANTITY OF PIN HOLES IN AN ANTIREFLECTIVE COATING OF A SOLAR CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
12832829
|
Filing Dt:
|
07/08/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
MULTI-GATE TRANSISTOR HAVING SIDEWALL CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
12833272
|
Filing Dt:
|
07/09/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
Implantless Dopant Segregation for Silicide Contacts
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12833446
|
Filing Dt:
|
07/09/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
MAGNETIC SPIN SHIFT REGISTER MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12834110
|
Filing Dt:
|
07/12/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
THERMALLY SENSITIVE MATERIAL EMBEDDED IN THE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12834428
|
Filing Dt:
|
07/12/2010
|
Publication #:
|
|
Pub Dt:
|
01/12/2012
| | | | |
Title:
|
SCHOTTKY FET FABRICATED WITH GATE LAST PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12835764
|
Filing Dt:
|
07/14/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
12835780
|
Filing Dt:
|
07/14/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12835811
|
Filing Dt:
|
07/14/2010
|
Publication #:
|
|
Pub Dt:
|
11/11/2010
| | | | |
Title:
|
HIGH DENSITY DATA STORAGE MEDIUM, METHOD AND DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
12836933
|
Filing Dt:
|
07/15/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
SYNCHRONOUS RECTIFIER GATE DRIVE TIMING TO COMPENSATE FOR TRANSFORMER LEAKAGE INDUCTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12837119
|
Filing Dt:
|
07/15/2010
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
Title:
|
ULTRA-SENSITIVE DETECTION TECHNIQUES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12837121
|
Filing Dt:
|
07/15/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
SEMICONDUCTOR CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12838147
|
Filing Dt:
|
07/16/2010
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
METHOD FOR REDUCING AMINE BASED CONTAMINANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
12838515
|
Filing Dt:
|
07/19/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
METHOD OF FABRICATING ISOLATED CAPACITORS AND STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
12838597
|
Filing Dt:
|
07/19/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
TECHNIQUES FOR FORMING NARROW COPPER FILLED VIAS HAVING IMPROVED CONDUCTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12838844
|
Filing Dt:
|
07/19/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
FORMATION METHOD AND STRUCTURE FOR A WELL-CONTROLLED METALLIC SOURCE/DRAIN SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12838850
|
Filing Dt:
|
07/19/2010
|
Publication #:
|
|
Pub Dt:
|
01/19/2012
| | | | |
Title:
|
FUSE STRUCTURE HAVING CRACK STOP VOID, METHOD FOR FORMING AND PROGRAMMING SAME, AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12839451
|
Filing Dt:
|
07/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/11/2010
| | | | |
Title:
|
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12839528
|
Filing Dt:
|
07/20/2010
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE (ESD) PROTECTION FOR ELECTRONIC DEVICES USING WIRE-BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12839697
|
Filing Dt:
|
07/20/2010
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
METHODS TO FORM SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12839777
|
Filing Dt:
|
07/20/2010
|
Publication #:
|
|
Pub Dt:
|
01/26/2012
| | | | |
Title:
|
MILLIMETER-WAVE ON-CHIP SWITCH EMPLOYING FREQUENCY-DEPENDENT INDUCTANCE FOR CANCELLATION OF OFF-STATE CAPACITANCE
|
|