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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036550/0001   Pages: 983
Recorded: 09/03/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
02/25/2014
Application #:
12905158
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
04/19/2012
Title:
Method and Structure for pFET Junction Profile With SiGe Channel
2
Patent #:
Issue Dt:
01/15/2013
Application #:
12905575
Filing Dt:
10/15/2010
Publication #:
Pub Dt:
04/19/2012
Title:
INTEGRATED PLANAR AND MULTIPLE GATE FETS
3
Patent #:
Issue Dt:
03/26/2013
Application #:
12906580
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
02/10/2011
Title:
INTERCONNECT STRUCTURE AND METHOD FOR CU/ULTRA LOW K INTEGRATION
4
Patent #:
Issue Dt:
08/14/2012
Application #:
12906690
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
02/10/2011
Title:
NEGATIVE THERMAL EXPANSION SYSTEM (NTES) DEVICE FOR TCE COMPENSATION IN ELASTOMER COMPOSITES AND CONDUCTIVE ELASTOMER INTERCONNECTS IN MICROELECTRONIC PACKAGING
5
Patent #:
Issue Dt:
07/01/2014
Application #:
12906697
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
04/19/2012
Title:
EMBEDDED VERTICAL OPTICAL GRATING FOR HETEROGENEOUS INTEGRATION
6
Patent #:
Issue Dt:
01/28/2014
Application #:
12906707
Filing Dt:
10/18/2010
Publication #:
Pub Dt:
04/19/2012
Title:
METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE
7
Patent #:
Issue Dt:
01/08/2013
Application #:
12907105
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
04/19/2012
Title:
LOW TRIGGER VOLTAGE ELECTROSTATIC DISCHARGE NFET IN TRIPLE WELL CMOS TECHNOLOGY
8
Patent #:
Issue Dt:
12/02/2014
Application #:
12907186
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
02/10/2011
Title:
SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE
9
Patent #:
Issue Dt:
01/28/2014
Application #:
12907904
Filing Dt:
10/19/2010
Publication #:
Pub Dt:
04/19/2012
Title:
PREVENTION AND REMEDIATION OF DAMAGE TO OPTICAL SURFACES
10
Patent #:
Issue Dt:
12/27/2011
Application #:
12908016
Filing Dt:
10/20/2010
Title:
REPLACEMENT METAL GATE METHOD
11
Patent #:
Issue Dt:
02/04/2014
Application #:
12908024
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
04/26/2012
Title:
STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR
12
Patent #:
Issue Dt:
06/11/2013
Application #:
12908306
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
04/26/2012
Title:
LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS
13
Patent #:
Issue Dt:
03/25/2014
Application #:
12908554
Filing Dt:
10/20/2010
Publication #:
Pub Dt:
02/10/2011
Title:
STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
14
Patent #:
Issue Dt:
07/03/2012
Application #:
12909325
Filing Dt:
10/21/2010
Publication #:
Pub Dt:
04/26/2012
Title:
SEMICONDUCTOR STRUCTURE AND METHODS OF MANUFACTURE
15
Patent #:
Issue Dt:
09/03/2013
Application #:
12909917
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
SIMULTANEOUS FORMATION OF FINFET AND MUGFET
16
Patent #:
Issue Dt:
09/03/2013
Application #:
12909919
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
FORMATION OF MULTI-HEIGHT MUGFET
17
Patent #:
Issue Dt:
02/17/2015
Application #:
12910075
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES
18
Patent #:
Issue Dt:
06/04/2013
Application #:
12910127
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
IMPLEMENTING ENHANCED RLM CONNECTIVITY ON A HIERARCHICAL DESIGN WITH TOP LEVEL PIPELINE REGISTERS
19
Patent #:
Issue Dt:
10/09/2012
Application #:
12910144
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
REDUCING ENERGY CONSUMPTION AND OPTIMIZING WORKLOAD AND PERFORMANCE IN MULTI-TIER STORAGE SYSTEMS USING EXTENT-LEVEL DYNAMIC TIERING
20
Patent #:
Issue Dt:
05/21/2013
Application #:
12910214
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
04/26/2012
Title:
IMPLEMENTING NET ROUTING WITH ENHANCED CORRELATION OF PRE-BUFFERED AND POST-BUFFERED ROUTES
21
Patent #:
Issue Dt:
12/04/2012
Application #:
12910236
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
02/17/2011
Title:
MAGNETIC MATERIALS HAVING SUPERPARAMAGNETIC PARTICLES
22
Patent #:
Issue Dt:
07/23/2013
Application #:
12910336
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
05/12/2011
Title:
PROVIDING SECONDARY POWER PINS IN INTEGRATED CIRCUIT DESIGN
23
Patent #:
Issue Dt:
11/25/2014
Application #:
12911327
Filing Dt:
10/25/2010
Publication #:
Pub Dt:
04/26/2012
Title:
ON-CHIP TUNABLE TRANSMISSION LINES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
24
Patent #:
Issue Dt:
05/22/2012
Application #:
12911379
Filing Dt:
10/25/2010
Publication #:
Pub Dt:
02/10/2011
Title:
PROGRAMMABLE SEMICONDUCTOR DEVICE
25
Patent #:
Issue Dt:
05/14/2013
Application #:
12911833
Filing Dt:
10/26/2010
Publication #:
Pub Dt:
04/26/2012
Title:
FABRICATING KESTERITE SOLAR CELLS AND PARTS THEREOF
26
Patent #:
Issue Dt:
01/15/2013
Application #:
12912819
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION
27
Patent #:
Issue Dt:
03/25/2014
Application #:
12912883
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions
28
Patent #:
Issue Dt:
04/01/2014
Application #:
12912897
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SEMICONDUCTOR DEVICE HAVING LOCALIZED EXTREMELY THIN SILICON ON INSULATOR CHANNEL REGION
29
Patent #:
Issue Dt:
06/04/2013
Application #:
12912919
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS
30
Patent #:
Issue Dt:
10/30/2012
Application #:
12912940
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
31
Patent #:
Issue Dt:
11/26/2013
Application #:
12912963
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
32
Patent #:
NONE
Issue Dt:
Application #:
12913064
Filing Dt:
10/27/2010
Publication #:
Pub Dt:
05/03/2012
Title:
Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines
33
Patent #:
Issue Dt:
07/01/2014
Application #:
12914095
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS
34
Patent #:
Issue Dt:
03/05/2013
Application #:
12914132
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SEALED AIR GAP FOR SEMICONDUCTOR CHIP
35
Patent #:
Issue Dt:
04/23/2013
Application #:
12914154
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
Pattern Recognition with Edge Correction for Design Based Metrology
36
Patent #:
Issue Dt:
02/19/2013
Application #:
12914212
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES
37
Patent #:
Issue Dt:
02/04/2014
Application #:
12914367
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
02/17/2011
Title:
METHOD FOR QUANTIFYING THE MANUFACTURING COMPLEXITY OF ELECTRICAL DESIGNS
38
Patent #:
Issue Dt:
01/15/2013
Application #:
12914573
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES
39
Patent #:
Issue Dt:
08/28/2012
Application #:
12914644
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
OPTIMIZED SEMICONDUCTOR PACKAGING IN A THREE-DIMENSIONAL STACK
40
Patent #:
Issue Dt:
03/26/2013
Application #:
12914697
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
HEAT SINK INTEGRATED POWER DELIVERY AND DISTRIBUTION FOR INTEGRATED CIRCUITS
41
Patent #:
Issue Dt:
04/23/2013
Application #:
12914730
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/03/2012
Title:
Thermal Power Plane for Integrated Circuits
42
Patent #:
Issue Dt:
01/14/2014
Application #:
12915003
Filing Dt:
10/28/2010
Publication #:
Pub Dt:
05/05/2011
Title:
PROVIDING NONDETERMINISTIC DATA
43
Patent #:
Issue Dt:
07/31/2012
Application #:
12915463
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS
44
Patent #:
Issue Dt:
12/16/2014
Application #:
12915510
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY
45
Patent #:
Issue Dt:
12/31/2013
Application #:
12915888
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
ANTI-BLOOMING PIXEL SENSOR CELL WITH ACTIVE NEUTRAL DENSITY FILTER, METHODS OF MANUFACTURE, AND DESIGN STRUCTURE
46
Patent #:
Issue Dt:
01/01/2013
Application #:
12915923
Filing Dt:
10/29/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SPLIT-LAYER DESIGN FOR DOUBLE PATTERNING LITHOGRAPHY
47
Patent #:
Issue Dt:
07/31/2012
Application #:
12916864
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
05/03/2012
Title:
LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE
48
Patent #:
Issue Dt:
07/31/2012
Application #:
12917029
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
05/03/2012
Title:
STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME
49
Patent #:
Issue Dt:
11/08/2011
Application #:
12917154
Filing Dt:
11/01/2010
Publication #:
Pub Dt:
02/24/2011
Title:
SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER
50
Patent #:
Issue Dt:
01/31/2012
Application #:
12917800
Filing Dt:
11/02/2010
Title:
PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE
51
Patent #:
Issue Dt:
11/26/2013
Application #:
12938411
Filing Dt:
11/03/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SELF-UPDATING NODE CONTROLLER FOR AN ENDPOINT IN A CLOUD COMPUTING ENVIRONMENT
52
Patent #:
NONE
Issue Dt:
Application #:
12938440
Filing Dt:
11/03/2010
Publication #:
Pub Dt:
05/03/2012
Title:
SILICON-ON-INSULATOR (SOI) BODY-CONTACT PASS GATE STRUCTURE
53
Patent #:
Issue Dt:
04/23/2013
Application #:
12938457
Filing Dt:
11/03/2010
Publication #:
Pub Dt:
05/03/2012
Title:
METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
54
Patent #:
Issue Dt:
12/18/2012
Application #:
12938459
Filing Dt:
11/03/2010
Publication #:
Pub Dt:
02/24/2011
Title:
FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
55
Patent #:
Issue Dt:
10/30/2012
Application #:
12938477
Filing Dt:
11/03/2010
Publication #:
Pub Dt:
05/03/2012
Title:
IMPLEMENTING PHYSICALLY UNCLONABLE FUNCTION (PUF) UTILIZING EDRAM MEMORY CELL CAPACITANCE VARIATION
56
Patent #:
Issue Dt:
06/25/2013
Application #:
12939119
Filing Dt:
11/03/2010
Publication #:
Pub Dt:
01/26/2012
Title:
BATCHING TRANSACTIONS TO APPLY TO A DATABASE
57
Patent #:
Issue Dt:
01/28/2014
Application #:
12939462
Filing Dt:
11/04/2010
Publication #:
Pub Dt:
05/10/2012
Title:
ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE
58
Patent #:
Issue Dt:
02/04/2014
Application #:
12939506
Filing Dt:
11/04/2010
Publication #:
Pub Dt:
05/10/2012
Title:
DEVICES HAVING REDUCED SUSCEPTIBILITY TO SOFT-ERROR EFFECTS AND METHOD FOR FABRICATION
59
Patent #:
Issue Dt:
01/03/2012
Application #:
12939520
Filing Dt:
11/04/2010
Publication #:
Pub Dt:
02/24/2011
Title:
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
60
Patent #:
Issue Dt:
08/07/2012
Application #:
12939538
Filing Dt:
11/04/2010
Publication #:
Pub Dt:
02/24/2011
Title:
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
61
Patent #:
Issue Dt:
07/31/2012
Application #:
12939668
Filing Dt:
11/04/2010
Publication #:
Pub Dt:
05/10/2012
Title:
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
62
Patent #:
Issue Dt:
05/21/2013
Application #:
12940115
Filing Dt:
11/05/2010
Publication #:
Pub Dt:
05/10/2012
Title:
STRAINED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING STRAINED SEMICONDUCTOR DEVICES
63
Patent #:
Issue Dt:
07/23/2013
Application #:
12940210
Filing Dt:
11/05/2010
Publication #:
Pub Dt:
05/10/2012
Title:
GATE-TO-GATE RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
64
Patent #:
Issue Dt:
12/11/2012
Application #:
12940762
Filing Dt:
11/05/2010
Publication #:
Pub Dt:
05/10/2012
Title:
REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT
65
Patent #:
Issue Dt:
10/29/2013
Application #:
12941016
Filing Dt:
11/05/2010
Publication #:
Pub Dt:
05/10/2012
Title:
SMART OPTIMIZATION OF TRACKS FOR CLOUD COMPUTING
66
Patent #:
Issue Dt:
12/04/2012
Application #:
12941042
Filing Dt:
11/06/2010
Publication #:
Pub Dt:
05/10/2012
Title:
CONTACTS FOR FET DEVICES
67
Patent #:
Issue Dt:
02/21/2012
Application #:
12941184
Filing Dt:
11/08/2010
Title:
METHOD OF FABRICATING DAMASCENE STRUCTURES
68
Patent #:
Issue Dt:
03/12/2013
Application #:
12941375
Filing Dt:
11/08/2010
Publication #:
Pub Dt:
05/10/2012
Title:
NOVEL INTEGRATION PROCESS TO IMPROVE FOCUS LEVELING WITHIN A LOT PROCESS VARIATION
69
Patent #:
Issue Dt:
12/31/2013
Application #:
12941771
Filing Dt:
11/08/2010
Publication #:
Pub Dt:
05/10/2012
Title:
METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE
70
Patent #:
Issue Dt:
06/13/2017
Application #:
12942011
Filing Dt:
11/08/2010
Publication #:
Pub Dt:
05/10/2012
Title:
OPTIMIZING STORAGE CLOUD ENVIRONMENTS THROUGH ADAPTIVE STATISTICAL MODELING
71
Patent #:
Issue Dt:
04/16/2013
Application #:
12942097
Filing Dt:
11/09/2010
Publication #:
Pub Dt:
05/10/2012
Title:
STRUCTURE AND METHOD FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS
72
Patent #:
Issue Dt:
01/29/2013
Application #:
12942289
Filing Dt:
11/09/2010
Publication #:
Pub Dt:
05/10/2012
Title:
STRESSED TRANSISTOR WITH IMPROVED METASTABILITY
73
Patent #:
Issue Dt:
09/24/2013
Application #:
12942490
Filing Dt:
11/09/2010
Publication #:
Pub Dt:
05/10/2012
Title:
FORMATION OF A GRAPHENE LAYER ON A LARGE SUBSTRATE
74
Patent #:
Issue Dt:
09/24/2013
Application #:
12942662
Filing Dt:
11/09/2010
Publication #:
Pub Dt:
05/10/2012
Title:
THREE-DIMENSIONAL (3D) STACKED INTEGRATED CIRCUIT TESTING
75
Patent #:
Issue Dt:
06/03/2014
Application #:
12943084
Filing Dt:
11/10/2010
Publication #:
Pub Dt:
05/10/2012
Title:
BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION
76
Patent #:
Issue Dt:
02/14/2012
Application #:
12943146
Filing Dt:
11/10/2010
Publication #:
Pub Dt:
03/10/2011
Title:
METHOD FOR CREATING 3-D SINGLE GATE INVERTER
77
Patent #:
Issue Dt:
02/18/2014
Application #:
12943973
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS
78
Patent #:
Issue Dt:
01/21/2014
Application #:
12943987
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
CREATING ANISOTROPICALLY DIFFUSED JUNCTIONS IN FIELD EFFECT TRANSISTOR DEVICES
79
Patent #:
Issue Dt:
01/28/2014
Application #:
12943995
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
80
Patent #:
NONE
Issue Dt:
Application #:
12944018
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE
81
Patent #:
Issue Dt:
08/20/2013
Application #:
12944020
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE
82
Patent #:
Issue Dt:
04/01/2014
Application #:
12944059
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
SYSTEM AND METHOD FOR PERFORMING STATIC TIMING ANALYSIS IN THE PRESENCE OF CORRELATIONS BETWEEN ASSERTED ARRIVAL TIMES
83
Patent #:
Issue Dt:
04/02/2013
Application #:
12944174
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT
84
Patent #:
Issue Dt:
10/22/2013
Application #:
12944392
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
VOLTAGE REGULATOR MODULE WITH POWER GATING AND BYPASS
85
Patent #:
Issue Dt:
08/07/2012
Application #:
12944480
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
METHOD AND SYSTEM FOR OPTIMIZING A DEVICE WITH CURRENT SOURCE MODELS
86
Patent #:
Issue Dt:
08/21/2012
Application #:
12944493
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
SLACK-BASED TIMING BUDGET APPORTIONMENT
87
Patent #:
Issue Dt:
09/03/2013
Application #:
12944682
Filing Dt:
11/11/2010
Publication #:
Pub Dt:
05/17/2012
Title:
METHOD AND APPARATUS FOR OPTIMAL CACHE SIZING AND CONFIGURATION FOR LARGE MEMORY SYSTEMS
88
Patent #:
Issue Dt:
06/11/2013
Application #:
12944892
Filing Dt:
11/12/2010
Publication #:
Pub Dt:
05/17/2012
Title:
PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES
89
Patent #:
NONE
Issue Dt:
Application #:
12946232
Filing Dt:
11/15/2010
Publication #:
Pub Dt:
05/17/2012
Title:
PHOTORESIST COMPOSITION FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
90
Patent #:
Issue Dt:
03/19/2013
Application #:
12946325
Filing Dt:
11/15/2010
Publication #:
Pub Dt:
06/23/2011
Title:
VERIFYING A REGISTER-TRANSFER LEVEL DESIGN OF AN EXECUTION UNIT
91
Patent #:
Issue Dt:
12/17/2013
Application #:
12946875
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
05/17/2012
Title:
POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES
92
Patent #:
Issue Dt:
03/12/2013
Application #:
12946915
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
05/17/2012
Title:
HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
93
Patent #:
Issue Dt:
10/08/2013
Application #:
12946925
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
05/17/2012
Title:
FREE COOLING SOLUTION FOR A CONTAINERIZED DATA CENTER
94
Patent #:
Issue Dt:
10/15/2013
Application #:
12946950
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
05/17/2012
Title:
OPTIMAL CHIP ACCEPTANCE CRITERION AND ITS APPLICATIONS
95
Patent #:
Issue Dt:
03/04/2014
Application #:
12947445
Filing Dt:
11/16/2010
Publication #:
Pub Dt:
05/17/2012
Title:
Clock Optimization with Local Clock Buffer Control Optimization
96
Patent #:
Issue Dt:
10/01/2013
Application #:
12948031
Filing Dt:
11/17/2010
Publication #:
Pub Dt:
05/17/2012
Title:
Replacement Gate Having Work Function at Valence Band Edge
97
Patent #:
Issue Dt:
03/20/2012
Application #:
12948079
Filing Dt:
11/17/2010
Title:
CHIP PACKAGE SOLDER INTERCONNECT FORMED BY SURFACE TENSION
98
Patent #:
Issue Dt:
07/24/2012
Application #:
12948092
Filing Dt:
11/17/2010
Publication #:
Pub Dt:
05/17/2012
Title:
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
99
Patent #:
Issue Dt:
10/23/2012
Application #:
12948165
Filing Dt:
11/17/2010
Publication #:
Pub Dt:
05/17/2012
Title:
IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION
100
Patent #:
Issue Dt:
12/27/2011
Application #:
12948246
Filing Dt:
11/17/2010
Title:
METHOD OF FORMING REPLACEMENT METAL GATE WITH BORDERLESS CONTACT AND STRUCTURE THEREOF
Assignor
1
Exec Dt:
06/29/2015
Assignee
1
2070 ROUTE 52
HOPEWELL JUNCTION, NEW YORK 12533
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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