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02/25/2014
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12905158
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10/15/2010
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04/19/2012
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01/15/2013
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12905575
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10/15/2010
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04/19/2012
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INTEGRATED PLANAR AND MULTIPLE GATE FETS
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03/26/2013
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12906580
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10/18/2010
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02/10/2011
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08/14/2012
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12906690
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10/18/2010
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02/10/2011
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NEGATIVE THERMAL EXPANSION SYSTEM (NTES) DEVICE FOR TCE COMPENSATION IN ELASTOMER COMPOSITES AND CONDUCTIVE ELASTOMER INTERCONNECTS IN MICROELECTRONIC PACKAGING
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07/01/2014
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10/18/2010
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04/19/2012
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01/28/2014
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10/18/2010
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04/19/2012
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METHODOLOGY ON DEVELOPING METAL FILL AS LIBRARY DEVICE AND DESIGN STRUCTURE
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01/08/2013
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10/19/2010
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04/19/2012
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LOW TRIGGER VOLTAGE ELECTROSTATIC DISCHARGE NFET IN TRIPLE WELL CMOS TECHNOLOGY
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12/02/2014
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10/19/2010
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02/10/2011
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SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE
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01/28/2014
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12907904
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10/19/2010
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04/19/2012
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12/27/2011
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12908016
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10/20/2010
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REPLACEMENT METAL GATE METHOD
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02/04/2014
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12908024
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10/20/2010
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04/26/2012
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STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR
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06/11/2013
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12908306
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10/20/2010
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04/26/2012
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LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS
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03/25/2014
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12908554
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10/20/2010
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02/10/2011
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STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
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07/03/2012
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12909325
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10/21/2010
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04/26/2012
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SEMICONDUCTOR STRUCTURE AND METHODS OF MANUFACTURE
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09/03/2013
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12909917
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10/22/2010
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04/26/2012
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SIMULTANEOUS FORMATION OF FINFET AND MUGFET
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09/03/2013
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12909919
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10/22/2010
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04/26/2012
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FORMATION OF MULTI-HEIGHT MUGFET
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02/17/2015
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12910075
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10/22/2010
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04/26/2012
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STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES
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06/04/2013
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12910127
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10/22/2010
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04/26/2012
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Title:
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IMPLEMENTING ENHANCED RLM CONNECTIVITY ON A HIERARCHICAL DESIGN WITH TOP LEVEL PIPELINE REGISTERS
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10/09/2012
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12910144
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10/22/2010
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04/26/2012
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Title:
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REDUCING ENERGY CONSUMPTION AND OPTIMIZING WORKLOAD AND PERFORMANCE IN MULTI-TIER STORAGE SYSTEMS USING EXTENT-LEVEL DYNAMIC TIERING
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05/21/2013
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12910214
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10/22/2010
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04/26/2012
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Title:
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IMPLEMENTING NET ROUTING WITH ENHANCED CORRELATION OF PRE-BUFFERED AND POST-BUFFERED ROUTES
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12/04/2012
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12910236
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10/22/2010
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02/17/2011
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Title:
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MAGNETIC MATERIALS HAVING SUPERPARAMAGNETIC PARTICLES
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07/23/2013
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12910336
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10/22/2010
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05/12/2011
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Title:
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PROVIDING SECONDARY POWER PINS IN INTEGRATED CIRCUIT DESIGN
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11/25/2014
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12911327
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10/25/2010
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Pub Dt:
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04/26/2012
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ON-CHIP TUNABLE TRANSMISSION LINES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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05/22/2012
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12911379
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10/25/2010
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02/10/2011
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Title:
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PROGRAMMABLE SEMICONDUCTOR DEVICE
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05/14/2013
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12911833
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10/26/2010
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04/26/2012
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Title:
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FABRICATING KESTERITE SOLAR CELLS AND PARTS THEREOF
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01/15/2013
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12912819
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10/27/2010
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05/03/2012
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Title:
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STATISTICAL METHOD FOR HIERARCHICALLY ROUTING LAYOUT UTILIZING FLAT ROUTE INFORMATION
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03/25/2014
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12912883
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10/27/2010
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05/03/2012
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Title:
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Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions
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04/01/2014
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12912897
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10/27/2010
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05/03/2012
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Title:
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SEMICONDUCTOR DEVICE HAVING LOCALIZED EXTREMELY THIN SILICON ON INSULATOR CHANNEL REGION
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06/04/2013
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12912919
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10/27/2010
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05/03/2012
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Title:
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LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS
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10/30/2012
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12912940
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10/27/2010
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05/03/2012
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GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
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11/26/2013
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12912963
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10/27/2010
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05/03/2012
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REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
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NONE
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12913064
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10/27/2010
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05/03/2012
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Title:
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Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines
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07/01/2014
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12914095
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10/28/2010
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05/03/2012
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SHALLOW TRENCH ISOLATION RECESS REPAIR USING SPACER FORMATION PROCESS
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03/05/2013
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12914132
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10/28/2010
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05/03/2012
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SEALED AIR GAP FOR SEMICONDUCTOR CHIP
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04/23/2013
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12914154
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10/28/2010
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05/03/2012
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Pattern Recognition with Edge Correction for Design Based Metrology
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02/19/2013
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12914212
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10/28/2010
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05/03/2012
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METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES
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02/04/2014
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12914367
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10/28/2010
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02/17/2011
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METHOD FOR QUANTIFYING THE MANUFACTURING COMPLEXITY OF ELECTRICAL DESIGNS
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01/15/2013
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12914573
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10/28/2010
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05/03/2012
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IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES
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08/28/2012
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12914644
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10/28/2010
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05/03/2012
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Title:
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OPTIMIZED SEMICONDUCTOR PACKAGING IN A THREE-DIMENSIONAL STACK
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03/26/2013
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12914697
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10/28/2010
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05/03/2012
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HEAT SINK INTEGRATED POWER DELIVERY AND DISTRIBUTION FOR INTEGRATED CIRCUITS
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04/23/2013
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12914730
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10/28/2010
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05/03/2012
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Thermal Power Plane for Integrated Circuits
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01/14/2014
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12915003
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10/28/2010
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Pub Dt:
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05/05/2011
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PROVIDING NONDETERMINISTIC DATA
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07/31/2012
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12915463
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10/29/2010
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Pub Dt:
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05/03/2012
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Title:
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DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS
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12/16/2014
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12915510
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10/29/2010
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05/03/2012
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INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY
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12/31/2013
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12915888
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10/29/2010
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Pub Dt:
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05/03/2012
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Title:
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ANTI-BLOOMING PIXEL SENSOR CELL WITH ACTIVE NEUTRAL DENSITY FILTER, METHODS OF MANUFACTURE, AND DESIGN STRUCTURE
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01/01/2013
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12915923
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10/29/2010
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Pub Dt:
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05/03/2012
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Title:
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SPLIT-LAYER DESIGN FOR DOUBLE PATTERNING LITHOGRAPHY
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07/31/2012
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12916864
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11/01/2010
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Pub Dt:
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05/03/2012
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LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE
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07/31/2012
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12917029
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11/01/2010
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Pub Dt:
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05/03/2012
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Title:
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STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME
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11/08/2011
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12917154
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11/01/2010
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Pub Dt:
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02/24/2011
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SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER
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01/31/2012
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12917800
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11/02/2010
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Title:
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PROCESS FOR SELECTIVELY PATTERNING A MAGNETIC FILM STRUCTURE
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11/26/2013
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12938411
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11/03/2010
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Pub Dt:
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05/03/2012
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Title:
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SELF-UPDATING NODE CONTROLLER FOR AN ENDPOINT IN A CLOUD COMPUTING ENVIRONMENT
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NONE
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12938440
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Filing Dt:
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11/03/2010
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Pub Dt:
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05/03/2012
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Title:
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SILICON-ON-INSULATOR (SOI) BODY-CONTACT PASS GATE STRUCTURE
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04/23/2013
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12938457
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11/03/2010
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Pub Dt:
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05/03/2012
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Title:
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METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
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Issue Dt:
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12/18/2012
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12938459
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11/03/2010
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Pub Dt:
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02/24/2011
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Title:
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FUNCTIONALIZED CARBOSILANE POLYMERS AND PHOTORESIST COMPOSITIONS CONTAINING THE SAME
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10/30/2012
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12938477
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11/03/2010
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Pub Dt:
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05/03/2012
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Title:
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IMPLEMENTING PHYSICALLY UNCLONABLE FUNCTION (PUF) UTILIZING EDRAM MEMORY CELL CAPACITANCE VARIATION
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06/25/2013
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12939119
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11/03/2010
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Pub Dt:
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01/26/2012
| | | | |
Title:
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BATCHING TRANSACTIONS TO APPLY TO A DATABASE
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Issue Dt:
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01/28/2014
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12939462
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11/04/2010
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Pub Dt:
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05/10/2012
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Title:
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ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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12939506
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Filing Dt:
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11/04/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
|
DEVICES HAVING REDUCED SUSCEPTIBILITY TO SOFT-ERROR EFFECTS AND METHOD FOR FABRICATION
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|
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Patent #:
|
|
Issue Dt:
|
01/03/2012
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Application #:
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12939520
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Filing Dt:
|
11/04/2010
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Publication #:
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Pub Dt:
|
02/24/2011
| | | | |
Title:
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FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
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Patent #:
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|
Issue Dt:
|
08/07/2012
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Application #:
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12939538
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Filing Dt:
|
11/04/2010
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Publication #:
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Pub Dt:
|
02/24/2011
| | | | |
Title:
|
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
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Patent #:
|
|
Issue Dt:
|
07/31/2012
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Application #:
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12939668
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Filing Dt:
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11/04/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
|
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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Patent #:
|
|
Issue Dt:
|
05/21/2013
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Application #:
|
12940115
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Filing Dt:
|
11/05/2010
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Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
|
STRAINED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING STRAINED SEMICONDUCTOR DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
07/23/2013
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Application #:
|
12940210
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Filing Dt:
|
11/05/2010
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Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
|
GATE-TO-GATE RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
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|
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Patent #:
|
|
Issue Dt:
|
12/11/2012
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Application #:
|
12940762
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Filing Dt:
|
11/05/2010
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Publication #:
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Pub Dt:
|
05/10/2012
| | | | |
Title:
|
REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT
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|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
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Application #:
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12941016
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Filing Dt:
|
11/05/2010
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Publication #:
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|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
SMART OPTIMIZATION OF TRACKS FOR CLOUD COMPUTING
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|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12941042
|
Filing Dt:
|
11/06/2010
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Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
CONTACTS FOR FET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12941184
|
Filing Dt:
|
11/08/2010
|
Title:
|
METHOD OF FABRICATING DAMASCENE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12941375
|
Filing Dt:
|
11/08/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
NOVEL INTEGRATION PROCESS TO IMPROVE FOCUS LEVELING WITHIN A LOT PROCESS VARIATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
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Application #:
|
12941771
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Filing Dt:
|
11/08/2010
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Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2017
|
Application #:
|
12942011
|
Filing Dt:
|
11/08/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
OPTIMIZING STORAGE CLOUD ENVIRONMENTS THROUGH ADAPTIVE STATISTICAL MODELING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12942097
|
Filing Dt:
|
11/09/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12942289
|
Filing Dt:
|
11/09/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
STRESSED TRANSISTOR WITH IMPROVED METASTABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
12942490
|
Filing Dt:
|
11/09/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
FORMATION OF A GRAPHENE LAYER ON A LARGE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
12942662
|
Filing Dt:
|
11/09/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
THREE-DIMENSIONAL (3D) STACKED INTEGRATED CIRCUIT TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
12943084
|
Filing Dt:
|
11/10/2010
|
Publication #:
|
|
Pub Dt:
|
05/10/2012
| | | | |
Title:
|
BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12943146
|
Filing Dt:
|
11/10/2010
|
Publication #:
|
|
Pub Dt:
|
03/10/2011
| | | | |
Title:
|
METHOD FOR CREATING 3-D SINGLE GATE INVERTER
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
12943973
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12943987
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
CREATING ANISOTROPICALLY DIFFUSED JUNCTIONS IN FIELD EFFECT TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/2014
|
Application #:
|
12943995
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12944018
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12944020
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
IMPLEMENTING VERTICAL DIE STACKING TO DISTRIBUTE LOGICAL FUNCTION OVER MULTIPLE DIES IN THROUGH-SILICON-VIA STACKED SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12944059
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
SYSTEM AND METHOD FOR PERFORMING STATIC TIMING ANALYSIS IN THE PRESENCE OF CORRELATIONS BETWEEN ASSERTED ARRIVAL TIMES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12944174
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12944392
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
VOLTAGE REGULATOR MODULE WITH POWER GATING AND BYPASS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12944480
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
METHOD AND SYSTEM FOR OPTIMIZING A DEVICE WITH CURRENT SOURCE MODELS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
12944493
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
SLACK-BASED TIMING BUDGET APPORTIONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
12944682
|
Filing Dt:
|
11/11/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR OPTIMAL CACHE SIZING AND CONFIGURATION FOR LARGE MEMORY SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
12944892
|
Filing Dt:
|
11/12/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12946232
|
Filing Dt:
|
11/15/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
PHOTORESIST COMPOSITION FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12946325
|
Filing Dt:
|
11/15/2010
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
VERIFYING A REGISTER-TRANSFER LEVEL DESIGN OF AN EXECUTION UNIT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
12946875
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12946915
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12946925
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
FREE COOLING SOLUTION FOR A CONTAINERIZED DATA CENTER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12946950
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
OPTIMAL CHIP ACCEPTANCE CRITERION AND ITS APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
12947445
|
Filing Dt:
|
11/16/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
Clock Optimization with Local Clock Buffer Control Optimization
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12948031
|
Filing Dt:
|
11/17/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
Replacement Gate Having Work Function at Valence Band Edge
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12948079
|
Filing Dt:
|
11/17/2010
|
Title:
|
CHIP PACKAGE SOLDER INTERCONNECT FORMED BY SURFACE TENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12948092
|
Filing Dt:
|
11/17/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12948165
|
Filing Dt:
|
11/17/2010
|
Publication #:
|
|
Pub Dt:
|
05/17/2012
| | | | |
Title:
|
IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12948246
|
Filing Dt:
|
11/17/2010
|
Title:
|
METHOD OF FORMING REPLACEMENT METAL GATE WITH BORDERLESS CONTACT AND STRUCTURE THEREOF
|
|