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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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09742131
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Filing Dt:
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12/20/2000
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT, IN PARTICULAR A SEMICONDUCTOR MEMORY CIRCUIT, HAVING AT LEAST ONE INTEGRATED ELECTRICAL ANTIFUSE STRUCTURE, AND A METHOD OF PRODUCING THE STRUCTURE
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09912039
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Filing Dt:
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07/24/2001
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Publication #:
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Pub Dt:
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09/19/2002
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Title:
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PROCESS FOR PRODUCING A FIRST ELECTRODE AND A SECOND ELECTRODE, ELECTRONIC COMPONENT AND ELECTRONIC MEMORY ELEMENT
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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09922471
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Filing Dt:
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08/03/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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CONFIGURATION AND METHOD FOR THE LOW-LOSS WRITING OF AN MRAM
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09922476
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Filing Dt:
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08/03/2001
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Publication #:
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Pub Dt:
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02/07/2002
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Title:
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ELECTRONIC CIRCUIT, TEST-APPARATUS ASSEMBLY, AND METHOD FOR OUTPUTTING A DATA ITEM
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Patent #:
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Issue Dt:
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04/22/2003
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Application #:
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09923703
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Filing Dt:
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08/06/2001
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Publication #:
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Pub Dt:
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02/14/2002
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Title:
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DEVICE AND METHOD FOR COMBINING SCANNING AND IMAGING METHODS IN CHECKING PHOTOMASKS
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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09923720
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Filing Dt:
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08/06/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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TEST APPARATUS FOR SEMICONDUCTOR CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR CIRCUITS
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Patent #:
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Issue Dt:
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05/27/2003
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Application #:
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09925168
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Filing Dt:
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08/08/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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SEMICONDUCTOR MEMORY HAVING A REDUNDANCY CIRCUIT FOR WORD LINES AND METHOD FOR OPERATING THE MEMORY
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09927554
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Filing Dt:
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08/09/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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MEMORY CELL AND PRODUCTION METHOD
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Patent #:
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Issue Dt:
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12/31/2002
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Application #:
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09927556
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Filing Dt:
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08/09/2001
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Publication #:
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Pub Dt:
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05/02/2002
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Title:
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ELECTRONIC DRIVER CIRCUIT FOR WORD LINES IN A MEMORY MATRIX, AND MEMORY APPARATUS
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09927573
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Filing Dt:
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08/09/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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MEMORY CELL, MEMORY CELL CONFIGURATION AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09929303
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Filing Dt:
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08/13/2001
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Publication #:
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Pub Dt:
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02/21/2002
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Title:
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INTEGRATED CIRCUIT, TEST STRUCTURE AND METHOD FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09932893
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Filing Dt:
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08/20/2001
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Publication #:
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Pub Dt:
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08/08/2002
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Title:
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METHOD AND DEVICE FOR STORING AND OUTPUTTING DATA WITH A VIRTUAL CHANNEL
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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09933304
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Filing Dt:
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08/20/2001
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Publication #:
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Pub Dt:
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03/28/2002
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Title:
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CMP PROCESS
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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09935353
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Filing Dt:
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08/22/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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METHOD FOR EXAMINING STRUCTURES ON A WAFER
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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09935503
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Filing Dt:
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08/23/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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METHOD AND DEVICE FOR DATA EXCHANGE BETWEEN MEMORY AND LOGIC MODULES
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Patent #:
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Issue Dt:
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07/16/2002
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Application #:
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09935622
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Filing Dt:
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08/23/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Title:
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MRAM CONFIGURATION
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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09935623
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Filing Dt:
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08/23/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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INTEGRATED SEMICONDUCTOR CONFIGURATION HAVING A SEMICONDUCTOR MEMORY WITH USER PROGRAMMABLE BIT WIDTH
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09938186
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Filing Dt:
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08/23/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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RESISTOR CASCADE FOR FORMING ELECTRICAL REFERENCE QUANTITIES AND ANALOG/DIGITAL CONVERTER
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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09939249
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Filing Dt:
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08/24/2001
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Publication #:
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Pub Dt:
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02/28/2002
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Title:
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METHOD FOR FABRICATING A MICROELECTRONIC COMPONENT
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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09941902
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Filing Dt:
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08/29/2001
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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SEMICONDUCTOR CONFIGURATION WITH OPTIMIZED REFRESH CYCLE
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09941955
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Filing Dt:
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08/28/2001
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Publication #:
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Pub Dt:
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03/21/2002
| | | | |
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Title:
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METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTING CONNECTION
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09941957
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Filing Dt:
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08/28/2001
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Publication #:
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Pub Dt:
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06/27/2002
| | | | |
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Title:
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MODULE TEST SOCKET FOR TEST ADAPTERS
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09942931
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Filing Dt:
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08/30/2001
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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OPC METHOD FOR GENERATING CORRECTED PATTERNS FOR A PHASE-SHIFTING MASK AND ITS TRIMMING MASK AND ASSOCIATED DEVICE AND INTEGRATED CIRCUIT CONFIGURATION
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09946941
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Filing Dt:
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09/04/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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MAGNETORESISTIVE MEMORY AND METHOD FOR READING A MAGNETORESISTIVE MEMORY
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Patent #:
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Issue Dt:
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07/13/2004
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Application #:
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09946994
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Filing Dt:
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09/04/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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EDGE-TRIGGERED D-FLIP-FLOP CIRCUIT
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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09948263
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Filing Dt:
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09/06/2001
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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INTEGRATED CIRCUIT ARRANGEMENT WITH FIELD-SHAPING ELECTRICAL CONDUCTOR
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Patent #:
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Issue Dt:
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10/07/2003
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Application #:
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09949511
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Filing Dt:
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09/07/2001
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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GENERATING MASK LAYOUT DATA FOR SIMULATION OF LITHOGRAPHIC PROCESSES
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09951823
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Filing Dt:
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09/13/2001
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Publication #:
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Pub Dt:
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05/09/2002
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Title:
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ELECTRONIC COMPONENT WITH EXTERNAL CONNECTION ELEMENTS
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09953729
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Filing Dt:
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09/17/2001
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Publication #:
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Pub Dt:
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03/28/2002
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Title:
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INTEGRATED MEMORY HAVING MEMORY CELLS AND BUFFER CAPACITORS
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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09957363
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Filing Dt:
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09/20/2001
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Publication #:
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Pub Dt:
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06/20/2002
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Title:
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METHOD FOR FABRICATING INTEGRATED CIRCUIT ARRANGEMENTS, AND ASSOCIATED CIRCUIT ARRANGEMENTS, IN PARTICULAR TUNNEL CONTACT ELEMENTS
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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09957390
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Filing Dt:
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09/20/2001
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Publication #:
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Pub Dt:
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03/21/2002
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Title:
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INTEGRATED MEMORY AND MEMORY CONFIGURATION WITH A PLURALITY OF MEMORIES AND METHOD OF OPERATING SUCH A MEMORY CONFIGURATION
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09962410
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Filing Dt:
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09/24/2001
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Publication #:
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Pub Dt:
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03/28/2002
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Title:
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1-OUT-OF-N DECODER CIRCUIT
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09967698
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/04/2002
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Title:
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PHOTOMASK, METHOD OF LITHOGRAPHICALLY STRUCTURING A PHOTORESIST LAYER WITH THE PHOTOMASK, AND METHOD OF PRODUCING MAGNETIC MEMORY ELEMENTS
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09970977
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Filing Dt:
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10/04/2001
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Publication #:
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Pub Dt:
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04/25/2002
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Title:
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METHOD FOR FABRICATING A THIN, FREE-STANDING SEMICONDUCTOR DEVICE LAYER AND FOR MAKING A THREE-DIMENSIONALLY INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09975058
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Filing Dt:
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10/11/2001
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Publication #:
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Pub Dt:
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04/18/2002
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Title:
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MRAM CONFIGURATION
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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09977787
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Filing Dt:
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10/15/2001
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Publication #:
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Pub Dt:
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05/09/2002
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Title:
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CIRCUIT AND METHOD FOR TESTING A DATA MEMORY
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Issue Dt:
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09/02/2003
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Application #:
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09977805
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10/15/2001
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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VOLTAGE REGULATING CIRCUIT, IN PARTICULAR FOR SEMICONDUCTOR MEMORIES
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09981856
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Filing Dt:
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10/18/2001
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Publication #:
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Pub Dt:
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05/23/2002
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Title:
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METHOD FOR PRODUCING CIRCUIT STRUCTURES ON A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CONFIGURATION WITH FUNCTIONAL CIRCUIT STRUCTURES AND DUMMY CIRCUIT STRUCTURES
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Patent #:
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Issue Dt:
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09/02/2003
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Application #:
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09991791
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Filing Dt:
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11/19/2001
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Pub Dt:
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06/27/2002
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Title:
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CIRCUIT AND METHOD FOR REFRESHING MEMORY CELLS IN A DRAM
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Issue Dt:
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11/11/2003
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09995209
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11/27/2001
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Publication #:
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Pub Dt:
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06/27/2002
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Title:
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PROCESS FOR PRODUCING A CAPACITOR CONFIGURATION
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02/04/2003
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09996260
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11/28/2001
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Pub Dt:
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07/11/2002
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Title:
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RANDOM ACCESS MEMORY WITH HIDDEN BITS
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Issue Dt:
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11/18/2003
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Application #:
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09996959
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11/20/2001
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Pub Dt:
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10/24/2002
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Title:
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METHOD FOR FABRICATING A CAPACITOR CONFIGURATION
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06/29/2004
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09997983
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11/29/2001
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Pub Dt:
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05/30/2002
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Title:
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INTEGRATED MAGNETORESISTIVE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE MEMORY
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02/04/2003
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09998723
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11/30/2001
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06/27/2002
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METHOD AND CIRCUIT CONFIGURATION FOR CONTROLLING A DATA DRIVER
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04/29/2003
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09998725
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11/30/2001
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06/13/2002
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CIRCUIT CONFIGURATION AND METHOD FOR SYNCHRONIZATION
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06/08/2004
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09999323
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10/31/2001
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05/16/2002
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METHOD OF STRUCTURING A PHOTORESIST LAYER
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02/07/2006
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09999382
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10/31/2001
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07/25/2002
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METHOD AND APPARATUS FOR DATA TRANSMISSION
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11/16/2004
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10000690
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11/15/2001
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Pub Dt:
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05/15/2003
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Title:
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DATA PROCESSING SYSTEM HAVING CONFIGURABLE COMPONENTS
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12/09/2003
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Application #:
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10000691
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11/15/2001
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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CONFIGURATION AND METHOD FOR INCREASING THE RETENTION TIME AND THE STORAGE SECURITY IN A FERROELECTRIC OR FERROMAGNETIC SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10001176
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11/02/2001
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Publication #:
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Pub Dt:
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08/22/2002
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Title:
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DATA MEMORY WITH A PLURALITY OF MEMORY BANKS
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Issue Dt:
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11/05/2002
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Application #:
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10005944
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12/03/2001
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Publication #:
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Pub Dt:
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07/04/2002
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Title:
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METHOD FOR OUTPUTTING DATA AND CIRCUIT CONFIGURATION WITH DRIVER CIRCUIT
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07/01/2003
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Application #:
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10005977
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12/03/2001
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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MEASURING DEVICE FOR TESTING UNPACKED CHIPS
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02/25/2003
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10008114
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11/08/2001
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Pub Dt:
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05/30/2002
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Title:
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CIRCUIT CONFIGURATION WITH INTERNAL SUPPLY VOLTAGE
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04/08/2003
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10008793
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11/13/2001
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05/23/2002
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03/11/2003
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10012161
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10/29/2001
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10/03/2002
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01/27/2004
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10012163
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10/26/2001
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07/04/2002
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10/25/2005
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10012164
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10/26/2001
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08/22/2002
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01/18/2005
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10012168
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10/26/2001
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06/06/2002
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05/06/2003
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10014776
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11/07/2001
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05/23/2002
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MEMORY CONFIGURATION WITH A CENTRAL CONNECTION AREA
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07/15/2003
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10015829
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12/13/2001
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07/25/2002
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INTEGRATED MEMORY HAVING A CELL ARRAY AND CHARGE EQUALIZATION DEVICES, AND METHOD FOR THE ACCELERATED WRITING OF A DATUM TO THE INTEGRATED MEMORY
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06/21/2005
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10016863
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12/14/2001
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07/04/2002
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07/13/2004
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10033123
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10/22/2001
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06/06/2002
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INTEGRATED CIRCUIT HAVING A SYNCHRONOUS AND AN ASYNCHRONOUS CIRCUIT AND METHOD FOR OPERATING SUCH AN INTEGRATED CIRCUIT
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12/30/2003
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10033131
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10/22/2001
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09/19/2002
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INTEGRATED CIRCUIT HAVING A TEST OPERATING MODE AND METHOD FOR TESTING A MULTIPLICITY OF SUCH CIRCUITS
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12/02/2003
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10033877
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12/27/2001
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07/11/2002
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07/27/2004
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10034053
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12/20/2001
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09/12/2002
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12/16/2003
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10034931
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11/21/2001
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09/05/2002
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11/12/2002
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10046395
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10/19/2001
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06/27/2002
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06/24/2003
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01/15/2002
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07/18/2002
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SEMICONDUCTOR MEMORY HAVING A DELAY LOCKED LOOP
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03/23/2004
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10053970
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01/22/2002
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07/25/2002
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03/09/2004
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10053983
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01/22/2002
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07/25/2002
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12/02/2003
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10054195
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01/22/2002
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08/22/2002
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03/02/2004
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01/22/2002
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08/15/2002
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10/05/2004
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10055522
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01/23/2002
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07/25/2002
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04/12/2005
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10060445
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01/30/2002
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08/01/2002
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07/05/2005
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10060447
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01/30/2002
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08/01/2002
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11/29/2005
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01/30/2002
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08/01/2002
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09/16/2003
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10065213
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09/26/2002
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04/03/2003
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11/04/2003
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02/13/2002
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09/05/2002
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11/29/2005
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02/14/2002
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09/26/2002
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05/27/2003
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02/14/2002
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09/12/2002
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11/13/2007
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02/13/2002
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08/15/2002
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08/10/2004
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02/15/2002
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08/15/2002
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09/27/2005
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02/25/2002
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09/12/2002
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05/17/2005
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03/04/2002
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09/05/2002
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07/08/2003
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03/05/2002
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09/05/2002
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10/28/2003
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03/12/2002
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09/12/2002
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05/20/2003
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03/12/2002
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09/12/2002
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02/08/2005
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03/26/2002
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09/26/2002
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10/28/2003
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03/25/2002
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09/26/2002
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12/07/2004
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03/26/2002
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09/26/2002
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07/08/2003
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03/28/2002
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10/03/2002
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11/11/2003
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04/10/2002
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10/10/2002
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INTEGRATED CLOCK GENERATOR, PARTICULARLY FOR DRIVING A SEMICONDUCTOR MEMORY WITH A TEST SIGNAL
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06/03/2003
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04/18/2002
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10/24/2002
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03/11/2008
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04/25/2002
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10/31/2002
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10/17/2006
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07/10/2003
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01/11/2005
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04/26/2002
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01/30/2003
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12/12/2002
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01/25/2005
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05/03/2002
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12/26/2002
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02/15/2005
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11/07/2002
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02/10/2004
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11/07/2002
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