Total properties:
207
Page
1
of
3
Pages:
1 2 3
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
11067496
|
Filing Dt:
|
02/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/31/2006
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A DIELECTRIC LAYER AND CORRESPONDING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11081085
|
Filing Dt:
|
03/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
|
Title:
|
METHOD FOR OPERATING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11086922
|
Filing Dt:
|
03/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/21/2006
| | | | |
|
Title:
|
INTEGRATED DEVICE AND ELECTRONIC SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11099384
|
Filing Dt:
|
04/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/05/2006
| | | | |
|
Title:
|
ELECTRONIC DEVICE WITH A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11100500
|
Filing Dt:
|
04/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/12/2006
| | | | |
|
Title:
|
PARTIALLY RECESSED DRAM CELL STRUCTURE AND METHOD OF MAKING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
11105580
|
Filing Dt:
|
04/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
|
Title:
|
MANUFACTURING METHOD FOR A RECESSED CHANNEL ARRAY TRANSISTOR AND CORRESPONDING RECESSED CHANNEL ARRAY TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
11108179
|
Filing Dt:
|
04/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
|
Title:
|
REDUNDANCY CIRCUITS FOR SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11114566
|
Filing Dt:
|
04/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/26/2006
| | | | |
|
Title:
|
CLOSING DISK FOR IMMERSION HEAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
11115391
|
Filing Dt:
|
04/27/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
MANUFACTURING METHOD FOR A TRENCH CAPACITOR HAVING AN ISOLATION COLLAR ELECTRICALLY CONNECTED WITH A SUBSTRATE ON A SINGLE SIDE VIA A BURIED CONTACT FOR USE IN A SEMICONDUCTOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11116875
|
Filing Dt:
|
04/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
VOLTAGE MONITORING TEST MODE AND TEST ADAPTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11117855
|
Filing Dt:
|
04/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
SELF-REFRESH CIRCUIT WITH OPTIMIZED POWER CONSUMPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11118036
|
Filing Dt:
|
04/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
SENSE AMPLIFIER FOR ELIMINATING LEAKAGE CURRENT DUE TO BIT LINE SHORTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11118037
|
Filing Dt:
|
04/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
MEMORY HAVING POWER-UP CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11118374
|
Filing Dt:
|
05/02/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
DISTRIBUTION OF SIGNALS THROUGHOUT A SPINE OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11118768
|
Filing Dt:
|
05/02/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/02/2006
| | | | |
|
Title:
|
MEMORY CELL ARRAY AND METHOD OF MANUFACTURING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11119029
|
Filing Dt:
|
04/29/2005
|
|
Title:
|
TARGETS FOR MEASUREMENTS IN SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2008
|
Application #:
|
11119320
|
Filing Dt:
|
04/29/2005
|
|
Title:
|
METHOD FOR REDUCING LITHOGRAPHY PATTERN DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11122016
|
Filing Dt:
|
05/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
|
Title:
|
APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION WITHIN AN OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
11126392
|
Filing Dt:
|
05/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING STACKED CHIPS AND A CORRESPONDING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11127022
|
Filing Dt:
|
05/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR WRITING DATA INTO A NON-VOLATILE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11128431
|
Filing Dt:
|
05/13/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/16/2006
| | | | |
|
Title:
|
METHOD FOR EXPOSING A SEMICONDUCTOR WAFER BY APPLYING PERIODIC MOVEMENT TO A COMPONENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11131356
|
Filing Dt:
|
05/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
LITHOGRAPHY METHOD AND SYSTEM WITH CORRECTION OF OVERLAY OFFSET ERRORS CAUSED BY WAFER PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11132562
|
Filing Dt:
|
05/19/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
|
Title:
|
ECC FLAG FOR TESTING ON-CHIP ERROR CORRECTION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
11133491
|
Filing Dt:
|
05/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
LOW POWER PHASE CHANGE MEMORY CELL WITH LARGE READ SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11135002
|
Filing Dt:
|
05/23/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PRODUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2009
|
Application #:
|
11135611
|
Filing Dt:
|
05/23/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/23/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR ADAPTING CIRCUIT COMPONENTS OF A MEMORY MODULE TO CHANGING OPERATING CONDITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2007
|
Application #:
|
11137736
|
Filing Dt:
|
05/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
|
Title:
|
INTEGRATED CIRCUIT CHIP HAVING A FIRST DELAY CIRCUIT TRIMMED VIA A SECOND DELAY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11138462
|
Filing Dt:
|
05/27/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
|
Title:
|
TEST MODE FOR PROGRAMMING RATE AND PRECHARGE TIME FOR DRAM ACTIVATE-PRECHARGE CYCLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11139975
|
Filing Dt:
|
05/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
11139976
|
Filing Dt:
|
05/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2007
|
Application #:
|
11140143
|
Filing Dt:
|
05/27/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
|
Title:
|
METHOD OF FORMING A MEMORY CELL ARRAY AND A MEMORY CELL ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11141255
|
Filing Dt:
|
05/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
11/30/2006
| | | | |
|
Title:
|
METHOD OF PROGRAMMING OF A NON-VOLATILE MEMORY CELL COMPRISING STEPS OF APPLYING CONSTANT VOLTAGE AND THEN CONSTANT CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11142023
|
Filing Dt:
|
06/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
|
Title:
|
IMPLEMENTATION OF A FUSING SCHEME TO ALLOW INTERNAL VOLTAGE TRIMMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
11144791
|
Filing Dt:
|
06/06/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
|
Title:
|
SENSING CURRENT RECYCLING METHOD DURING SELF-REFRESH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11145520
|
Filing Dt:
|
06/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
|
Title:
|
REFERENCE SCHEME FOR A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
11145551
|
Filing Dt:
|
06/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
|
Title:
|
SENSING SCHEME FOR A NON-VOLATILE SEMICONDUCTOR MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11147260
|
Filing Dt:
|
06/08/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATED BEAM OPTIMIZATION IN A SCANNING ELECTRON MICROSCOPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11151650
|
Filing Dt:
|
06/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
|
Title:
|
MEMORY DEVICE WITH ERROR CORRECTION CODE MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11152769
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
HIGH-SPEED INTERFACE CIRCUIT FOR SEMICONDUCTOR MEMORY CHIPS AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR MEMORY CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11152793
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MEMORY CELL ARRAY AND METHOD OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11153187
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MEMORY HAVING PARITY GENERATION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
11153795
|
Filing Dt:
|
06/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MEMORY HAVING PARITY ERROR CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
11153969
|
Filing Dt:
|
06/16/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/19/2006
| | | | |
|
Title:
|
RANDOM ACCESS MEMORY HAVING VOLTAGE PROVIDED OUT OF BOOSTED SUPPLY VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11155277
|
Filing Dt:
|
06/17/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
MULTI-CHIP DEVICE AND METHOD FOR PRODUCING A MULTI-CHIP DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11157143
|
Filing Dt:
|
06/20/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
METHOD OF FORMING A CONTACT IN A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11157425
|
Filing Dt:
|
06/21/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
|
Title:
|
OUTPUT CIRCUIT THAT TURNS OFF ONE OF A FIRST CIRCUIT AND A SECOND CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11166788
|
Filing Dt:
|
06/24/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
|
Title:
|
MEMORY DEVICE AND METHOD FOR OPERATING THE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11168820
|
Filing Dt:
|
06/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
|
Title:
|
MULTI-CHIP DEVICE AND METHOD FOR PRODUCING A MULTI-CHIP DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11170187
|
Filing Dt:
|
06/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
METHOD FOR PRODUCING CHARGE-TRAPPING MEMORY CELL ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11170190
|
Filing Dt:
|
06/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
HANDLING UNIT FOR ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11170200
|
Filing Dt:
|
06/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
FLUIDS FOR IMMERSION LITHOGRAPHY SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11170887
|
Filing Dt:
|
06/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
SYNCHRONOUS SIGNAL GENERATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/2009
|
Application #:
|
11172366
|
Filing Dt:
|
06/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR PRODUCT AND SEMICONDUCTOR PRODUCT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11172367
|
Filing Dt:
|
06/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SENSING A STATE OF A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2007
|
Application #:
|
11172421
|
Filing Dt:
|
06/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2007
| | | | |
|
Title:
|
METHOD FOR PROGRAMMING MULTI-BIT CHARGE-TRAPPING MEMORY CELL ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11175280
|
Filing Dt:
|
07/07/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SELECTIVELY ACCESSING AND CONFIGURING INDIVIDUAL CHIPS OF A SEMI-CONDUCTOR WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
11179345
|
Filing Dt:
|
07/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
NON-VOLATILE MEMORY CELL DEVICE, PROGRAMMING ELEMENT AND METHOD FOR PROGRAMMING DATA INTO A PLURALITY OF NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
11179358
|
Filing Dt:
|
07/12/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
COLUMN REDUNDANCY REUSE IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
11181387
|
Filing Dt:
|
07/13/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11182022
|
Filing Dt:
|
07/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
RESISTIVITY CHANGING MEMORY CELL HAVING NANOWIRE ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11182063
|
Filing Dt:
|
07/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE INCLUDING A SIGNAL CONTROL DEVICE AND METHOD OF OPERATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11182064
|
Filing Dt:
|
07/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
INTEGRATED RECEIVER CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2007
|
Application #:
|
11183224
|
Filing Dt:
|
07/14/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/18/2007
| | | | |
|
Title:
|
MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE AND CORRESPONDING INTEGRATED SEMICONDUCTOR STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11184074
|
Filing Dt:
|
07/19/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
LOW RESISTANCE CONTACT IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2007
|
Application #:
|
11187321
|
Filing Dt:
|
07/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
TEMPERATURE UPDATE MASKING TO ENSURE CORRECT MEASUREMENT OF TEMPERATURE WHEN REFERENCES BECOME UNSTABLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
|
11187546
|
Filing Dt:
|
07/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
CLOCKED STANDBY MODE WITH MAXIMUM CLOCK FREQUENCY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
11187643
|
Filing Dt:
|
07/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
DISABLING CLOCKED STANDBY MODE BASED ON DEVICE TEMPERATURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11187693
|
Filing Dt:
|
07/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2007
| | | | |
|
Title:
|
NON-VOLATILE MEMORY CELLS AND METHODS FOR FABRICATING NON-VOLATILE MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
11190068
|
Filing Dt:
|
07/26/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
SUBSTRATE BASED IC-PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11191837
|
Filing Dt:
|
07/28/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
NON-VOLATILE, RESISTIVE MEMORY CELL BASED ON METAL OXIDE NANOPARTICLES, PROCESS FOR MANUFACTURING THE SAME AND MEMORY CELL ARRANGEMENT OF THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
11192335
|
Filing Dt:
|
07/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
RE-DRIVING CAWD AND RD SIGNAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
11192981
|
Filing Dt:
|
07/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE BASED ON LEAD-ON-CHIP ARCHITECTURE, THE FABRICATION THEREOF AND A LEADFRAME FOR IMPLEMENTING IN A SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
11193026
|
Filing Dt:
|
07/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY WITH CHARGE-TRAPPING STACK ARRANGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
11193184
|
Filing Dt:
|
07/29/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY CHIP AND MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
11194302
|
Filing Dt:
|
08/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
MAINTAINING INTERNAL VOLTAGES OF AN INTEGRATED CIRCUIT IN RESPONSE TO A CLOCKED STANDBY MODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11194489
|
Filing Dt:
|
08/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
METHOD OF PRODUCING PITCH FRACTIONIZATIONS IN SEMICONDUCTOR TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11194773
|
Filing Dt:
|
08/01/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/01/2007
| | | | |
|
Title:
|
METHOD OF OPERATING A MEMORY DEVICE, MEMORY MODULE, AND A MEMORY DEVICE COMPRISING THE MEMORY MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
11196369
|
Filing Dt:
|
08/03/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
|
Title:
|
TECHNIQUE TO SUPPRESS LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11198129
|
Filing Dt:
|
08/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
|
Title:
|
CARD STIFFENER AND INSERTION TOOL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2008
|
Application #:
|
11198246
|
Filing Dt:
|
08/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
|
Title:
|
MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
11198366
|
Filing Dt:
|
08/05/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/08/2007
| | | | |
|
Title:
|
SYSTEM MEMORY DEVICE HAVING A DUAL PORT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11200256
|
Filing Dt:
|
08/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
METHOD FOR OPTIMIZING A PHOTOLITHOGRAPHIC MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2007
|
Application #:
|
11200504
|
Filing Dt:
|
08/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR READING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11203927
|
Filing Dt:
|
08/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
MEMORY DEVICE AND METHOD OF MANUFACTURING A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2007
|
Application #:
|
11204281
|
Filing Dt:
|
08/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
STACKABLE SINGLE PACKAGE AND STACKED MULTI-CHIP ASSEMBLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2008
|
Application #:
|
11204604
|
Filing Dt:
|
08/15/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2007
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR MONITORING PRECISION OF WAFER PLACEMENT ALIGNMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11206481
|
Filing Dt:
|
08/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
02/22/2007
| | | | |
|
Title:
|
SIGNAL ROUTING ON REDISTRIBUTION LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11210372
|
Filing Dt:
|
08/24/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING A SWITCH.
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
11211824
|
Filing Dt:
|
08/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
DIFFERENTIAL DUTY CYCLE RESTORATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11211825
|
Filing Dt:
|
08/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
DELAY LOCKED LOOP USING A FIFO CIRCUIT TO SYNCHRONIZE BETWEEN BLENDER AND COARSE DELAY CONTROL SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2008
|
Application #:
|
11215442
|
Filing Dt:
|
08/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
DUTY CYCLE CORRECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11215779
|
Filing Dt:
|
08/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
CLOCK CONTROLLER WITH INTEGRATED DLL AND DCC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
11216524
|
Filing Dt:
|
08/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
METHOD FOR PROCESSING A LAYERED STACK IN THE PRODUCTION OF A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11217081
|
Filing Dt:
|
08/30/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
|
Title:
|
DATA MEMORY SYSTEM AND METHOD FOR TRANSFERRING DATA INTO A DATA MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11217086
|
Filing Dt:
|
08/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
DUTY CYCLE DETECTOR WITH FIRST AND SECOND OSCILLATING SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11217122
|
Filing Dt:
|
08/31/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
|
Title:
|
METHOD OF FORMING CONTACTS USING AUXILIARY STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11222282
|
Filing Dt:
|
09/08/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
|
Title:
|
METHOD FOR WRITING DATA INTO A MEMORY CELL OF A CONDUCTIVE BRIDGING RANDOM ACCESS MEMORY, MEMORY CIRCUIT AND CBRAM MEMORY CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/2010
|
Application #:
|
11222540
|
Filing Dt:
|
09/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
|
Title:
|
INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11222613
|
Filing Dt:
|
09/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
|
Title:
|
METHOD OF MANUFACTURING A TRANSISTOR AND A METHOD OF FORMING A MEMORY DEVICE WITH ISOLATION TRENCHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
11223801
|
Filing Dt:
|
09/09/2005
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2007
| | | | |
|
Title:
|
METHOD FOR COMPENSATING FILM HEIGHT MODULATIONS IN SPIN COATING OF A RESIST FILM LAYER
|
|
