skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
12/29/2015
Application #:
13447751
Filing Dt:
04/16/2012
Publication #:
Pub Dt:
10/17/2013
Title:
REDUCING REPEATER POWER
2
Patent #:
Issue Dt:
04/07/2015
Application #:
13447982
Filing Dt:
04/16/2012
Publication #:
Pub Dt:
08/09/2012
Title:
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
3
Patent #:
Issue Dt:
06/09/2015
Application #:
13448428
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
08/16/2012
Title:
Operation of a Noise Cancellation Device
4
Patent #:
NONE
Issue Dt:
Application #:
13448500
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
08/09/2012
Title:
METHOD OF FORMING UNDERBUMP METALLURGY STRUCTURE EMPLOYING SPUTTER-DEPOSITED NICKEL COPPER ALLOY
5
Patent #:
Issue Dt:
02/18/2014
Application #:
13448749
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
10/17/2013
Title:
SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
6
Patent #:
Issue Dt:
04/14/2015
Application #:
13448775
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
10/17/2013
Title:
SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS
7
Patent #:
NONE
Issue Dt:
Application #:
13448780
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
08/09/2012
Title:
INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
8
Patent #:
NONE
Issue Dt:
Application #:
13448876
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
10/17/2013
Title:
METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING
9
Patent #:
Issue Dt:
08/13/2013
Application #:
13448925
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
08/09/2012
Title:
SYSTEM AND METHOD FOR MODELING I/O SIMULTANEOUS SWITCHING NOISE
10
Patent #:
Issue Dt:
07/23/2013
Application #:
13449009
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
08/09/2012
Title:
Generating Capacitance Look-up Tables for Wiring Patterns in the Presence of Metal Fills
11
Patent #:
Issue Dt:
05/07/2013
Application #:
13449139
Filing Dt:
04/17/2012
Publication #:
Pub Dt:
08/09/2012
Title:
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
12
Patent #:
Issue Dt:
10/15/2013
Application #:
13449378
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/09/2012
Title:
POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM
13
Patent #:
Issue Dt:
07/23/2013
Application #:
13449419
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/09/2012
Title:
LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE
14
Patent #:
Issue Dt:
06/24/2014
Application #:
13449433
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
10/24/2013
Title:
ETCH STOP LAYER FORMATION IN METAL GATE PROCESS
15
Patent #:
Issue Dt:
10/01/2013
Application #:
13449708
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
10/24/2013
Title:
STRUCTURE FOR REMOVABLE PROCESSOR SOCKET
16
Patent #:
Issue Dt:
02/04/2014
Application #:
13449732
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/09/2012
Title:
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
17
Patent #:
Issue Dt:
06/16/2015
Application #:
13449741
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/23/2012
Title:
Process of Multiple Exposures With Spin Castable Films
18
Patent #:
NONE
Issue Dt:
Application #:
13449885
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
04/25/2013
Title:
MULTI-MODAL DATA ANALYSIS FOR DEFECT IDENTIFICATION
19
Patent #:
Issue Dt:
03/26/2013
Application #:
13450004
Filing Dt:
04/18/2012
Publication #:
Pub Dt:
08/16/2012
Title:
Design Structure for High Density Stable Static Random Access Memory
20
Patent #:
Issue Dt:
02/03/2015
Application #:
13451054
Filing Dt:
04/19/2012
Publication #:
Pub Dt:
10/24/2013
Title:
Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric
21
Patent #:
Issue Dt:
12/03/2013
Application #:
13451087
Filing Dt:
04/19/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO
22
Patent #:
Issue Dt:
07/08/2014
Application #:
13451141
Filing Dt:
04/19/2012
Publication #:
Pub Dt:
10/24/2013
Title:
FARBRICATION OF A LOCALIZED THICK BOX WITH PLANAR OXIDE/SOI INTERFACE ON BULK SILICON SUBSTRATE FOR SILICON PHOTONICS INTEGRATION
23
Patent #:
Issue Dt:
11/19/2013
Application #:
13451382
Filing Dt:
04/19/2012
Publication #:
Pub Dt:
10/24/2013
Title:
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
24
Patent #:
NONE
Issue Dt:
Application #:
13451806
Filing Dt:
04/20/2012
Publication #:
Pub Dt:
10/24/2013
Title:
BICMOS DEVICES ON ETSOI
25
Patent #:
Issue Dt:
09/16/2014
Application #:
13451902
Filing Dt:
04/20/2012
Publication #:
Pub Dt:
10/24/2013
Title:
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
26
Patent #:
NONE
Issue Dt:
Application #:
13452335
Filing Dt:
04/20/2012
Publication #:
Pub Dt:
10/24/2013
Title:
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
27
Patent #:
Issue Dt:
11/19/2013
Application #:
13452454
Filing Dt:
04/20/2012
Publication #:
Pub Dt:
08/09/2012
Title:
METHOD AND SYSTEM FOR FEATURE FUNCTION AWARE PRIORITY PRINTING
28
Patent #:
Issue Dt:
09/27/2016
Application #:
13452857
Filing Dt:
04/21/2012
Publication #:
Pub Dt:
08/09/2012
Title:
NANOPORE CAPTURE SYSTEM
29
Patent #:
Issue Dt:
10/01/2013
Application #:
13453027
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
09/26/2013
Title:
FLEXIBLE FIBER TO WAFER INTERFACE
30
Patent #:
NONE
Issue Dt:
Application #:
13453131
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
10/24/2013
Title:
SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE
31
Patent #:
Issue Dt:
08/19/2014
Application #:
13453165
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/23/2012
Title:
STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING
32
Patent #:
Issue Dt:
10/29/2013
Application #:
13453215
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/09/2012
Title:
CMOS STRUCTURE INCLUDING NON-PLANAR HYBRID ORIENTATION SUBSTRATE WITH PLANAR GATE ELECTRODES & METHOD FOR FABRICATION
33
Patent #:
Issue Dt:
05/21/2013
Application #:
13453262
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/16/2012
Title:
FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS
34
Patent #:
Issue Dt:
07/16/2013
Application #:
13453426
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/16/2012
Title:
STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS
35
Patent #:
Issue Dt:
05/28/2013
Application #:
13453508
Filing Dt:
04/23/2012
Publication #:
Pub Dt:
08/16/2012
Title:
STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES
36
Patent #:
NONE
Issue Dt:
Application #:
13454172
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
11/01/2012
Title:
ESD PROTECTION DEVICE
37
Patent #:
Issue Dt:
06/16/2015
Application #:
13454220
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
10/24/2013
Title:
Automated Fault and Recovery System
38
Patent #:
Issue Dt:
02/24/2015
Application #:
13454518
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
08/16/2012
Title:
BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES
39
Patent #:
Issue Dt:
01/20/2015
Application #:
13454635
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
08/16/2012
Title:
INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT
40
Patent #:
Issue Dt:
04/01/2014
Application #:
13454709
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE
41
Patent #:
Issue Dt:
08/05/2014
Application #:
13454723
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING
42
Patent #:
Issue Dt:
10/15/2013
Application #:
13454795
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
10/24/2013
Title:
ENABLING STATISTICAL TESTING USING DETERMINISTIC MULTI-CORNER TIMING ANALYSIS
43
Patent #:
Issue Dt:
10/07/2014
Application #:
13454935
Filing Dt:
04/24/2012
Publication #:
Pub Dt:
10/24/2013
Title:
COMBINED SOFT DETECTION AND SOFT DECODING IN TAPE DRIVE STORAGE CHANNELS.
44
Patent #:
Issue Dt:
01/08/2013
Application #:
13455174
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/16/2012
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER
45
Patent #:
Issue Dt:
03/25/2014
Application #:
13455177
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/23/2012
Title:
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
46
Patent #:
Issue Dt:
04/01/2014
Application #:
13455181
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
MODELING THE TOTAL PARASITIC RESISTANCES OF THE SOURCE/DRAIN REGIONS OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR
47
Patent #:
Issue Dt:
11/26/2013
Application #:
13455394
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS
48
Patent #:
NONE
Issue Dt:
Application #:
13455505
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/16/2012
Title:
METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
49
Patent #:
Issue Dt:
03/12/2013
Application #:
13455507
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/16/2012
Title:
AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES
50
Patent #:
Issue Dt:
03/25/2014
Application #:
13455653
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE
51
Patent #:
Issue Dt:
05/07/2013
Application #:
13455725
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
52
Patent #:
Issue Dt:
06/24/2014
Application #:
13455732
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES
53
Patent #:
Issue Dt:
09/03/2013
Application #:
13455789
Filing Dt:
04/25/2012
Title:
METHOD AND SYSTEM FOR OPTIMAL COUNTEREXAMPLE-GUIDED PROOF-BASED ABSTRACTION
54
Patent #:
Issue Dt:
11/19/2013
Application #:
13455839
Filing Dt:
04/25/2012
Publication #:
Pub Dt:
10/31/2013
Title:
CONSTRUCTING INDUCTIVE COUNTEREXAMPLES IN A MULTI-ALGORITHM VERIFICATION FRAMEWORK
55
Patent #:
NONE
Issue Dt:
Application #:
13456282
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
08/16/2012
Title:
Device component forming method with a trim step prior to sidewall image transfer (SIT) processing
56
Patent #:
Issue Dt:
03/04/2014
Application #:
13456456
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/31/2013
Title:
NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT
57
Patent #:
Issue Dt:
01/14/2014
Application #:
13456591
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/31/2013
Title:
SWAPPING PORTS TO CHANGE THE TIMING WINDOW OVERLAP OF ADJACENT NETS
58
Patent #:
Issue Dt:
09/02/2014
Application #:
13456596
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
12/27/2012
Title:
ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
59
Patent #:
Issue Dt:
12/23/2014
Application #:
13456745
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/25/2012
Title:
Generating Constraints in a Class Model
60
Patent #:
Issue Dt:
11/26/2013
Application #:
13456921
Filing Dt:
04/26/2012
Publication #:
Pub Dt:
10/31/2013
Title:
FINFET DIODE WITH INCREASED JUNCTION AREA
61
Patent #:
Issue Dt:
10/07/2014
Application #:
13457529
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
FINFET WITH ENHANCED EMBEDDED STRESSOR
62
Patent #:
Issue Dt:
09/17/2013
Application #:
13457551
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
11/08/2012
Title:
GENERATING PHYSICAL DESIGNS FOR ELECTRONIC CIRCUIT BOARDS
63
Patent #:
Issue Dt:
02/03/2015
Application #:
13457601
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)
64
Patent #:
Issue Dt:
03/10/2015
Application #:
13457692
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE
65
Patent #:
Issue Dt:
08/09/2016
Application #:
13457722
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING
66
Patent #:
Issue Dt:
09/30/2014
Application #:
13457735
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
67
Patent #:
Issue Dt:
11/11/2014
Application #:
13457748
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS
68
Patent #:
NONE
Issue Dt:
Application #:
13457847
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/31/2013
Title:
CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
69
Patent #:
NONE
Issue Dt:
Application #:
13457932
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
08/23/2012
Title:
STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
70
Patent #:
Issue Dt:
07/09/2013
Application #:
13458534
Filing Dt:
04/27/2012
Publication #:
Pub Dt:
10/25/2012
Title:
ENHANCING REDUNDANCY REMOVAL WITH EARLY MERGING
71
Patent #:
Issue Dt:
06/14/2016
Application #:
13459460
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
10/31/2013
Title:
Assembly of Electronic and Optical Devices
72
Patent #:
Issue Dt:
06/24/2014
Application #:
13459785
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
10/31/2013
Title:
ELONGATED VIA STRUCTURES
73
Patent #:
Issue Dt:
07/23/2013
Application #:
13459863
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
01/03/2013
Title:
MATCHING SYSTEMS WITH POWER AND THERMAL DOMAINS
74
Patent #:
Issue Dt:
11/26/2013
Application #:
13460369
Filing Dt:
04/30/2012
Publication #:
Pub Dt:
06/20/2013
Title:
GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES
75
Patent #:
Issue Dt:
02/18/2014
Application #:
13461912
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
STRUCTURE FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
76
Patent #:
Issue Dt:
08/12/2014
Application #:
13461935
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
11/07/2013
Title:
DOPED CORE TRIGATE FET STRUCTURE AND METHOD
77
Patent #:
Issue Dt:
09/30/2014
Application #:
13461960
Filing Dt:
05/02/2012
Publication #:
Pub Dt:
08/23/2012
Title:
PHOTORESIST COMPOSITIONS
78
Patent #:
Issue Dt:
04/12/2016
Application #:
13462964
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
08/30/2012
Title:
METHOD AND APPARATUS FOR PROBING A WAFER
79
Patent #:
Issue Dt:
05/20/2014
Application #:
13463283
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
08/23/2012
Title:
METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
80
Patent #:
NONE
Issue Dt:
Application #:
13463402
Filing Dt:
05/03/2012
Publication #:
Pub Dt:
11/07/2013
Title:
SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
81
Patent #:
Issue Dt:
09/03/2013
Application #:
13463857
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
02/28/2013
Title:
ESTIMATING CLOCK SKEW
82
Patent #:
Issue Dt:
07/02/2013
Application #:
13463879
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
08/30/2012
Title:
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
83
Patent #:
Issue Dt:
02/04/2014
Application #:
13464131
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
11/07/2013
Title:
CURRENT LEAKAGE IN RC ESD CLAMPS
84
Patent #:
Issue Dt:
09/16/2014
Application #:
13464267
Filing Dt:
05/04/2012
Publication #:
Pub Dt:
10/03/2013
Title:
LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION
85
Patent #:
Issue Dt:
09/24/2013
Application #:
13465115
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
09/27/2012
Title:
TRANSACTIONAL MEMORY PREEMPTION MECHANISM
86
Patent #:
Issue Dt:
05/26/2015
Application #:
13465159
Filing Dt:
05/07/2012
Publication #:
Pub Dt:
11/07/2013
Title:
FORMING CMOS WITH CLOSE PROXIMITY STRESSORS
87
Patent #:
NONE
Issue Dt:
Application #:
13466973
Filing Dt:
05/08/2012
Publication #:
Pub Dt:
05/23/2013
Title:
REDUCED LEAKAGE BANKED WORDLINE HEADER
88
Patent #:
Issue Dt:
06/25/2013
Application #:
13467126
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
08/30/2012
Title:
NANOWIRE MESH FET WITH MULTIPLE THRESHOLD VOLTAGES
89
Patent #:
Issue Dt:
06/04/2013
Application #:
13467191
Filing Dt:
05/09/2012
Title:
MITIGATION OF MASK DEFECTS BY PATTERN SHIFTING
90
Patent #:
Issue Dt:
12/25/2012
Application #:
13467385
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
08/30/2012
Title:
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
91
Patent #:
Issue Dt:
11/05/2013
Application #:
13467425
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
11/14/2013
Title:
METHOD AND SYSTEM FOR OPTIMAL DIAMETER BOUNDING OF DESIGNS WITH COMPLEX FEED-FORWARD COMPONENTS
92
Patent #:
NONE
Issue Dt:
Application #:
13467537
Filing Dt:
05/09/2012
Publication #:
Pub Dt:
08/30/2012
Title:
METHOD FOR IMPARTING A CONTROLLED AMOUNT OF STRESS IN SEMICONDUCTOR DEVICES FOR FABRICATING THIN FLEXIBLE CIRCUITS
93
Patent #:
Issue Dt:
07/22/2014
Application #:
13468223
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/13/2012
Title:
PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES
94
Patent #:
Issue Dt:
09/16/2014
Application #:
13468232
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/13/2012
Title:
METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
95
Patent #:
Issue Dt:
02/11/2014
Application #:
13468268
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
11/14/2013
Title:
INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL)
96
Patent #:
Issue Dt:
07/09/2013
Application #:
13468270
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
Structure and Method for Manufacturing Asymmetric Devices
97
Patent #:
Issue Dt:
12/24/2013
Application #:
13468281
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
98
Patent #:
Issue Dt:
09/03/2013
Application #:
13468307
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
09/06/2012
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
99
Patent #:
Issue Dt:
07/21/2015
Application #:
13468576
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
11/14/2013
Title:
PRINTED TRANSISTOR AND FABRICATION METHOD
100
Patent #:
Issue Dt:
08/05/2014
Application #:
13468609
Filing Dt:
05/10/2012
Publication #:
Pub Dt:
08/30/2012
Title:
THROUGH SUBSTRATE VIAS
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

Search Results as of: 05/09/2024 11:13 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT