|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
13447751
|
Filing Dt:
|
04/16/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
REDUCING REPEATER POWER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2015
|
Application #:
|
13447982
|
Filing Dt:
|
04/16/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR FABRICATING OR ALTERING MICROSTRUCTURES USING LOCAL CHEMICAL ALTERATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13448428
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Operation of a Noise Cancellation Device
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13448500
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD OF FORMING UNDERBUMP METALLURGY STRUCTURE EMPLOYING SPUTTER-DEPOSITED NICKEL COPPER ALLOY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13448749
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES, AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING FIN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13448775
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13448780
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
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08/09/2012
| | | | |
Title:
|
INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13448876
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
10/17/2013
| | | | |
Title:
|
METHOD FOR FORMING SEMICONDUCTOR DEVICE WITH EPITAXY SOURCE AND DRAIN REGIONS INDEPENDENT OF PATTERNING AND LOADING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
13448925
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
SYSTEM AND METHOD FOR MODELING I/O SIMULTANEOUS SWITCHING NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13449009
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
Generating Capacitance Look-up Tables for Wiring Patterns in the Presence of Metal Fills
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13449139
|
Filing Dt:
|
04/17/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13449378
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13449419
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13449433
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
ETCH STOP LAYER FORMATION IN METAL GATE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13449708
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
STRUCTURE FOR REMOVABLE PROCESSOR SOCKET
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13449732
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13449741
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
Process of Multiple Exposures With Spin Castable Films
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13449885
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
MULTI-MODAL DATA ANALYSIS FOR DEFECT IDENTIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13450004
|
Filing Dt:
|
04/18/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Design Structure for High Density Stable Static Random Access Memory
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13451054
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13451087
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13451141
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
FARBRICATION OF A LOCALIZED THICK BOX WITH PLANAR OXIDE/SOI INTERFACE ON BULK SILICON SUBSTRATE FOR SILICON PHOTONICS INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13451382
|
Filing Dt:
|
04/19/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13451806
|
Filing Dt:
|
04/20/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
BICMOS DEVICES ON ETSOI
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13451902
|
Filing Dt:
|
04/20/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13452335
|
Filing Dt:
|
04/20/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13452454
|
Filing Dt:
|
04/20/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
METHOD AND SYSTEM FOR FEATURE FUNCTION AWARE PRIORITY PRINTING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2016
|
Application #:
|
13452857
|
Filing Dt:
|
04/21/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
NANOPORE CAPTURE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13453027
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
09/26/2013
| | | | |
Title:
|
FLEXIBLE FIBER TO WAFER INTERFACE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13453131
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING GRADED GATE STACK, RELATED METHOD AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
13453165
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
13453215
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/09/2012
| | | | |
Title:
|
CMOS STRUCTURE INCLUDING NON-PLANAR HYBRID ORIENTATION SUBSTRATE WITH PLANAR GATE ELECTRODES & METHOD FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13453262
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
FRACTURING CONTINUOUS PHOTOLITHOGRAPHY MASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
13453426
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
13453508
|
Filing Dt:
|
04/23/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13454172
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
11/01/2012
| | | | |
Title:
|
ESD PROTECTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
13454220
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
Automated Fault and Recovery System
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13454518
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
BODY CONTACTED HYBRID SURFACE SEMICONDUCTOR-ON-INSULATOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2015
|
Application #:
|
13454635
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13454709
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13454723
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
13454795
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
ENABLING STATISTICAL TESTING USING DETERMINISTIC MULTI-CORNER TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
|
Application #:
|
13454935
|
Filing Dt:
|
04/24/2012
|
Publication #:
|
|
Pub Dt:
|
10/24/2013
| | | | |
Title:
|
COMBINED SOFT DETECTION AND SOFT DECODING IN TAPE DRIVE STORAGE CHANNELS.
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
13455174
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13455177
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
13455181
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
MODELING THE TOTAL PARASITIC RESISTANCES OF THE SOURCE/DRAIN REGIONS OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13455394
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
IMPLEMENTING SUPPLY AND SOURCE WRITE ASSIST FOR SRAM ARRAYS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13455505
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
13455507
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
AVALANCHE IMPACT IONIZATION AMPLIFICATION DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13455653
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
DIODE-TRIGGERED SILICON CONTROLLED RECTIFIER WITH AN INTEGRATED DIODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2013
|
Application #:
|
13455725
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13455732
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
DEVICE STRUCTURES COMPATIBLE WITH FIN-TYPE FIELD-EFFECT TRANSISTOR TECHNOLOGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13455789
|
Filing Dt:
|
04/25/2012
|
Title:
|
METHOD AND SYSTEM FOR OPTIMAL COUNTEREXAMPLE-GUIDED PROOF-BASED ABSTRACTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
13455839
|
Filing Dt:
|
04/25/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
CONSTRUCTING INDUCTIVE COUNTEREXAMPLES IN A MULTI-ALGORITHM VERIFICATION FRAMEWORK
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13456282
|
Filing Dt:
|
04/26/2012
|
Publication #:
|
|
Pub Dt:
|
08/16/2012
| | | | |
Title:
|
Device component forming method with a trim step prior to sidewall image transfer (SIT) processing
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13456456
|
Filing Dt:
|
04/26/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13456591
|
Filing Dt:
|
04/26/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
SWAPPING PORTS TO CHANGE THE TIMING WINDOW OVERLAP OF ADJACENT NETS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13456596
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Filing Dt:
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04/26/2012
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Publication #:
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Pub Dt:
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12/27/2012
| | | | |
Title:
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ACCURATE DEPOSITION OF NANO-OBJECTS ON A SURFACE
|
|
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Patent #:
|
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Issue Dt:
|
12/23/2014
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Application #:
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13456745
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Filing Dt:
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04/26/2012
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Publication #:
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Pub Dt:
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10/25/2012
| | | | |
Title:
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Generating Constraints in a Class Model
|
|
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Patent #:
|
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Issue Dt:
|
11/26/2013
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Application #:
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13456921
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Filing Dt:
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04/26/2012
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Publication #:
|
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Pub Dt:
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10/31/2013
| | | | |
Title:
|
FINFET DIODE WITH INCREASED JUNCTION AREA
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2014
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Application #:
|
13457529
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Filing Dt:
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04/27/2012
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Publication #:
|
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Pub Dt:
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10/31/2013
| | | | |
Title:
|
FINFET WITH ENHANCED EMBEDDED STRESSOR
|
|
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Patent #:
|
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Issue Dt:
|
09/17/2013
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Application #:
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13457551
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Filing Dt:
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04/27/2012
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Publication #:
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Pub Dt:
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11/08/2012
| | | | |
Title:
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GENERATING PHYSICAL DESIGNS FOR ELECTRONIC CIRCUIT BOARDS
|
|
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Patent #:
|
|
Issue Dt:
|
02/03/2015
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Application #:
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13457601
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Filing Dt:
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04/27/2012
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Publication #:
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Pub Dt:
|
10/31/2013
| | | | |
Title:
|
METAL-INSULATOR-METAL (MIM) CAPACITOR WITH DEEP TRENCH (DT) STRUCTURE AND METHOD IN A SILICON-ON-INSULATOR (SOI)
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2015
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Application #:
|
13457692
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Filing Dt:
|
04/27/2012
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Publication #:
|
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Pub Dt:
|
10/31/2013
| | | | |
Title:
|
THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
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Application #:
|
13457722
|
Filing Dt:
|
04/27/2012
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Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
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Application #:
|
13457735
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Filing Dt:
|
04/27/2012
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Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
PHOTORESIST COMPOSITION CONTAINING A PROTECTED HYDROXYL GROUP FOR NEGATIVE DEVELOPMENT AND PATTERN FORMING METHOD USING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
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Application #:
|
13457748
|
Filing Dt:
|
04/27/2012
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Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
NARROW BODY FIELD-EFFECT TRANSISTOR STRUCTURES WITH FREE-STANDING EXTENSION REGIONS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13457847
|
Filing Dt:
|
04/27/2012
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Publication #:
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|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13457932
|
Filing Dt:
|
04/27/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13458534
|
Filing Dt:
|
04/27/2012
|
Publication #:
|
|
Pub Dt:
|
10/25/2012
| | | | |
Title:
|
ENHANCING REDUNDANCY REMOVAL WITH EARLY MERGING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2016
|
Application #:
|
13459460
|
Filing Dt:
|
04/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
Assembly of Electronic and Optical Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2014
|
Application #:
|
13459785
|
Filing Dt:
|
04/30/2012
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
Title:
|
ELONGATED VIA STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
13459863
|
Filing Dt:
|
04/30/2012
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
Title:
|
MATCHING SYSTEMS WITH POWER AND THERMAL DOMAINS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13460369
|
Filing Dt:
|
04/30/2012
|
Publication #:
|
|
Pub Dt:
|
06/20/2013
| | | | |
Title:
|
GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/2014
|
Application #:
|
13461912
|
Filing Dt:
|
05/02/2012
|
Publication #:
|
|
Pub Dt:
|
11/07/2013
| | | | |
Title:
|
STRUCTURE FOR MONITORING STRESS INDUCED FAILURES IN INTERLEVEL DIELECTRIC LAYERS OF SOLDER BUMP INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13461935
|
Filing Dt:
|
05/02/2012
|
Publication #:
|
|
Pub Dt:
|
11/07/2013
| | | | |
Title:
|
DOPED CORE TRIGATE FET STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2014
|
Application #:
|
13461960
|
Filing Dt:
|
05/02/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
PHOTORESIST COMPOSITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2016
|
Application #:
|
13462964
|
Filing Dt:
|
05/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROBING A WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13463283
|
Filing Dt:
|
05/03/2012
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
METHOD AND STRUCTURE FOR WORK FUNCTION ENGINEERING IN TRANSISTORS INCLUDING A HIGH DIELECTRIC CONSTANT GATE INSULATOR AND METAL GATE (HKMG)
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13463402
|
Filing Dt:
|
05/03/2012
|
Publication #:
|
|
Pub Dt:
|
11/07/2013
| | | | |
Title:
|
SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13463857
|
Filing Dt:
|
05/04/2012
|
Publication #:
|
|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
ESTIMATING CLOCK SKEW
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
13463879
|
Filing Dt:
|
05/04/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13464131
|
Filing Dt:
|
05/04/2012
|
Publication #:
|
|
Pub Dt:
|
11/07/2013
| | | | |
Title:
|
CURRENT LEAKAGE IN RC ESD CLAMPS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13464267
|
Filing Dt:
|
05/04/2012
|
Publication #:
|
|
Pub Dt:
|
10/03/2013
| | | | |
Title:
|
LOW EXTENSION DOSE IMPLANTS IN SRAM FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2013
|
Application #:
|
13465115
|
Filing Dt:
|
05/07/2012
|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
Title:
|
TRANSACTIONAL MEMORY PREEMPTION MECHANISM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13465159
|
Filing Dt:
|
05/07/2012
|
Publication #:
|
|
Pub Dt:
|
11/07/2013
| | | | |
Title:
|
FORMING CMOS WITH CLOSE PROXIMITY STRESSORS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13466973
|
Filing Dt:
|
05/08/2012
|
Publication #:
|
|
Pub Dt:
|
05/23/2013
| | | | |
Title:
|
REDUCED LEAKAGE BANKED WORDLINE HEADER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
13467126
|
Filing Dt:
|
05/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
NANOWIRE MESH FET WITH MULTIPLE THRESHOLD VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
13467191
|
Filing Dt:
|
05/09/2012
|
Title:
|
MITIGATION OF MASK DEFECTS BY PATTERN SHIFTING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
13467385
|
Filing Dt:
|
05/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
VERTICAL HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/2013
|
Application #:
|
13467425
|
Filing Dt:
|
05/09/2012
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
Title:
|
METHOD AND SYSTEM FOR OPTIMAL DIAMETER BOUNDING OF DESIGNS WITH COMPLEX FEED-FORWARD COMPONENTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13467537
|
Filing Dt:
|
05/09/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
METHOD FOR IMPARTING A CONTROLLED AMOUNT OF STRESS IN SEMICONDUCTOR DEVICES FOR FABRICATING THIN FLEXIBLE CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13468223
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13468232
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
09/13/2012
| | | | |
Title:
|
METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
13468268
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
Title:
|
INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL)
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
13468270
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
Structure and Method for Manufacturing Asymmetric Devices
|
|
|
Patent #:
|
|
Issue Dt:
|
12/24/2013
|
Application #:
|
13468281
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13468307
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
09/06/2012
| | | | |
Title:
|
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
13468576
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
11/14/2013
| | | | |
Title:
|
PRINTED TRANSISTOR AND FABRICATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/05/2014
|
Application #:
|
13468609
|
Filing Dt:
|
05/10/2012
|
Publication #:
|
|
Pub Dt:
|
08/30/2012
| | | | |
Title:
|
THROUGH SUBSTRATE VIAS
|
|