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Patent #:
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|
Issue Dt:
|
08/04/2015
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Application #:
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13490740
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Filing Dt:
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06/07/2012
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|
Publication #:
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|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE
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Patent #:
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|
Issue Dt:
|
12/23/2014
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Application #:
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13491036
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Filing Dt:
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06/07/2012
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|
Publication #:
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Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRAIN AND METHODS OF MANUFACTURING AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
|
02/09/2016
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Application #:
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13491093
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Filing Dt:
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06/07/2012
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|
Publication #:
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Pub Dt:
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09/27/2012
| | | | |
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Title:
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REMOVING MATERIAL FROM DEFECTIVE OPENING IN GLASS MOLD
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Patent #:
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Issue Dt:
|
05/31/2016
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Application #:
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13491210
|
Filing Dt:
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06/07/2012
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|
Publication #:
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Pub Dt:
|
12/12/2013
| | | | |
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Title:
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UNIVERSAL JITTER METER AND PHASE NOISE MEASUREMENT
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Patent #:
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|
Issue Dt:
|
03/25/2014
|
Application #:
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13491857
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Filing Dt:
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06/08/2012
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|
Publication #:
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Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13491873
|
Filing Dt:
|
06/08/2012
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|
Publication #:
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Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
Plating Stub Resonance Shift with Filter Stub Design Methodology
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|
Patent #:
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|
Issue Dt:
|
09/19/2017
|
Application #:
|
13492108
|
Filing Dt:
|
06/08/2012
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|
Publication #:
|
|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
METHOD OF FABRICATING A FINFET HAVING A GATE STRUCTURE DISPOSED AT LEAST PARTIALLY AT A BEND REGION OF THE SEMICONDUCTOR FIN.
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13492399
|
Filing Dt:
|
06/08/2012
|
|
Publication #:
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|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
IDENTIFICATION OF MISTIMED FORCING OF VALUES IN DESIGN SIMULATION
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|
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|
Patent #:
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|
Issue Dt:
|
09/24/2013
|
Application #:
|
13492964
|
Filing Dt:
|
06/11/2012
|
|
Publication #:
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|
Pub Dt:
|
09/27/2012
| | | | |
|
Title:
|
COMPUTER IMPLEMENTED DESIGN OF DEVICE FOR ELECTRO-OPTICAL
MODULATION OF LIGHT INCIDENT UPON DEVICE
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|
|
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|
Patent #:
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|
Issue Dt:
|
11/17/2015
|
Application #:
|
13494047
|
Filing Dt:
|
06/12/2012
|
|
Publication #:
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|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
Optimizing Heat Transfer in 3-D Chip-Stacks
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13494312
|
Filing Dt:
|
06/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13494327
|
Filing Dt:
|
06/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
LAYERED STRUCTURE WITH FUSE
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|
|
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|
Patent #:
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|
Issue Dt:
|
01/07/2014
|
Application #:
|
13494635
|
Filing Dt:
|
06/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13494667
|
Filing Dt:
|
06/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
THREE DIMENSIONAL FLIP CHIP SYSTEM AND METHOD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
13495081
|
Filing Dt:
|
06/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13495148
|
Filing Dt:
|
06/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
|
Title:
|
METHODS FOR FABRICATING SEMICONDUCTOR WIRE-ARRAY VARACTOR STRUCTURES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
13495195
|
Filing Dt:
|
06/13/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13517799
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
COMPRESSED GAS CYLINDER CABINET WITH REGULATED EXHAUST CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13523048
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13523179
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
PLATING BATHS AND METHODS FOR ELECTROPLATING SELENIUM AND SELENIUM ALLOYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2016
|
Application #:
|
13523182
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
GRAPHENE BASED STRUCTURES AND METHODS FOR BROADBAND ELECTROMAGNETIC RADIATION ABSORPTION AT THE MICROWAVE AND TERAHERTZ FREQUENCIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
13523331
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/03/2013
| | | | |
|
Title:
|
ANALOG-DIGITAL CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13523624
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
BITLINE DELETION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13523633
|
Filing Dt:
|
06/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
BITLINE DELETION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13523971
|
Filing Dt:
|
06/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
BAD WORDLINE/ARRAY DETECTION IN MEMORY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13523983
|
Filing Dt:
|
06/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2012
| | | | |
|
Title:
|
FACILITATING DEBUGGING A HARDWARE DESIGN
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13524131
|
Filing Dt:
|
06/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
|
Title:
|
FIN ISOLATION FOR MULTIGATE TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
13524298
|
Filing Dt:
|
06/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13524576
|
Filing Dt:
|
06/15/2012
|
|
Title:
|
REPLACEMENT METAL GATE PROCESSING WITH REDUCED INTERLEVEL DIELECTRIC LAYER ETCH RATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2013
|
Application #:
|
13525479
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS)
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13525650
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13525996
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/04/2012
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR GENERATING PROFILE OF SOLUTIONS TRADING OFF NUMBER OF ACTIVITIES UTILIZED AND OBJECTIVE VALUE FOR BILINEAR INTEGER OPTIMIZATION MODELS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2013
|
Application #:
|
13526139
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/21/2013
| | | | |
|
Title:
|
SEMICONDUCTOR ACTIVE MATRIX ON BURIED INSULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13526152
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR HIERARCHICAL WAFER QUALITY PREDICTIVE MODELING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13526153
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/20/2014
| | | | |
|
Title:
|
Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13526252
|
Filing Dt:
|
06/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2014
|
Application #:
|
13526585
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
11/28/2013
| | | | |
|
Title:
|
DRIFT-INSENSITIVE OR INVARIANT MATERIAL FOR PHASE CHANGE MEMORY
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13526840
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
EPITAXIAL GROWTH OF SMOOTH AND HIGHLY STRAINED GERMANIUM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13526915
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
RESISTOR-2 RESISTOR (R-2R) DIGITAL-TO-ANALOG CONVERTER WITH RESISTOR NETWORK REVERSAL
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13527063
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/12/2013
| | | | |
|
Title:
|
PREVENTING FULLY SILICIDED FORMATION IN HIGH-K METAL GATE PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13527131
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
THROUGH SILICON VIA WAFER AND METHODS OF MANUFACTURING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13527280
|
Filing Dt:
|
06/19/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
COPPER FEATURE DESIGN FOR WARPAGE CONTROL OF SUBSTRATES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13527828
|
Filing Dt:
|
06/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
|
Title:
|
REPLACEMENT METAL GATE PROCESSING WITH REDUCED INTERLEVEL DIELECTRIC LAYER ETCH RATE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13527961
|
Filing Dt:
|
06/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13528947
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
PROBE-ON-SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13529334
|
Filing Dt:
|
06/21/2012
|
|
Title:
|
NANOWIRE FET AND FINFET
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13529360
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
DOUBLE LAYER INTERLEAVED P-N DIODE MODULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
13529389
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
13529557
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
13529558
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13529625
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13530004
|
Filing Dt:
|
06/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2013
| | | | |
|
Title:
|
ORGANIC SOLVENT DEVELOPABLE PHOTORESIST COMPOSITION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2014
|
Application #:
|
13530519
|
Filing Dt:
|
06/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/18/2012
| | | | |
|
Title:
|
LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13530549
|
Filing Dt:
|
06/22/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2012
| | | | |
|
Title:
|
NANOPILLAR DECOUPLING CAPACITOR
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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13530605
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Filing Dt:
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06/22/2012
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Title:
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METHOD OF LARGE-AREA CIRCUIT LAYOUT RECOGNITION
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13530637
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Filing Dt:
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06/22/2012
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Title:
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RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13530725
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Filing Dt:
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06/22/2012
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Publication #:
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Pub Dt:
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12/19/2013
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Title:
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GRAPHENE BASED STRUCTURES AND METHODS FOR BROADBAND ELECTROMAGNETIC RADIATION ABSORPTION AT THE MICROWAVE AND TERAHERTZ FREQUENCIES
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Patent #:
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Issue Dt:
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07/15/2014
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Application #:
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13530887
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Filing Dt:
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06/22/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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INTEGRATION OF FIN-BASED DEVICES AND ETSOI DEVICES
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13530889
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Filing Dt:
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06/22/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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PHASE CHANGE MEMORY CYCLE TIMER AND METHOD
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13531053
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Filing Dt:
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06/22/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13531175
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Filing Dt:
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06/22/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13531518
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Filing Dt:
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06/23/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13531654
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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12/26/2013
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Title:
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SHALLOW TRENCH ISOLATION STRUCTURES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13531703
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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Gradient-Based Search Mechanism for Optimizing Photolithograph Masks
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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13531733
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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GRADIENT-BASED SEARCH MECHANISM FOR OPTIMIZING PHOTOLITHOGRAPH MASKS
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13531754
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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10/11/2012
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Title:
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Gradient-Based Search Mechanism for Optimizing Photolithograph Masks
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13531778
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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GRADIENT-BASED SEARCH MECHANISM FOR OPTIMIZING PHOTOLITHOGRAPH MASKS
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13531780
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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12/26/2013
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Title:
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SHALLOW TRENCH ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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13531811
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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GRADIENT-BASED SEARCH MECHANISM FOR OPTIMIZING PHOTOLITHOGRAPH MASKS
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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13531831
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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GRADIENT-BASED SEARCH MECHANISM FOR OPTIMIZING PHOTOLITHOGRAPH MASKS
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Patent #:
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Issue Dt:
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05/14/2013
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Application #:
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13532204
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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RUNTIME DYNAMIC PERFORMANCE SKEW ELIMINATION
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13532323
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Filing Dt:
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06/25/2012
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Title:
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BIPOLAR JUNCTION TRANSISTOR WITH EPITAXIAL CONTACTS
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Patent #:
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Issue Dt:
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01/05/2016
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Application #:
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13532716
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Filing Dt:
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06/25/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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METHODS FOR FABRICATING MAGNETIC TRANSDUCERS USING POST-DEPOSITION TILTING
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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13532991
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Filing Dt:
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06/26/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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COUPLING PIEZOELECTRIC MATERIAL GENERATED STRESSES TO DEVICES FORMED IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13533099
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Filing Dt:
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06/26/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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METHOD OF FABRICATING ISOLATED CAPACITORS AND STRUCTURE THEREOF
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13533182
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Filing Dt:
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06/26/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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FORMATION OF ALPHA PARTICLE SHIELDS IN CHIP PACKAGING
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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13533484
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Filing Dt:
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06/26/2012
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Publication #:
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Pub Dt:
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12/26/2013
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Title:
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IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13533499
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Filing Dt:
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06/26/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13534012
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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SEMICONDUCTOR DEVICES HAVING DIFFERENT GATE OXIDE THICKNESSES
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13534037
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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13534067
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Filing Dt:
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06/27/2012
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Title:
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THREE DIMENSIONAL INTEGRATED CIRCUIT INTEGRATION USING ALIGNMENT VIA/DIELECTRIC BONDING FIRST AND THROUGH VIA FORMATION LAST
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13534082
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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DAMASCENE METHOD OF FORMING A SEMICONDUCTOR STRUCTURE AND A SEMICONDUCTOR STRUCTURE WITH MULTIPLE FIN-SHAPED CHANNEL REGIONS HAVING DIFFERENT WIDTHS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13534241
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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08/15/2013
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Title:
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EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13534350
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13534355
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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ON-CHIP CAPACITORS WITH A VARIABLE CAPACITANCE FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13534407
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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13534462
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13534522
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13534596
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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08/15/2013
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Title:
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EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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13534855
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13534890
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13535393
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/18/2012
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Title:
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ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13535394
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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METHOD OF FORMING A FIELD EFFECT TRANSISTOR HAVING A GATE STRUCTURE TRAVERSING CHANNEL REGION COMPRISING A FIRST SECTION FORMED ON A CENTRAL PORTION AND A SECOND SECTION FORMED ABOVE THE FIRST SECTION AND EXTENDING ONTO THE ISOLATION REGION.
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13535412
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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06/04/2013
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Application #:
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13535466
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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13535528
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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11/01/2012
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Title:
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SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13535660
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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Enhanced Modularity in Heterogeneous 3D Stacks
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Patent #:
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Issue Dt:
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06/21/2016
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Application #:
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13535675
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/25/2012
| | | | |
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Title:
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ENHANCED MODULARITY IN HETEROGENEOUS 3D STACKS
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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13535676
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS
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Patent #:
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Issue Dt:
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07/12/2016
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Application #:
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13535694
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Filing Dt:
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06/28/2012
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Publication #:
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Pub Dt:
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10/25/2012
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Title:
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Enhanced Modularity in Heterogeneous 3D Stacks
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