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Patent #:
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|
Issue Dt:
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08/18/2015
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Application #:
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13646120
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Filing Dt:
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10/05/2012
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Publication #:
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|
Pub Dt:
|
04/10/2014
| | | | |
Title:
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Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack For Dopant Source and Passivation
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13647538
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Filing Dt:
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10/09/2012
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Publication #:
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|
Pub Dt:
|
02/07/2013
| | | | |
Title:
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METHODS FOR NORMALIZING STRAIN IN SEMICONDCUTOR DEVICES AND STRAIN NORMALIZED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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13647547
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Filing Dt:
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10/09/2012
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Publication #:
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Pub Dt:
|
03/27/2014
| | | | |
Title:
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METHOD FOR RADIATION MONITORING
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Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13647862
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Filing Dt:
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10/09/2012
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Publication #:
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Pub Dt:
|
04/10/2014
| | | | |
Title:
|
COMPRESSIVELY STRAINED SOI SUBSTRATE
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Patent #:
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Issue Dt:
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12/01/2015
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Application #:
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13648292
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Filing Dt:
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10/10/2012
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Publication #:
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|
Pub Dt:
|
04/10/2014
| | | | |
Title:
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CHIP AUTHENTICATION USING MULTI-DOMAIN INTRINSIC IDENTIFIERS
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Patent #:
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Issue Dt:
|
12/09/2014
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Application #:
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13648321
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Filing Dt:
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10/10/2012
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Publication #:
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Pub Dt:
|
04/10/2014
| | | | |
Title:
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SINGLE FIN CUT EMPLOYING ANGLED PROCESSING METHODS
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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13648555
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Filing Dt:
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10/10/2012
|
Publication #:
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|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA
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Patent #:
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Issue Dt:
|
07/16/2013
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Application #:
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13648799
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Filing Dt:
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10/10/2012
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Publication #:
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|
Pub Dt:
|
02/07/2013
| | | | |
Title:
|
SELF CALIBRATED, BROADBAND, TUNABLE, ACTIVE OSCILLATOR WITH UNITY GAIN CELLS FOR MULTI-STANDARD AND/OR MULTIBAND CHANNEL SELECTION
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13649284
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Filing Dt:
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10/11/2012
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Publication #:
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Pub Dt:
|
06/20/2013
| | | | |
Title:
|
FINFET WITH VERTICAL SILICIDE STRUCTURE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13649364
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Filing Dt:
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10/11/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
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ION IMPLANTATION TUNING TO ACHIEVE SIMULTANEOUS MULTIPLE IMPLANT ENERGIES
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Patent #:
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Issue Dt:
|
05/12/2015
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Application #:
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13649458
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Filing Dt:
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10/11/2012
|
Publication #:
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Pub Dt:
|
04/17/2014
| | | | |
Title:
|
ADVANCED HANDLER WAFER BONDING AND DEBONDING
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13649573
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Filing Dt:
|
10/11/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
ADVANCED HANDLER WAFER BONDING AND DEBONDING
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|
Patent #:
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|
Issue Dt:
|
02/21/2017
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Application #:
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13649699
|
Filing Dt:
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10/11/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
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METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS WAFER
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|
Patent #:
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Issue Dt:
|
09/30/2014
|
Application #:
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13649760
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Filing Dt:
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10/11/2012
|
Publication #:
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|
Pub Dt:
|
02/07/2013
| | | | |
Title:
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THERMAL EXPANSION CONTROL EMPLOYING PLATELET FILLERS
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|
Patent #:
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Issue Dt:
|
10/21/2014
|
Application #:
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13649769
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Filing Dt:
|
10/11/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES
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Patent #:
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Issue Dt:
|
03/03/2015
|
Application #:
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13650176
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Filing Dt:
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10/12/2012
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Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
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VERTICAL SOURCE/DRAIN JUNCTIONS FOR A FINFET INCLUDING A PLURALITY OF FINS
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|
Patent #:
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Issue Dt:
|
03/01/2016
|
Application #:
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13650591
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Filing Dt:
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10/12/2012
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Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
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HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
|
11/18/2014
|
Application #:
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13651874
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Filing Dt:
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10/15/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
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|
Patent #:
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|
Issue Dt:
|
10/01/2013
|
Application #:
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13651918
|
Filing Dt:
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10/15/2012
|
Publication #:
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|
Pub Dt:
|
02/14/2013
| | | | |
Title:
|
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
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|
Patent #:
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Issue Dt:
|
11/03/2015
|
Application #:
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13651974
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Filing Dt:
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10/15/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
Method and System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
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|
Patent #:
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Issue Dt:
|
10/28/2014
|
Application #:
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13652521
|
Filing Dt:
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10/16/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
EMBEDDED SOURCE/DRAINS WITH EPITAXIAL OXIDE UNDERLAYER
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|
Patent #:
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|
Issue Dt:
|
01/06/2015
|
Application #:
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13652623
|
Filing Dt:
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10/16/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
Method Of Fabricating MEMS Transistors On Far Back End Of Line
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|
Patent #:
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|
Issue Dt:
|
05/14/2013
|
Application #:
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13652804
|
Filing Dt:
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10/16/2012
|
Publication #:
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|
Pub Dt:
|
02/28/2013
| | | | |
Title:
|
NANOPILLAR E-FUSE STRUCTURE AND PROCESS
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|
Patent #:
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Issue Dt:
|
12/09/2014
|
Application #:
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13653291
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Filing Dt:
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10/16/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
BLOCK-INTERLEAVED AND ERROR CORRECTION CODE (ECC)-ENCODED SUB DATA SET (SDS) FORMAT
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13653658
|
Filing Dt:
|
10/17/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
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REPLACEMENT GATE WITH AN INNER DIELECTRIC SPACER
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|
Patent #:
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|
Issue Dt:
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07/23/2013
|
Application #:
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13653665
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Filing Dt:
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10/17/2012
|
Publication #:
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|
Pub Dt:
|
05/09/2013
| | | | |
Title:
|
METAL ALLOY CAP INTEGRATION
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|
Patent #:
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|
Issue Dt:
|
09/16/2014
|
Application #:
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13653679
|
Filing Dt:
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10/17/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13653699
|
Filing Dt:
|
10/17/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
FET Devices with Oxide Spacers
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|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
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13653996
|
Filing Dt:
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10/17/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
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REACTIVE MATERIAL FOR INTEGRATED CIRCUIT TAMPER DETECTION AND RESPONSE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13654010
|
Filing Dt:
|
10/17/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS
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|
Patent #:
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|
Issue Dt:
|
10/14/2014
|
Application #:
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13654040
|
Filing Dt:
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10/17/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
MULTI-DOPED SILICON ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
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13654987
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Filing Dt:
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10/18/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
STRUCTURE AND METHOD FOR FORMING A LOW GATE RESISTANCE HIGH-K METAL GATE TRANSISTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
04/14/2015
|
Application #:
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13655003
|
Filing Dt:
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10/18/2012
|
Publication #:
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Pub Dt:
|
04/24/2014
| | | | |
Title:
|
SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE
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|
Patent #:
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|
Issue Dt:
|
09/03/2013
|
Application #:
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13655426
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Filing Dt:
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10/18/2012
|
Title:
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FORMING AN ARRAY OF METAL BALLS OR SHAPES ON A SUBSTRATE
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|
Patent #:
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|
Issue Dt:
|
05/26/2015
|
Application #:
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13655520
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Filing Dt:
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10/19/2012
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Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
Title:
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USER-COORDINATED RESOURCE RECOVERY
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|
Patent #:
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Issue Dt:
|
10/28/2014
|
Application #:
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13655599
|
Filing Dt:
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10/19/2012
|
Publication #:
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Pub Dt:
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02/21/2013
| | | | |
Title:
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REDUCTION OF PORE FILL MATERIAL DEWETTING
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Patent #:
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Issue Dt:
|
03/25/2014
|
Application #:
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13655610
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Filing Dt:
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10/19/2012
|
Publication #:
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Pub Dt:
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02/21/2013
| | | | |
Title:
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RAISED SOURCE/DRAIN FIELD EFFECT TRANSISTOR
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|
Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
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13655980
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Filing Dt:
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10/19/2012
|
Publication #:
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|
Pub Dt:
|
02/21/2013
| | | | |
Title:
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VISUALIZATION INTERFACE OF CONTINUOUS WAVEFORM MULTI-SPEAKER IDENTIFICATION
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|
Patent #:
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|
Issue Dt:
|
09/30/2014
|
Application #:
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13656396
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Filing Dt:
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10/19/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
METHOD AND SYSTEM FOR PERFORMING INVARIANT-GUIDED ABSTRACTION OF A LOGIC DESIGN
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Patent #:
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Issue Dt:
|
11/25/2014
|
Application #:
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13656819
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Filing Dt:
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10/22/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
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FIELD EFFECT TRANSISTOR HAVING PHASE TRANSITION MATERIAL INCORPORATED INTO ONE OR MORE COMPONENTS FOR REDUCED LEAKAGE CURRENT
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Patent #:
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Issue Dt:
|
09/30/2014
|
Application #:
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13656829
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Filing Dt:
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10/22/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
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MEMORY SYSTEM INCORPORATING A CIRCUIT TO GENERATE A DELAY SIGNAL AND AN ASSOCIATED METHOD OF OPERATING A MEMORY SYSTEM
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|
Patent #:
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|
Issue Dt:
|
03/29/2016
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Application #:
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13657058
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Filing Dt:
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10/22/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
|
MEMORY SYSTEM CONNECTOR
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13658007
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Filing Dt:
|
10/23/2012
|
Publication #:
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|
Pub Dt:
|
03/27/2014
| | | | |
Title:
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STACKED NANOWIRE FIELD EFFECT TRANSISTOR
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Patent #:
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|
Issue Dt:
|
04/29/2014
|
Application #:
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13658148
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Filing Dt:
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10/23/2012
|
Publication #:
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Pub Dt:
|
02/21/2013
| | | | |
Title:
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CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS
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|
Patent #:
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|
Issue Dt:
|
08/05/2014
|
Application #:
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13658226
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Filing Dt:
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10/23/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
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IMPLEMENTING SDRAM HAVING NO RAS TO CAS DELAY IN WRITE OPERATION
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|
Patent #:
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|
Issue Dt:
|
01/28/2014
|
Application #:
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13658733
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Filing Dt:
|
10/23/2012
|
Title:
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HIGH ASPECT RATIO SAMPLE HOLDER
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|
Patent #:
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|
Issue Dt:
|
08/09/2016
|
Application #:
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13658856
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Filing Dt:
|
10/24/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
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WAFER BONDING FOR 3D DEVICE PACKAGING FABRICATION
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|
Patent #:
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|
Issue Dt:
|
01/07/2014
|
Application #:
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13658861
|
Filing Dt:
|
10/24/2012
|
Publication #:
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|
Pub Dt:
|
02/21/2013
| | | | |
Title:
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SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13659076
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Filing Dt:
|
10/24/2012
|
Publication #:
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Pub Dt:
|
03/27/2014
| | | | |
Title:
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MULTI-GATE FIELD EFFECT TRANSISTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
03/25/2014
|
Application #:
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13659236
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Filing Dt:
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10/24/2012
|
Publication #:
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Pub Dt:
|
04/11/2013
| | | | |
Title:
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Polarization Monitoring Reticle Design for High Numerical Aperture Lithography Systems
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Patent #:
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|
Issue Dt:
|
07/29/2014
|
Application #:
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13659281
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Filing Dt:
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10/24/2012
|
Publication #:
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|
Pub Dt:
|
03/27/2014
| | | | |
Title:
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ZINC OXIDE-CONTAINING TRANSPARENT CONDUCTIVE ELECTRODE
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|
Patent #:
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|
Issue Dt:
|
01/19/2016
|
Application #:
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13659292
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Filing Dt:
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10/24/2012
|
Publication #:
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Pub Dt:
|
04/24/2014
| | | | |
Title:
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BULK FINFET WELL CONTACTS WITH FIN PATTERN UNIFORMITY
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|
Patent #:
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|
Issue Dt:
|
11/03/2015
|
Application #:
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13659318
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Filing Dt:
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10/24/2012
|
Publication #:
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|
Pub Dt:
|
04/24/2014
| | | | |
Title:
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SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH
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|
Patent #:
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|
Issue Dt:
|
09/09/2014
|
Application #:
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13660206
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Filing Dt:
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10/25/2012
|
Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
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METHOD AND STRUCTURE FOR BODY CONTACTED FET WITH REDUCED BODY RESISTANCE AND SOURCE TO DRAIN CONTACT LEAKAGE
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13660229
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Filing Dt:
|
10/25/2012
|
Publication #:
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Pub Dt:
|
02/28/2013
| | | | |
Title:
|
Techniques for Impeding Reverse Engineering
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|
Patent #:
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|
Issue Dt:
|
01/27/2015
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Application #:
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13660497
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Filing Dt:
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10/25/2012
|
Publication #:
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Pub Dt:
|
04/03/2014
| | | | |
Title:
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TRANSISTOR FORMATION USING COLD WELDING
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|
Patent #:
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|
Issue Dt:
|
06/03/2014
|
Application #:
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13660604
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Filing Dt:
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10/25/2012
|
Publication #:
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|
Pub Dt:
|
03/27/2014
| | | | |
Title:
|
TRANSPARENT CONDUCTIVE ELECTRODE STACK CONTAINING CARBON-CONTAINING MATERIAL
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|
Patent #:
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|
Issue Dt:
|
06/17/2014
|
Application #:
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13661062
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Filing Dt:
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10/26/2012
|
Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
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PROGRAMMABLE DUTY CYCLE SETTER EMPLOYING TIME TO VOLTAGE DOMAIN REFERENCED PULSE CREATION
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Patent #:
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|
Issue Dt:
|
12/30/2014
|
Application #:
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13661359
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Filing Dt:
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10/26/2012
|
Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
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ISOLATION SCHEME FOR BIPOLAR TRANSISTORS IN BICMOS TECHNOLOGY
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Patent #:
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Issue Dt:
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04/21/2015
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Application #:
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13661683
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Filing Dt:
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10/26/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13663511
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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HIGH RESPONSIVITY DEVICE FOR THERMAL SENSING IN A TERAHERTZ RADIATION DETECTOR
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13663768
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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FEED-FORWARD EQUALIZATION IN A RECEIVER
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13663811
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/02/2013
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Title:
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PROTECTING A THERMAL SENSITIVE COMPONENT IN A THERMAL PROCESS
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13663816
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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AUTOMATIC WAFER DATA SAMPLE PLANNING AND REVIEW
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13663836
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Filing Dt:
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10/30/2012
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Publication #:
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Pub Dt:
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02/28/2013
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Title:
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METHODS OF FORMING STRUCTURES WITH A FOCUSED ION BEAM FOR USE IN ATOMIC FORCE PROBING AND STRUCTURES FOR USE IN ATOMIC FORCE PROBING
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13664744
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING REPLACEMENT METAL GATE PROCESS INCORPORATING A CONDUCTIVE DUMMY GATE LAYER
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13664784
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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SEMICONDUCTOR STRUCTURE INCORPORATING A CONTACT SIDEWALL SPACER WITH A SELF-ALIGNED AIRGAP AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13664812
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP
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Patent #:
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Issue Dt:
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04/07/2015
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Application #:
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13664850
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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LOCAL INTERCONNECTS FOR FIELD EFFECT TRANSISTOR DEVICES
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13664869
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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SELF-ALIGNED CONTACT STRUCTURE FOR REPLACEMENT METAL GATE
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13664873
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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BULK FINFET WITH PUNCHTHROUGH STOPPER REGION AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13664955
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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INSULATIVE CAP FOR BORDERLESS SELF-ALIGNING CONTACT IN SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13665140
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13665276
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13665315
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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PARASITIC EXTRACTION IN AN INTEGRATED CIRCUIT WITH MULTI-PATTERNING REQUIREMENTS
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Patent #:
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Issue Dt:
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12/24/2013
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Application #:
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13665334
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Filing Dt:
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10/31/2012
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Title:
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Techniques for Fabricating Janus MEMS Transistors
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13665388
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13665466
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Filing Dt:
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10/31/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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13666031
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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DUAL GATE FINFET DEVICES
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Patent #:
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Issue Dt:
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03/24/2015
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Application #:
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13666214
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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03/07/2013
| | | | |
Title:
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TRANSISTORS HAVING STRESSED CHANNEL REGIONS AND METHODS OF FORMING TRANSISTORS HAVING STRESSED CHANNEL REGIONS
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13666386
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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05/01/2014
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Title:
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FIN FIELD EFFECT TRANSISTORS HAVING A NITRIDE CONTAINING SPACER TO REDUCE LATERAL GROWTH OF EPITAXIALLY DEPOSITED SEMICONDUCTOR MATERIALS
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Patent #:
|
|
Issue Dt:
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01/14/2014
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Application #:
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13666484
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Filing Dt:
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11/01/2012
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Publication #:
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Pub Dt:
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03/07/2013
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Title:
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IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES
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Patent #:
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Issue Dt:
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06/24/2014
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Application #:
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13667312
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
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03/07/2013
| | | | |
Title:
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SEGREGATING WAFER CARRIER TYPES IN SEMICONDUCTOR STORAGE DEVICES
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Patent #:
|
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Issue Dt:
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08/11/2015
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Application #:
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13667384
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX USING SELECTIVE EPITAXY ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
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Patent #:
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Issue Dt:
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01/12/2016
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Application #:
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13667389
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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FABRICATION OF LOCALIZED SOI ON LOCALIZED THICK BOX LATERAL EPITAXIAL REALIGNMENT OF DEPOSITED NON-CRYSTALLINE FILM ON BULK SEMICONDUCTOR SUBSTRATES FOR PHOTONICS DEVICE INTEGRATION
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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13667603
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Filing Dt:
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11/02/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13668401
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Filing Dt:
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11/05/2012
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Publication #:
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Pub Dt:
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12/12/2013
| | | | |
Title:
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SIDE-GATE DEFINED TUNABLE NANOCONSTRICTION IN DOUBLE-GATED GRAPHENE MULTILAYERS
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13668869
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Filing Dt:
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11/05/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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MAGNETORESISTIVE RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13669627
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Filing Dt:
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11/06/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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CLEANING COMPOSITION AND PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
|
02/11/2014
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Application #:
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13669651
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Filing Dt:
|
11/06/2012
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Title:
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PROCESS FOR CLEANING SEMICONDUCTOR DEVICES AND/OR TOOLING DURING MANUFACTURING THEREOF
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|
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Patent #:
|
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Issue Dt:
|
03/24/2015
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Application #:
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13669891
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Filing Dt:
|
11/06/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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MAPPING DENSITY AND TEMPERATURE OF A CHIP, IN SITU
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Patent #:
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Issue Dt:
|
08/19/2014
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Application #:
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13670674
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Filing Dt:
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11/07/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
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|
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Patent #:
|
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Issue Dt:
|
07/08/2014
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Application #:
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13670694
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Filing Dt:
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11/07/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
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ENHANCED CAPTURE PADS FOR THROUGH SEMICONDUCTOR VIAS
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|
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Patent #:
|
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Issue Dt:
|
08/12/2014
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Application #:
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13670711
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
|
COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME
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|
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Patent #:
|
|
Issue Dt:
|
09/16/2014
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Application #:
|
13670748
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Filing Dt:
|
11/07/2012
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Publication #:
|
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Pub Dt:
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05/08/2014
| | | | |
Title:
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ROBUST REPLACEMENT GATE INTEGRATION
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|
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Patent #:
|
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Issue Dt:
|
07/01/2014
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Application #:
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13670768
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET
|
|
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Patent #:
|
|
Issue Dt:
|
03/25/2014
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Application #:
|
13670921
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Filing Dt:
|
11/07/2012
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Title:
|
SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
13670960
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
|
PRE-SIMULATION CIRCUIT PARTITIONING
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|
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Patent #:
|
|
Issue Dt:
|
08/27/2013
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Application #:
|
13671098
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Filing Dt:
|
11/07/2012
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Title:
|
WAFER-TO-WAFER PROCESS FOR MANUFACTURING A STACKED STRUCTURE
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|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
|
13671166
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Filing Dt:
|
11/07/2012
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Publication #:
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Pub Dt:
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05/08/2014
| | | | |
Title:
|
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
|
|