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Patent #:
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|
Issue Dt:
|
01/21/2014
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Application #:
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13671186
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Filing Dt:
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11/07/2012
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Title:
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SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13671605
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Filing Dt:
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11/08/2012
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Publication #:
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|
Pub Dt:
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05/08/2014
| | | | |
Title:
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STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
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Patent #:
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Issue Dt:
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10/21/2014
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Application #:
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13671776
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Filing Dt:
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11/08/2012
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Publication #:
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Pub Dt:
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05/01/2014
| | | | |
Title:
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Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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13671940
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Filing Dt:
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11/08/2012
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Publication #:
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|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13672040
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Filing Dt:
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11/08/2012
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Publication #:
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|
Pub Dt:
|
03/14/2013
| | | | |
Title:
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HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
|
13672257
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Filing Dt:
|
11/08/2012
|
Publication #:
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Pub Dt:
|
04/17/2014
| | | | |
Title:
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STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE
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Patent #:
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Issue Dt:
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11/15/2016
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Application #:
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13672751
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Filing Dt:
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11/09/2012
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Publication #:
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Pub Dt:
|
05/16/2013
| | | | |
Title:
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MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE
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Patent #:
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Issue Dt:
|
06/16/2015
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Application #:
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13672770
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Filing Dt:
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11/09/2012
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Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
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PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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13672864
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Filing Dt:
|
11/09/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT
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|
Patent #:
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Issue Dt:
|
04/28/2015
|
Application #:
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13672925
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Filing Dt:
|
11/09/2012
|
Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
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DUAL GATE FINFET DEVICES
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|
Patent #:
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|
Issue Dt:
|
02/09/2016
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Application #:
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13673262
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Filing Dt:
|
11/09/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS
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|
Patent #:
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|
Issue Dt:
|
11/19/2013
|
Application #:
|
13673521
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Filing Dt:
|
11/09/2012
|
Title:
|
DEVICE-BASED RANDOM VARIABILITY MODELING IN TIMING ANALYSIS
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|
Patent #:
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|
Issue Dt:
|
07/01/2014
|
Application #:
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13674225
|
Filing Dt:
|
11/12/2012
|
Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
INSULATIVE CAP FOR BORDERLESS SELF-ALIGNING CONTACT IN SEMICONDUCTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13674498
|
Filing Dt:
|
11/12/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
METHOD OF MANUFACTURING AN ENHANCED ELECTROMIGRATION PERFORMANCE HETERO-JUNCTION BIPOLAR TRANSISTOR
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|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13674623
|
Filing Dt:
|
11/12/2012
|
Publication #:
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|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
Wafer-to-Wafer Process for Manufacturing a Stacked Structure
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13675496
|
Filing Dt:
|
11/13/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
PRECISE SIMULATION OF PROGENY DERIVED FROM RECOMBINING PARENTS
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|
Patent #:
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|
Issue Dt:
|
11/17/2015
|
Application #:
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13676063
|
Filing Dt:
|
11/13/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
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FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN
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|
Patent #:
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|
Issue Dt:
|
03/25/2014
|
Application #:
|
13676174
|
Filing Dt:
|
11/14/2012
|
Publication #:
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|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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|
|
Patent #:
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|
Issue Dt:
|
12/17/2013
|
Application #:
|
13676180
|
Filing Dt:
|
11/14/2012
|
Publication #:
|
|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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|
|
Patent #:
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|
Issue Dt:
|
01/19/2016
|
Application #:
|
13676412
|
Filing Dt:
|
11/14/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE
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|
|
Patent #:
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|
Issue Dt:
|
09/09/2014
|
Application #:
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13676817
|
Filing Dt:
|
11/14/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
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|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
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13676927
|
Filing Dt:
|
11/14/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES
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|
|
Patent #:
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|
Issue Dt:
|
02/11/2014
|
Application #:
|
13677373
|
Filing Dt:
|
11/15/2012
|
Title:
|
ELASTIC MODULUS MAPPING OF AN INTEGRATED CIRCUIT CHIP IN A CHIP/DEVICE PACKAGE
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13677489
|
Filing Dt:
|
11/15/2012
|
Publication #:
|
|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK
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|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
13677542
|
Filing Dt:
|
11/15/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
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|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
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13677610
|
Filing Dt:
|
11/15/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
09/23/2014
|
Application #:
|
13677647
|
Filing Dt:
|
11/15/2012
|
Publication #:
|
|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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|
Patent #:
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|
Issue Dt:
|
01/07/2014
|
Application #:
|
13677863
|
Filing Dt:
|
11/15/2012
|
Title:
|
SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
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|
Patent #:
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|
Issue Dt:
|
12/08/2015
|
Application #:
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13677908
|
Filing Dt:
|
11/15/2012
|
Publication #:
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|
Pub Dt:
|
05/01/2014
| | | | |
Title:
|
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
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|
Patent #:
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|
Issue Dt:
|
06/02/2015
|
Application #:
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13677954
|
Filing Dt:
|
11/15/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
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DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
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|
Patent #:
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|
Issue Dt:
|
08/04/2015
|
Application #:
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13677997
|
Filing Dt:
|
11/15/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
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SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
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|
Patent #:
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|
Issue Dt:
|
12/02/2014
|
Application #:
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13678111
|
Filing Dt:
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11/15/2012
|
Publication #:
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|
Pub Dt:
|
04/17/2014
| | | | |
Title:
|
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
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|
Patent #:
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|
Issue Dt:
|
11/12/2013
|
Application #:
|
13679115
|
Filing Dt:
|
11/16/2012
|
Title:
|
BLOCK MASK DECOMPOSITION FOR MITIGATING CORNER ROUNDING
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|
Patent #:
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|
Issue Dt:
|
02/18/2014
|
Application #:
|
13679222
|
Filing Dt:
|
11/16/2012
|
Title:
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STRAINED SIGE NANOWIRE HAVING (111)-ORIENTED SIDEWALLS
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|
Patent #:
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|
Issue Dt:
|
06/09/2015
|
Application #:
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13679284
|
Filing Dt:
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11/16/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
02/04/2014
|
Application #:
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13679357
|
Filing Dt:
|
11/16/2012
|
Publication #:
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|
Pub Dt:
|
03/21/2013
| | | | |
Title:
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SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
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|
|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
13680470
|
Filing Dt:
|
11/19/2012
|
Publication #:
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|
Pub Dt:
|
03/21/2013
| | | | |
Title:
|
STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS
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|
Patent #:
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|
Issue Dt:
|
04/01/2014
|
Application #:
|
13680560
|
Filing Dt:
|
11/19/2012
|
Title:
|
METAL GATE STRUCTURES FOR CMOS TRANSISTOR DEVICES HAVING REDUCED PARASITIC CAPACITANCE
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|
Patent #:
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|
Issue Dt:
|
07/08/2014
|
Application #:
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13680775
|
Filing Dt:
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11/19/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN
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|
Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
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13681761
|
Filing Dt:
|
11/20/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
DENSE FINFET SRAM
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|
|
Patent #:
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|
Issue Dt:
|
08/26/2014
|
Application #:
|
13682056
|
Filing Dt:
|
11/20/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
POLYGON RECOVERY FOR VLSI MASK CORRECTION
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|
Patent #:
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|
Issue Dt:
|
10/08/2013
|
Application #:
|
13682108
|
Filing Dt:
|
11/20/2012
|
Publication #:
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|
Pub Dt:
|
03/28/2013
| | | | |
Title:
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FIELD EFFECT TRANSISTOR WITH ASYMMETRIC ABRUPT JUNCTION IMPLANT
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|
Patent #:
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|
Issue Dt:
|
01/28/2014
|
Application #:
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13682184
|
Filing Dt:
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11/20/2012
|
Publication #:
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|
Pub Dt:
|
04/25/2013
| | | | |
Title:
|
ENHANCING INVESTIGATION OF VARIABILITY BY INCLUSION OF SIMILAR OBJECTS WITH KNOWN DIFFERENCES TO THE ORIGINAL ONES
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
13683050
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Filing Dt:
|
11/21/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
PATTERNED BACKSIDE METAL GROUND PLANE FOR IMPROVED METAL ADHESION
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|
Patent #:
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|
Issue Dt:
|
04/26/2016
|
Application #:
|
13683508
|
Filing Dt:
|
11/21/2012
|
Publication #:
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|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
POWER-SCALABLE SKEW COMPENSATION IN SOURCE-SYNCHRONOUS PARALLEL INTERFACES
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|
Patent #:
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|
Issue Dt:
|
07/01/2014
|
Application #:
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13684695
|
Filing Dt:
|
11/26/2012
|
Publication #:
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|
Pub Dt:
|
05/15/2014
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES
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|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13684818
|
Filing Dt:
|
11/26/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS
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|
Patent #:
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|
Issue Dt:
|
02/03/2015
|
Application #:
|
13684842
|
Filing Dt:
|
11/26/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
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|
Patent #:
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|
Issue Dt:
|
06/10/2014
|
Application #:
|
13684869
|
Filing Dt:
|
11/26/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK
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|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
13685077
|
Filing Dt:
|
11/26/2012
|
Publication #:
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|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY
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|
Patent #:
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|
Issue Dt:
|
05/21/2013
|
Application #:
|
13685113
|
Filing Dt:
|
11/26/2012
|
Publication #:
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|
Pub Dt:
|
03/28/2013
| | | | |
Title:
|
MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
06/16/2015
|
Application #:
|
13685733
|
Filing Dt:
|
11/27/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
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Finfet Semiconductor Device Having Increased Gate Height Control
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|
|
Patent #:
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|
Issue Dt:
|
04/15/2014
|
Application #:
|
13685735
|
Filing Dt:
|
11/27/2012
|
Title:
|
LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
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|
Patent #:
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|
Issue Dt:
|
12/16/2014
|
Application #:
|
13685779
|
Filing Dt:
|
11/27/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY
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|
Patent #:
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|
Issue Dt:
|
10/14/2014
|
Application #:
|
13686263
|
Filing Dt:
|
11/27/2012
|
Publication #:
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|
Pub Dt:
|
04/04/2013
| | | | |
Title:
|
METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS
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|
Patent #:
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|
Issue Dt:
|
12/23/2014
|
Application #:
|
13686377
|
Filing Dt:
|
11/27/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13686414
|
Filing Dt:
|
11/27/2012
|
Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY
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|
Patent #:
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|
Issue Dt:
|
01/28/2014
|
Application #:
|
13686422
|
Filing Dt:
|
11/27/2012
|
Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13686624
|
Filing Dt:
|
11/27/2012
|
Title:
|
AUTOMATED SYNTHESIS OF HIGH-PERFORMANCE TWO OPERAND BINARY PARALLEL PREFIX ADDER
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|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13686954
|
Filing Dt:
|
11/28/2012
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION
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|
|
Patent #:
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Issue Dt:
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06/09/2015
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Application #:
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13686969
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13686989
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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CORNER SPECIFIC NORMALIZATION OF STATIC TIMING ANALYSIS
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Patent #:
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Issue Dt:
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06/03/2014
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Application #:
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13687218
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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04/11/2013
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Title:
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Ball Grid Array with Improved Single-Ended and Differential Signal Performance
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13687240
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/16/2013
| | | | |
Title:
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METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
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Patent #:
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Issue Dt:
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03/10/2015
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Application #:
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13687314
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/15/2014
| | | | |
Title:
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CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13687515
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
|
STRAIN RELAXATION WITH SELF-ALIGNED NOTCH
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13687531
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Filing Dt:
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11/28/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
|
WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION
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Patent #:
|
|
Issue Dt:
|
03/04/2014
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Application #:
|
13688595
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Filing Dt:
|
11/29/2012
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Title:
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INTEGRATED CIRCUIT HAVING LOCAL MAXIMUM OPERATING VOLTAGE
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Patent #:
|
|
Issue Dt:
|
11/26/2013
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Application #:
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13688879
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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04/11/2013
| | | | |
Title:
|
CHROMELESS PHASE-SHIFTING PHOTOMASK WITH UNDERCUT RIM-SHIFTING ELEMENT
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|
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Patent #:
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|
Issue Dt:
|
06/16/2015
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Application #:
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13689044
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Filing Dt:
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11/29/2012
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Publication #:
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Pub Dt:
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05/29/2014
| | | | |
Title:
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ISOLATING FAILING LATCHES USING A LOGIC BUILT-IN SELF-TEST
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|
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Patent #:
|
|
Issue Dt:
|
06/03/2014
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Application #:
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13689052
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Filing Dt:
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11/29/2012
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Publication #:
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|
Pub Dt:
|
05/08/2014
| | | | |
Title:
|
MAGNETORESISTIVE RANDOM ACCESS MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
09/06/2016
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Application #:
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13689090
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Filing Dt:
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11/29/2012
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Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
LIGHT ACTIVATED TEST CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
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Application #:
|
13689437
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Filing Dt:
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11/29/2012
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Publication #:
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|
Pub Dt:
|
05/29/2014
| | | | |
Title:
|
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS
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|
Patent #:
|
|
Issue Dt:
|
08/26/2014
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Application #:
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13689838
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Filing Dt:
|
11/30/2012
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Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
HETEROJUNCTION BIPOLAR TRANSISTOR
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|
|
Patent #:
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|
Issue Dt:
|
01/06/2015
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Application #:
|
13689924
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Filing Dt:
|
11/30/2012
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Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
UNIFORM FINFET GATE HEIGHT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13689948
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Filing Dt:
|
11/30/2012
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Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
UNIFORM FINFET GATE HEIGHT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13690209
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Filing Dt:
|
11/30/2012
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Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
TECHNIQUES FOR ROUTING SIGNAL WIRES IN AN INTEGRATED CIRCUIT DESIGN
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|
|
Patent #:
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|
Issue Dt:
|
02/03/2015
|
Application #:
|
13690240
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Filing Dt:
|
11/30/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
Semiconductor Device Having SSOI Substrate with Relaxed Tensile Stress
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|
|
Patent #:
|
|
Issue Dt:
|
05/12/2015
|
Application #:
|
13690867
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Filing Dt:
|
11/30/2012
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Publication #:
|
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Pub Dt:
|
06/05/2014
| | | | |
Title:
|
SEMICONDUCTOR DEVICE WITH REPLACEMENT METAL GATE AND METHOD FOR SELECTIVE DEPOSITION OF MATERIAL FOR REPLACEMENT METAL GATE
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|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
13690871
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Filing Dt:
|
11/30/2012
|
Publication #:
|
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Pub Dt:
|
06/05/2014
| | | | |
Title:
|
METHODS, SYSTEMS AND COMPUTER PROGRAM STORAGE DEVICES FOR GENERATING A FLOODING FORECAST
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13690985
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Filing Dt:
|
11/30/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
RECONFIGURABLE SWITCHED-CAPACITOR VOLTAGE CONVERTER CIRCUIT, INTEGRATED CIRCUIT (IC) CHIP INCLUDING THE CIRCUIT AND METHOD OF SWITCHING VOLTAGE ON CHIP
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|
|
Patent #:
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|
Issue Dt:
|
08/18/2015
|
Application #:
|
13691129
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Filing Dt:
|
11/30/2012
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Publication #:
|
|
Pub Dt:
|
04/11/2013
| | | | |
Title:
|
MULTI COMPONENT DIELECTRIC LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
13692069
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
INDUCING CHANNEL STRESS IN SEMICONDUCTOR-ON-INSULATOR DEVICES BY BASE SUBSTRATE OXIDATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13692144
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
FIN FIELD EFFECT TRANSISTORS INCLUDING COMPLIMENTARILY STRESSED CHANNELS
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13692162
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
SUBSTRATE-TEMPLATED EPITAXIAL SOURCE/DRAIN CONTACT STRUCTURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13692182
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
HYBRID NANOMESH STRUCTURES
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13692188
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
NANOMESH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS
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|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13692603
|
Filing Dt:
|
12/03/2012
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
Title:
|
DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
13693127
|
Filing Dt:
|
12/04/2012
|
Title:
|
IDENTIFYING LOGIC BLOCKS IN A SYNTHESIZED LOGIC DESIGN THAT HAVE SPECIFIED INPUTS
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|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13693285
|
Filing Dt:
|
12/04/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH
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|
|
Patent #:
|
|
Issue Dt:
|
01/13/2015
|
Application #:
|
13693749
|
Filing Dt:
|
12/04/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
FAR BACK END OF THE LINE STACK ENCAPSULATION
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|
|
Patent #:
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|
Issue Dt:
|
08/05/2014
|
Application #:
|
13705242
|
Filing Dt:
|
12/05/2012
|
Publication #:
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|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
Inducing Channel Strain via Encapsulated Silicide Formation
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|
|
Patent #:
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|
Issue Dt:
|
06/09/2015
|
Application #:
|
13705300
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
Title:
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DYNAMICALLY LIMITING ENERGY CONSUMED BY COOLING APPARATUS
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|
|
Patent #:
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|
Issue Dt:
|
03/18/2014
|
Application #:
|
13705477
|
Filing Dt:
|
12/05/2012
|
Title:
|
Finfet eDram Strap Connection Structure
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|
|
Patent #:
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|
Issue Dt:
|
07/28/2015
|
Application #:
|
13705717
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13705738
|
Filing Dt:
|
12/05/2012
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
Title:
|
MODELING MULTIPLE INTERACTIONS BETWEEN MULTIPLE LOCI
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|
|
Patent #:
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|
Issue Dt:
|
12/17/2013
|
Application #:
|
13705920
|
Filing Dt:
|
12/05/2012
|
Title:
|
GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
13707003
|
Filing Dt:
|
12/06/2012
|
Publication #:
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|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13707058
|
Filing Dt:
|
12/06/2012
|
Publication #:
|
|
Pub Dt:
|
05/16/2013
| | | | |
Title:
|
SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13707864
|
Filing Dt:
|
12/07/2012
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
Title:
|
ETCH RESISTANT RAISED ISOLATION FOR SEMICONDUCTOR DEVICES
|
|