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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
01/21/2014
Application #:
13671186
Filing Dt:
11/07/2012
Title:
SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS
2
Patent #:
Issue Dt:
01/13/2015
Application #:
13671605
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
05/08/2014
Title:
STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
3
Patent #:
Issue Dt:
10/21/2014
Application #:
13671776
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
05/01/2014
Title:
Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process
4
Patent #:
Issue Dt:
07/08/2014
Application #:
13671940
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
05/08/2014
Title:
METHODS OF FORMING REPLACEMENT GATE STRUCTURES ON SEMICONDUCTOR DEVICES AND THE RESULTING DEVICE
5
Patent #:
Issue Dt:
08/20/2013
Application #:
13672040
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
03/14/2013
Title:
HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
6
Patent #:
NONE
Issue Dt:
Application #:
13672257
Filing Dt:
11/08/2012
Publication #:
Pub Dt:
04/17/2014
Title:
STRUCTURE FOR MEMS TRANSISTORS ON FAR BACK END OF LINE
7
Patent #:
Issue Dt:
11/15/2016
Application #:
13672751
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
05/16/2013
Title:
MEMORY MODULE AND MEMORY CONTROLLER FOR CONTROLLING A MEMORY MODULE
8
Patent #:
Issue Dt:
06/16/2015
Application #:
13672770
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
05/15/2014
Title:
PROACTIVE RISK ANALYSIS AND GOVERNANCE OF UPGRADE PROCESS
9
Patent #:
NONE
Issue Dt:
Application #:
13672864
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
05/15/2014
Title:
DIELECTRIC CAP LAYER FOR REPLACEMENT GATE WITH SELF-ALIGNED CONTACT
10
Patent #:
Issue Dt:
04/28/2015
Application #:
13672925
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
05/01/2014
Title:
DUAL GATE FINFET DEVICES
11
Patent #:
Issue Dt:
02/09/2016
Application #:
13673262
Filing Dt:
11/09/2012
Publication #:
Pub Dt:
05/15/2014
Title:
MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS
12
Patent #:
Issue Dt:
11/19/2013
Application #:
13673521
Filing Dt:
11/09/2012
Title:
DEVICE-BASED RANDOM VARIABILITY MODELING IN TIMING ANALYSIS
13
Patent #:
Issue Dt:
07/01/2014
Application #:
13674225
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
05/01/2014
Title:
INSULATIVE CAP FOR BORDERLESS SELF-ALIGNING CONTACT IN SEMICONDUCTOR DEVICE
14
Patent #:
Issue Dt:
12/02/2014
Application #:
13674498
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
05/15/2014
Title:
METHOD OF MANUFACTURING AN ENHANCED ELECTROMIGRATION PERFORMANCE HETERO-JUNCTION BIPOLAR TRANSISTOR
15
Patent #:
NONE
Issue Dt:
Application #:
13674623
Filing Dt:
11/12/2012
Publication #:
Pub Dt:
05/08/2014
Title:
Wafer-to-Wafer Process for Manufacturing a Stacked Structure
16
Patent #:
NONE
Issue Dt:
Application #:
13675496
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
05/15/2014
Title:
PRECISE SIMULATION OF PROGENY DERIVED FROM RECOMBINING PARENTS
17
Patent #:
Issue Dt:
11/17/2015
Application #:
13676063
Filing Dt:
11/13/2012
Publication #:
Pub Dt:
05/15/2014
Title:
FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN
18
Patent #:
Issue Dt:
03/25/2014
Application #:
13676174
Filing Dt:
11/14/2012
Publication #:
Pub Dt:
03/21/2013
Title:
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
19
Patent #:
Issue Dt:
12/17/2013
Application #:
13676180
Filing Dt:
11/14/2012
Publication #:
Pub Dt:
03/21/2013
Title:
CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
20
Patent #:
Issue Dt:
01/19/2016
Application #:
13676412
Filing Dt:
11/14/2012
Publication #:
Pub Dt:
05/15/2014
Title:
SEMICONDUCTOR DEVICE HAVING DIFFUSION BARRIER TO REDUCE BACK CHANNEL LEAKAGE
21
Patent #:
Issue Dt:
09/09/2014
Application #:
13676817
Filing Dt:
11/14/2012
Publication #:
Pub Dt:
05/15/2014
Title:
COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE
22
Patent #:
Issue Dt:
07/08/2014
Application #:
13676927
Filing Dt:
11/14/2012
Publication #:
Pub Dt:
05/15/2014
Title:
FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES
23
Patent #:
Issue Dt:
02/11/2014
Application #:
13677373
Filing Dt:
11/15/2012
Title:
ELASTIC MODULUS MAPPING OF AN INTEGRATED CIRCUIT CHIP IN A CHIP/DEVICE PACKAGE
24
Patent #:
NONE
Issue Dt:
Application #:
13677489
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
04/17/2014
Title:
FIELD EFFECT TRANSISTOR DEVICE HAVING A HYBRID METAL GATE STACK
25
Patent #:
Issue Dt:
07/19/2016
Application #:
13677542
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
04/17/2014
Title:
System for Wafer Quality Predictive Modeling based on Multi-Source Information with Heterogeneous Relatedness
26
Patent #:
Issue Dt:
06/16/2015
Application #:
13677610
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
05/15/2014
Title:
ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES
27
Patent #:
Issue Dt:
09/23/2014
Application #:
13677647
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
05/15/2014
Title:
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
28
Patent #:
Issue Dt:
01/07/2014
Application #:
13677863
Filing Dt:
11/15/2012
Title:
SELF-FORMATION OF HIGH-DENSITY DEFECT-FREE AND ALIGNED NANOSTRUCTURES
29
Patent #:
Issue Dt:
12/08/2015
Application #:
13677908
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
05/01/2014
Title:
BACK-END TRANSISTORS WITH HIGHLY DOPED LOW-TEMPERATURE CONTACTS
30
Patent #:
Issue Dt:
06/02/2015
Application #:
13677954
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
05/15/2014
Title:
DUAL PHASE GALLIUM NITRIDE MATERIAL FORMATION ON (100) SILICON
31
Patent #:
Issue Dt:
08/04/2015
Application #:
13677997
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
05/15/2014
Title:
SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
32
Patent #:
Issue Dt:
12/02/2014
Application #:
13678111
Filing Dt:
11/15/2012
Publication #:
Pub Dt:
04/17/2014
Title:
EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT
33
Patent #:
Issue Dt:
11/12/2013
Application #:
13679115
Filing Dt:
11/16/2012
Title:
BLOCK MASK DECOMPOSITION FOR MITIGATING CORNER ROUNDING
34
Patent #:
Issue Dt:
02/18/2014
Application #:
13679222
Filing Dt:
11/16/2012
Title:
STRAINED SIGE NANOWIRE HAVING (111)-ORIENTED SIDEWALLS
35
Patent #:
Issue Dt:
06/09/2015
Application #:
13679284
Filing Dt:
11/16/2012
Publication #:
Pub Dt:
05/22/2014
Title:
LOCAL TAILORING OF FINGERS IN MULTI-FINGER FIN FIELD EFFECT TRANSISTORS
36
Patent #:
Issue Dt:
02/04/2014
Application #:
13679357
Filing Dt:
11/16/2012
Publication #:
Pub Dt:
03/21/2013
Title:
SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE
37
Patent #:
NONE
Issue Dt:
Application #:
13680470
Filing Dt:
11/19/2012
Publication #:
Pub Dt:
03/21/2013
Title:
STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS
38
Patent #:
Issue Dt:
04/01/2014
Application #:
13680560
Filing Dt:
11/19/2012
Title:
METAL GATE STRUCTURES FOR CMOS TRANSISTOR DEVICES HAVING REDUCED PARASITIC CAPACITANCE
39
Patent #:
Issue Dt:
07/08/2014
Application #:
13680775
Filing Dt:
11/19/2012
Publication #:
Pub Dt:
05/22/2014
Title:
DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN
40
Patent #:
Issue Dt:
09/02/2014
Application #:
13681761
Filing Dt:
11/20/2012
Publication #:
Pub Dt:
05/22/2014
Title:
DENSE FINFET SRAM
41
Patent #:
Issue Dt:
08/26/2014
Application #:
13682056
Filing Dt:
11/20/2012
Publication #:
Pub Dt:
05/22/2014
Title:
POLYGON RECOVERY FOR VLSI MASK CORRECTION
42
Patent #:
Issue Dt:
10/08/2013
Application #:
13682108
Filing Dt:
11/20/2012
Publication #:
Pub Dt:
03/28/2013
Title:
FIELD EFFECT TRANSISTOR WITH ASYMMETRIC ABRUPT JUNCTION IMPLANT
43
Patent #:
Issue Dt:
01/28/2014
Application #:
13682184
Filing Dt:
11/20/2012
Publication #:
Pub Dt:
04/25/2013
Title:
ENHANCING INVESTIGATION OF VARIABILITY BY INCLUSION OF SIMILAR OBJECTS WITH KNOWN DIFFERENCES TO THE ORIGINAL ONES
44
Patent #:
NONE
Issue Dt:
Application #:
13683050
Filing Dt:
11/21/2012
Publication #:
Pub Dt:
05/22/2014
Title:
PATTERNED BACKSIDE METAL GROUND PLANE FOR IMPROVED METAL ADHESION
45
Patent #:
Issue Dt:
04/26/2016
Application #:
13683508
Filing Dt:
11/21/2012
Publication #:
Pub Dt:
05/22/2014
Title:
POWER-SCALABLE SKEW COMPENSATION IN SOURCE-SYNCHRONOUS PARALLEL INTERFACES
46
Patent #:
Issue Dt:
07/01/2014
Application #:
13684695
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
05/15/2014
Title:
FIELD EFFECT TRANSISTOR DEVICES WITH DOPANT FREE CHANNELS AND BACK GATES
47
Patent #:
Issue Dt:
03/24/2015
Application #:
13684818
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
05/29/2014
Title:
FIN ISOLATION IN MULTI-GATE FIELD EFFECT TRANSISTORS
48
Patent #:
Issue Dt:
02/03/2015
Application #:
13684842
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
05/29/2014
Title:
DUMMY FIN FORMATION BY GAS CLUSTER ION BEAM
49
Patent #:
Issue Dt:
06/10/2014
Application #:
13684869
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
05/29/2014
Title:
REPLACEMENT METAL GATE TRANSISTORS USING BI-LAYER HARDMASK
50
Patent #:
Issue Dt:
05/21/2013
Application #:
13685077
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
04/04/2013
Title:
MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY
51
Patent #:
Issue Dt:
05/21/2013
Application #:
13685113
Filing Dt:
11/26/2012
Publication #:
Pub Dt:
03/28/2013
Title:
MULTILEVEL PROGRAMMING OF PHASE CHANGE MEMORY
52
Patent #:
Issue Dt:
06/16/2015
Application #:
13685733
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
05/29/2014
Title:
Finfet Semiconductor Device Having Increased Gate Height Control
53
Patent #:
Issue Dt:
04/15/2014
Application #:
13685735
Filing Dt:
11/27/2012
Title:
LOCALLY ISOLATED PROTECTED BULK FINFET SEMICONDUCTOR DEVICE
54
Patent #:
Issue Dt:
12/16/2014
Application #:
13685779
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
05/29/2014
Title:
SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRCUITRY
55
Patent #:
Issue Dt:
10/14/2014
Application #:
13686263
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/04/2013
Title:
METHOD OF MANUFACTURING COMPLIMENTARY METAL-INSULATOR-METAL (MIM) CAPACITORS
56
Patent #:
Issue Dt:
12/23/2014
Application #:
13686377
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
05/29/2014
Title:
PACKAGE STRUCTURES TO IMPROVE ON-CHIP ANTENNA PERFORMANCE
57
Patent #:
NONE
Issue Dt:
Application #:
13686414
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
05/29/2014
Title:
DIAGNOSTIC TESTING FOR A DOUBLE-PUMPED MEMORY ARRAY
58
Patent #:
Issue Dt:
01/28/2014
Application #:
13686422
Filing Dt:
11/27/2012
Publication #:
Pub Dt:
04/11/2013
Title:
ELECTROSTATIC DISCHARGE (ESD) SILICON CONTROLLED RECTIFIER (SCR) STRUCTURE
59
Patent #:
Issue Dt:
03/25/2014
Application #:
13686624
Filing Dt:
11/27/2012
Title:
AUTOMATED SYNTHESIS OF HIGH-PERFORMANCE TWO OPERAND BINARY PARALLEL PREFIX ADDER
60
Patent #:
Issue Dt:
01/06/2015
Application #:
13686954
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/29/2014
Title:
VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION
61
Patent #:
Issue Dt:
06/09/2015
Application #:
13686969
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/29/2014
Title:
DOUBLE DENSITY SEMICONDUCTOR FINS AND METHOD OF FABRICATION
62
Patent #:
NONE
Issue Dt:
Application #:
13686989
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/29/2014
Title:
CORNER SPECIFIC NORMALIZATION OF STATIC TIMING ANALYSIS
63
Patent #:
Issue Dt:
06/03/2014
Application #:
13687218
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
04/11/2013
Title:
Ball Grid Array with Improved Single-Ended and Differential Signal Performance
64
Patent #:
Issue Dt:
01/07/2014
Application #:
13687240
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/16/2013
Title:
METHOD FOR FORMING AND STRUCTURE OF A RECESSED SOURCE/DRAIN STRAP FOR A MUGFET
65
Patent #:
Issue Dt:
03/10/2015
Application #:
13687314
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/15/2014
Title:
CO-INTEGRATION OF ELEMENTAL SEMICONDUCTOR DEVICES AND COMPOUND SEMICONDUCTOR DEVICES
66
Patent #:
NONE
Issue Dt:
Application #:
13687515
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/29/2014
Title:
STRAIN RELAXATION WITH SELF-ALIGNED NOTCH
67
Patent #:
NONE
Issue Dt:
Application #:
13687531
Filing Dt:
11/28/2012
Publication #:
Pub Dt:
05/29/2014
Title:
WAFER DEBONDING USING LONG-WAVELENGTH INFRARED RADIATION ABLATION
68
Patent #:
Issue Dt:
03/04/2014
Application #:
13688595
Filing Dt:
11/29/2012
Title:
INTEGRATED CIRCUIT HAVING LOCAL MAXIMUM OPERATING VOLTAGE
69
Patent #:
Issue Dt:
11/26/2013
Application #:
13688879
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
04/11/2013
Title:
CHROMELESS PHASE-SHIFTING PHOTOMASK WITH UNDERCUT RIM-SHIFTING ELEMENT
70
Patent #:
Issue Dt:
06/16/2015
Application #:
13689044
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/29/2014
Title:
ISOLATING FAILING LATCHES USING A LOGIC BUILT-IN SELF-TEST
71
Patent #:
Issue Dt:
06/03/2014
Application #:
13689052
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/08/2014
Title:
MAGNETORESISTIVE RANDOM ACCESS MEMORY
72
Patent #:
Issue Dt:
09/06/2016
Application #:
13689090
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/29/2014
Title:
LIGHT ACTIVATED TEST CONNECTIONS
73
Patent #:
Issue Dt:
02/10/2015
Application #:
13689437
Filing Dt:
11/29/2012
Publication #:
Pub Dt:
05/29/2014
Title:
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS
74
Patent #:
Issue Dt:
08/26/2014
Application #:
13689838
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR
75
Patent #:
Issue Dt:
01/06/2015
Application #:
13689924
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
UNIFORM FINFET GATE HEIGHT
76
Patent #:
Issue Dt:
09/09/2014
Application #:
13689948
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
UNIFORM FINFET GATE HEIGHT
77
Patent #:
Issue Dt:
02/03/2015
Application #:
13690209
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
TECHNIQUES FOR ROUTING SIGNAL WIRES IN AN INTEGRATED CIRCUIT DESIGN
78
Patent #:
Issue Dt:
02/03/2015
Application #:
13690240
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
Semiconductor Device Having SSOI Substrate with Relaxed Tensile Stress
79
Patent #:
Issue Dt:
05/12/2015
Application #:
13690867
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
SEMICONDUCTOR DEVICE WITH REPLACEMENT METAL GATE AND METHOD FOR SELECTIVE DEPOSITION OF MATERIAL FOR REPLACEMENT METAL GATE
80
Patent #:
NONE
Issue Dt:
Application #:
13690871
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
METHODS, SYSTEMS AND COMPUTER PROGRAM STORAGE DEVICES FOR GENERATING A FLOODING FORECAST
81
Patent #:
NONE
Issue Dt:
Application #:
13690985
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
06/05/2014
Title:
RECONFIGURABLE SWITCHED-CAPACITOR VOLTAGE CONVERTER CIRCUIT, INTEGRATED CIRCUIT (IC) CHIP INCLUDING THE CIRCUIT AND METHOD OF SWITCHING VOLTAGE ON CHIP
82
Patent #:
Issue Dt:
08/18/2015
Application #:
13691129
Filing Dt:
11/30/2012
Publication #:
Pub Dt:
04/11/2013
Title:
MULTI COMPONENT DIELECTRIC LAYER
83
Patent #:
Issue Dt:
08/26/2014
Application #:
13692069
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
INDUCING CHANNEL STRESS IN SEMICONDUCTOR-ON-INSULATOR DEVICES BY BASE SUBSTRATE OXIDATION
84
Patent #:
NONE
Issue Dt:
Application #:
13692144
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
FIN FIELD EFFECT TRANSISTORS INCLUDING COMPLIMENTARILY STRESSED CHANNELS
85
Patent #:
NONE
Issue Dt:
Application #:
13692162
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
SUBSTRATE-TEMPLATED EPITAXIAL SOURCE/DRAIN CONTACT STRUCTURES
86
Patent #:
NONE
Issue Dt:
Application #:
13692182
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
HYBRID NANOMESH STRUCTURES
87
Patent #:
NONE
Issue Dt:
Application #:
13692188
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
06/05/2014
Title:
NANOMESH COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS
88
Patent #:
Issue Dt:
07/08/2014
Application #:
13692603
Filing Dt:
12/03/2012
Publication #:
Pub Dt:
05/22/2014
Title:
DIELECTRIC EQUIVALENT THICKNESS AND CAPACITANCE SCALING FOR SEMICONDUCTOR DEVICES
89
Patent #:
Issue Dt:
12/10/2013
Application #:
13693127
Filing Dt:
12/04/2012
Title:
IDENTIFYING LOGIC BLOCKS IN A SYNTHESIZED LOGIC DESIGN THAT HAVE SPECIFIED INPUTS
90
Patent #:
Issue Dt:
05/27/2014
Application #:
13693285
Filing Dt:
12/04/2012
Publication #:
Pub Dt:
06/05/2014
Title:
NON-VOLATILE GRAPHENE NANOMECHANICAL SWITCH
91
Patent #:
Issue Dt:
01/13/2015
Application #:
13693749
Filing Dt:
12/04/2012
Publication #:
Pub Dt:
06/05/2014
Title:
FAR BACK END OF THE LINE STACK ENCAPSULATION
92
Patent #:
Issue Dt:
08/05/2014
Application #:
13705242
Filing Dt:
12/05/2012
Publication #:
Pub Dt:
06/05/2014
Title:
Inducing Channel Strain via Encapsulated Silicide Formation
93
Patent #:
Issue Dt:
06/09/2015
Application #:
13705300
Filing Dt:
12/05/2012
Publication #:
Pub Dt:
05/30/2013
Title:
DYNAMICALLY LIMITING ENERGY CONSUMED BY COOLING APPARATUS
94
Patent #:
Issue Dt:
03/18/2014
Application #:
13705477
Filing Dt:
12/05/2012
Title:
Finfet eDram Strap Connection Structure
95
Patent #:
Issue Dt:
07/28/2015
Application #:
13705717
Filing Dt:
12/05/2012
Publication #:
Pub Dt:
06/05/2014
Title:
BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
96
Patent #:
NONE
Issue Dt:
Application #:
13705738
Filing Dt:
12/05/2012
Publication #:
Pub Dt:
06/05/2014
Title:
MODELING MULTIPLE INTERACTIONS BETWEEN MULTIPLE LOCI
97
Patent #:
Issue Dt:
12/17/2013
Application #:
13705920
Filing Dt:
12/05/2012
Title:
GATE-ALL-AROUND CARBON NANOTUBE TRANSISTOR WITH SELECTIVELY DOPED SPACERS
98
Patent #:
Issue Dt:
03/29/2016
Application #:
13707003
Filing Dt:
12/06/2012
Publication #:
Pub Dt:
06/12/2014
Title:
PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS
99
Patent #:
Issue Dt:
02/04/2014
Application #:
13707058
Filing Dt:
12/06/2012
Publication #:
Pub Dt:
05/16/2013
Title:
SILICIDE CONTACTS HAVING DIFFERENT SHAPES ON REGIONS OF A SEMICONDUCTOR DEVICE
100
Patent #:
NONE
Issue Dt:
Application #:
13707864
Filing Dt:
12/07/2012
Publication #:
Pub Dt:
06/12/2014
Title:
ETCH RESISTANT RAISED ISOLATION FOR SEMICONDUCTOR DEVICES
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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