|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14616614
|
Filing Dt:
|
02/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
MULTI-FORMAT READ DRIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
14616855
|
Filing Dt:
|
02/09/2015
|
Publication #:
|
|
Pub Dt:
|
12/29/2016
| | | | |
Title:
|
PLANAR QUBITS HAVING INCREASED COHERENCE TIMES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
|
Application #:
|
14617314
|
Filing Dt:
|
02/09/2015
|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
Techniques to Form Uniform and Stable Silicide
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14617647
|
Filing Dt:
|
02/09/2015
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
NONVOLATILE MEMORY DEVICE USING SEMICONDUCTOR NANOCRYSTALS AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2016
|
Application #:
|
14618498
|
Filing Dt:
|
02/10/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
DEFECTIVE P-N JUNCTION FOR BACKGATED FULLY DEPLETED SILICON ON INSULATOR MOSFET
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14619152
|
Filing Dt:
|
02/11/2015
|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2016
|
Application #:
|
14620233
|
Filing Dt:
|
02/12/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
LOCALLY RAISED EPITAXY FOR IMPROVED CONTACT BY LOCAL SILICON CAPPING DURING TRENCH SILICIDE PROCESSINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2017
|
Application #:
|
14620273
|
Filing Dt:
|
02/12/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED CIRCUIT CHIP INTO A PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2015
|
Application #:
|
14621039
|
Filing Dt:
|
02/12/2015
|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
Title:
|
LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
|
Application #:
|
14621785
|
Filing Dt:
|
02/13/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2018
|
Application #:
|
14622997
|
Filing Dt:
|
02/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
MODIFIED TUNGSTEN SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
14623115
|
Filing Dt:
|
02/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
MODIFIED TUNGSTEN SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
14623720
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
III-V Device with Overlapped Extension Regions Using Replacement Gate
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
14623732
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
III-V FET Device with Overlapped Extension Regions Using Gate Last
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14623847
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14623916
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14624019
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14624026
|
Filing Dt:
|
02/17/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
EFFICIENT WAKEUP OF POWER GATED DOMAINS THROUGH CHARGE SHARING AND RECYCLING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
14624601
|
Filing Dt:
|
02/18/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
LASER ASHING OF POLYIMIDE FOR SEMICONDUCTOR MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2017
|
Application #:
|
14624907
|
Filing Dt:
|
02/18/2015
|
Publication #:
|
|
Pub Dt:
|
08/18/2016
| | | | |
Title:
|
SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFYING OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14626945
|
Filing Dt:
|
02/20/2015
|
Publication #:
|
|
Pub Dt:
|
06/11/2015
| | | | |
Title:
|
POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2016
|
Application #:
|
14628446
|
Filing Dt:
|
02/23/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
SAMPLE PLAN CREATION FOR OPTICAL PROXIMITY CORRECTION WITH MINIMAL NUMBER OF CLIPS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2017
|
Application #:
|
14630774
|
Filing Dt:
|
02/25/2015
|
Publication #:
|
|
Pub Dt:
|
08/25/2016
| | | | |
Title:
|
MITIGATING COLLISIONS IN A PHYSICAL SPACE DURING GAMING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
14632180
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2019
|
Application #:
|
14632194
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
METHOD AND DEVICE FOR COOLING A HEAT GENERATING COMPONENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14632313
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
06/18/2015
| | | | |
Title:
|
INTEGRATION OF DENSE AND VARIABLE PITCH FIN STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14633069
|
Filing Dt:
|
02/26/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
14633477
|
Filing Dt:
|
02/27/2015
|
Publication #:
|
|
Pub Dt:
|
09/03/2015
| | | | |
Title:
|
METHOD AND APPARATUS FOR PHYSICAL-AWARE HOLD VIOLATION FIXING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14634820
|
Filing Dt:
|
02/28/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
CIRCUIT TECHNIQUE TO ELECTRICALLY CHARACTERIZE BLOCK MASK SHIFTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2018
|
Application #:
|
14635005
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
METHOD TO PROTECT SENSITIVE DEVICES FROM ELECTROSTATIC DISCHARGE DAMAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
14635125
|
Filing Dt:
|
03/02/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
ELECTROMIGRATION TESTING OF INTERCONNECT ANALOGUES HAVING BOTTOM-CONNECTED SENSORY PINS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14636679
|
Filing Dt:
|
03/03/2015
|
Publication #:
|
|
Pub Dt:
|
09/08/2016
| | | | |
Title:
|
REMOVAL OF INTEGRATED CIRCUIT CHIPS FROM A WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14640047
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
MULTIPLE VOLUME ENCRYPTION OF STORAGE DEVICES USING SELF ENCRYPTING DRIVE (SED)
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2015
|
Application #:
|
14640698
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14640735
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2016
|
Application #:
|
14640851
|
Filing Dt:
|
03/06/2015
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
Title:
|
FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2016
|
Application #:
|
14641462
|
Filing Dt:
|
03/09/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
MULTI-FIN FINFETS WITH MERGED-FIN SOURCE/DRAINS AND REPLACEMENT GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2017
|
Application #:
|
14641917
|
Filing Dt:
|
03/09/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
DIAMOND SHAPED SOURCE DRAIN EPITAXY WITH UNDERLYING BUFFER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14642909
|
Filing Dt:
|
03/10/2015
|
Title:
|
FABRICATION OF A DEEP TRENCH MEMORY CELL
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14643224
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
STACKED CARBON-BASED FETS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14643323
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
OPTICAL DIE PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2018
|
Application #:
|
14643436
|
Filing Dt:
|
03/10/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14644416
|
Filing Dt:
|
03/11/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
PHOTO-PATTERNABLE DIELECTRIC MATERIALS AND FORMULATIONS AND METHODS OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14645350
|
Filing Dt:
|
03/11/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
BACKWARD COMPATIBLE HEAD FOR QUASI-STATIC TILTED READING AND/OR RECORDING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2018
|
Application #:
|
14645449
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14645477
|
Filing Dt:
|
03/12/2015
|
Publication #:
|
|
Pub Dt:
|
09/15/2016
| | | | |
Title:
|
INTEGRATED STRAINED FIN AND RELAXED FIN
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14656790
|
Filing Dt:
|
03/13/2015
|
Publication #:
|
|
Pub Dt:
|
10/01/2015
| | | | |
Title:
|
DIGITAL IC SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
14657864
|
Filing Dt:
|
03/13/2015
|
Publication #:
|
|
Pub Dt:
|
09/10/2015
| | | | |
Title:
|
CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2016
|
Application #:
|
14658587
|
Filing Dt:
|
03/16/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
OPTIMIZING PERFORMANCE OF A COMPUTER SYSTEM IN RESPONSE TO A SOFTWARE CHANGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14658975
|
Filing Dt:
|
03/16/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
CONTACT RESISTANCE REDUCTION IN FINFETS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2017
|
Application #:
|
14659793
|
Filing Dt:
|
03/17/2015
|
Publication #:
|
|
Pub Dt:
|
07/02/2015
| | | | |
Title:
|
VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2016
|
Application #:
|
14661383
|
Filing Dt:
|
03/18/2015
|
Title:
|
REBALANCING IN TWIN CELL MEMORY SCHEMES TO ENABLE MULTIPLE WRITES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2016
|
Application #:
|
14662468
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2016
|
Application #:
|
14662743
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14663256
|
Filing Dt:
|
03/19/2015
|
Publication #:
|
|
Pub Dt:
|
11/12/2015
| | | | |
Title:
|
INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14663754
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/28/2015
|
Application #:
|
14663806
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14664036
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
METHOD TO FABRICATE COPPER WIRING STRUCTURES AND STRUCTURES FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
14664435
|
Filing Dt:
|
03/20/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14665432
|
Filing Dt:
|
03/23/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2016
|
Application #:
|
14666469
|
Filing Dt:
|
03/24/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
SILICON-ON-NOTHING FINFETS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14666590
|
Filing Dt:
|
03/24/2015
|
Publication #:
|
|
Pub Dt:
|
07/09/2015
| | | | |
Title:
|
TAPE HEAD WITH TAPE-BEARING SURFACE EXHIBITING AN ARRAY OF PROTRUDING TOPOGRAPHIC FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
14668017
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
GLASS INTERPOSER WITH EMBEDDED THERMOELECTRIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2016
|
Application #:
|
14668018
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
07/16/2015
| | | | |
Title:
|
DENSE FINFET SRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2017
|
Application #:
|
14668031
|
Filing Dt:
|
03/25/2015
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
Title:
|
METHOD OF FORMING A GLASS INTERPOSER WITH THERMAL VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2016
|
Application #:
|
14669043
|
Filing Dt:
|
03/26/2015
|
Title:
|
MEMORY CELLS WITH READ ACCESS SCHEMES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2016
|
Application #:
|
14669775
|
Filing Dt:
|
03/26/2015
|
Title:
|
THERMAL HOT SPOT COOLING FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2016
|
Application #:
|
14671819
|
Filing Dt:
|
03/27/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
HIGH DENSITY TIMING BASED SERVO FORMAT FOR USE WITH TILTED TRANSDUCER ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14672157
|
Filing Dt:
|
03/28/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14672160
|
Filing Dt:
|
03/28/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
|
Application #:
|
14672865
|
Filing Dt:
|
03/30/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
HIGH VOLTAGE LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LDMOSFET) HAVING A DEEP FULLY DEPLETED DRAIN DRIFT REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2017
|
Application #:
|
14673185
|
Filing Dt:
|
03/30/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
VIA LEAKAGE AND BREAKDOWN TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2016
|
Application #:
|
14673926
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
MAINTAINING A CLUSTER OF VIRTUAL MACHINES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/2015
|
Application #:
|
14673958
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
FORMATION OF A HIGH ASPECT RATIO TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT RATIO TRENCH ISOLATION REGION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14674242
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
Title:
|
LIQUID CRYSTAL INTEGRATED CIRCUIT AND METHOD TO FABRICATE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2016
|
Application #:
|
14674571
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
PREDICTING PROCESS FAIL LIMITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2017
|
Application #:
|
14674859
|
Filing Dt:
|
03/31/2015
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
Title:
|
ANONYMOUS VEHICLE COMMUNICATION PROTOCOL IN VEHICLE-TO-VEHICLE NETWORKS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
14677303
|
Filing Dt:
|
04/02/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14678024
|
Filing Dt:
|
04/03/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
FINFET STRUCTURES HAVING SILICON GERMANIUM AND SILICON CHANNELS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2016
|
Application #:
|
14680328
|
Filing Dt:
|
04/07/2015
|
Title:
|
DEFECT REDUCTION WITH ROTATED DOUBLE ASPECT RATIO TRAPPING
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14681215
|
Filing Dt:
|
04/08/2015
|
Publication #:
|
|
Pub Dt:
|
07/30/2015
| | | | |
Title:
|
ENGINEERING MULTIPLE THRESHOLD VOLTAGES IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14683995
|
Filing Dt:
|
04/10/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
SPLIT FLEX CABLE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14684533
|
Filing Dt:
|
04/13/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
DEEP TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2016
|
Application #:
|
14685061
|
Filing Dt:
|
04/13/2015
|
Publication #:
|
|
Pub Dt:
|
10/13/2016
| | | | |
Title:
|
ELECTRONIC PACKAGE THAT INCLUDES A PLURALITY OF INTEGRATED CIRCUIT DEVICES BONDED IN A THREE-DIMENSIONAL STACK ARRANGEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14685736
|
Filing Dt:
|
04/14/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
Automatic Analytical Cloud Scaling of Hardware Using Resource Sub-Cloud
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14685973
|
Filing Dt:
|
04/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
SEPARATING BONDED WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2016
|
Application #:
|
14686260
|
Filing Dt:
|
04/14/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING SOURCE/DRAIN EPITAXIAL OVERGROWTH FOR FORMING SELF-ALIGNED CONTACTS WITHOUT SPACER LOSS AND A SEMICONDUCTOR DEVICE FORMED BY SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2017
|
Application #:
|
14686904
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
WHOLE WAFER EDGE SEAL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
14686972
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
BARRIER TRENCH STRUCTURE AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2017
|
Application #:
|
14687002
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
10/20/2016
| | | | |
Title:
|
ON CHIP ANTENNA WITH OPENING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2016
|
Application #:
|
14687049
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
ALTERING CAPACITANCE OF MIM CAPACITOR HAVING REACTIVE LAYER THEREIN
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
14687050
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
DATA STORAGE TAPE WITH RANDOM ACCESS DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2016
|
Application #:
|
14687489
|
Filing Dt:
|
04/15/2015
|
Publication #:
|
|
Pub Dt:
|
10/15/2015
| | | | |
Title:
|
CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/2016
|
Application #:
|
14688027
|
Filing Dt:
|
04/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14688215
|
Filing Dt:
|
04/16/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14689463
|
Filing Dt:
|
04/17/2015
|
Publication #:
|
|
Pub Dt:
|
08/06/2015
| | | | |
Title:
|
ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
14691124
|
Filing Dt:
|
04/20/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
Laser Doping of Crystalline Semiconductors Using a Dopant-Containing Amorphous Silicon Stack for Dopant Source and Passivation
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14691326
|
Filing Dt:
|
04/20/2015
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
Title:
|
FORMATION OF METAL NANOSPHERES AND MICROSPHERES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2017
|
Application #:
|
14692881
|
Filing Dt:
|
04/22/2015
|
Publication #:
|
|
Pub Dt:
|
10/27/2016
| | | | |
Title:
|
HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2017
|
Application #:
|
14694265
|
Filing Dt:
|
04/23/2015
|
Publication #:
|
|
Pub Dt:
|
09/24/2015
| | | | |
Title:
|
BURIED WAVEGUIDE PHOTODETECTOR
|
|