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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14854
Page 31 of 149
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1
Patent #:
7472320
Issue Dt:
12/30/2008
Application #:
10708316
Filing Dt:
02/24/2004
Publication #:
US20050188289
Pub Dt:
08/25/2005
Title:
Autonomous Self-Monitoring and Corrective Operation of an Integrated Circuit
2
Patent #:
7120732
Issue Dt:
10/10/2006
Application #:
10708317
Filing Dt:
02/24/2004
Publication #:
US20050185436
Pub Dt:
08/25/2005
Title:
CONTENT ADDRESSABLE MEMORY STRUCTURE
3
Patent #:
7425754
Issue Dt:
09/16/2008
Application #:
10708340
Filing Dt:
02/25/2004
Publication #:
US20050184359
Pub Dt:
08/25/2005
Title:
STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR
4
Patent #:
7923782
Issue Dt:
04/12/2011
Application #:
10708378
Filing Dt:
02/27/2004
Publication #:
US20050189589
Pub Dt:
09/01/2005
Title:
HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS
5
Patent #:
7543203
Issue Dt:
06/02/2009
Application #:
10708382
Filing Dt:
02/27/2004
Publication #:
US20050204244
Pub Dt:
09/15/2005
Title:
LSSD-COMPATIBLE EDGE-TRIGGERED SHIFT REGISTER LATCH
6
Patent #:
7205206
Issue Dt:
04/17/2007
Application #:
10708430
Filing Dt:
03/03/2004
Publication #:
US20050194699
Pub Dt:
09/08/2005
Title:
METHOD OF FABRICATING MOBILITY ENHANCED CMOS DEVICES
7
Patent #:
7105391
Issue Dt:
09/12/2006
Application #:
10708451
Filing Dt:
03/04/2004
Publication #:
US20050196912
Pub Dt:
09/08/2005
Title:
PLANAR PEDESTAL MULTI GATE DEVICE
8
Patent #:
7173338
Issue Dt:
02/06/2007
Application #:
10708486
Filing Dt:
03/06/2004
Publication #:
US20050194689
Pub Dt:
09/08/2005
Title:
SUPPRESSION OF LOCALIZED METAL PRECIPITATE FORMATION AND CORRESPONDING METALLIZATION DEPLETION IN SEMICONDUCTOR PROCESSING
9
Patent #:
NONE
Issue Dt:
Application #:
10708515
Filing Dt:
03/09/2004
Publication #:
US20050202326
Pub Dt:
09/15/2005
Title:
OPTIMIZED PLACEMENT OF SUB-RESOLUTION ASSIST FEATURES WITHIN TWO-DIMENSIONAL ENVIRONMENTS
10
Patent #:
7115343
Issue Dt:
10/03/2006
Application #:
10708535
Filing Dt:
03/10/2004
Publication #:
US20050202321
Pub Dt:
09/15/2005
Title:
PLIANT SRAF FOR IMPROVED PERFORMANCE AND MANUFACTURABILITY
11
Patent #:
6940149
Issue Dt:
09/06/2005
Application #:
10708563
Filing Dt:
03/11/2004
Publication #:
US20050199907
Pub Dt:
09/15/2005
Title:
STRUCTURE AND METHOD OF FORMING A BIPOLAR TRANSISTOR HAVING A VOID BETWEEN EMITTER AND EXTRINSIC BASE
12
Patent #:
NONE
Issue Dt:
Application #:
10708648
Filing Dt:
03/17/2004
Publication #:
US20050208742
Pub Dt:
09/22/2005
Title:
OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING
13
Patent #:
7005665
Issue Dt:
02/28/2006
Application #:
10708667
Filing Dt:
03/18/2004
Publication #:
US20050208699
Pub Dt:
09/22/2005
Title:
PHASE CHANGE MEMORY CELL ON SILICON-ON INSULATOR SUBSTRATE
14
Patent #:
7124396
Issue Dt:
10/17/2006
Application #:
10708684
Filing Dt:
03/18/2004
Publication #:
US20050210436
Pub Dt:
09/22/2005
Title:
ALTERNATING PHASE-SHIFT MASK RULE COMPLIANT IC DESIGN
15
Patent #:
7061793
Issue Dt:
06/13/2006
Application #:
10708713
Filing Dt:
03/19/2004
Publication #:
US20050207210
Pub Dt:
09/22/2005
Title:
APPARATUS AND METHOD FOR SMALL SIGNAL SENSING IN AN SRAM CELL UTILIZING PFET ACCESS DEVICES
16
Patent #:
7109093
Issue Dt:
09/19/2006
Application #:
10708735
Filing Dt:
03/22/2004
Publication #:
US20050208781
Pub Dt:
09/22/2005
Title:
CRACKSTOP WITH RELEASE LAYER FOR CRACK CONTROL IN SEMICONDUCTORS
17
Patent #:
6936910
Issue Dt:
08/30/2005
Application #:
10708743
Filing Dt:
03/23/2004
Publication #:
US20040222486
Pub Dt:
11/11/2004
Title:
BICMOS TECHNOLOGY ON SOI SUBSTRATES
18
Patent #:
6881635
Issue Dt:
04/19/2005
Application #:
10708746
Filing Dt:
03/23/2004
Title:
STRAINED SILICON NMOS DEVICES WITH EMBEDDED SOURCE/DRAIN
19
Patent #:
6998684
Issue Dt:
02/14/2006
Application #:
10708907
Filing Dt:
03/31/2004
Publication #:
US20050224875
Pub Dt:
10/13/2005
Title:
HIGH MOBILITY PLANE CMOS SOI
20
Patent #:
7115920
Issue Dt:
10/03/2006
Application #:
10709076
Filing Dt:
04/12/2004
Publication #:
US20050224890
Pub Dt:
10/13/2005
Title:
FINFET TRANSISTOR AND CIRCUIT
21
Patent #:
6888221
Issue Dt:
05/03/2005
Application #:
10709114
Filing Dt:
04/14/2004
Title:
BICMOS TECHNOLOGY ON SIMOX WAFERS
22
Patent #:
7239006
Issue Dt:
07/03/2007
Application #:
10709115
Filing Dt:
04/14/2004
Publication #:
US20050230785
Pub Dt:
10/20/2005
Title:
RESISTOR TUNING
23
Patent #:
7262084
Issue Dt:
08/28/2007
Application #:
10709129
Filing Dt:
04/15/2004
Publication #:
US20050233565
Pub Dt:
10/20/2005
Title:
METHODS FOR MANUFACTURING A FINFET USING A CONVENTIONAL WAFER AND APPARATUS MANUFACTURED THEREFROM
24
Patent #:
NONE
Issue Dt:
Application #:
10709204
Filing Dt:
04/21/2004
Publication #:
US20050239284
Pub Dt:
10/27/2005
Title:
WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE
25
Patent #:
7087940
Issue Dt:
08/08/2006
Application #:
10709220
Filing Dt:
04/22/2004
Publication #:
US20050236645
Pub Dt:
10/27/2005
Title:
STRUCTURE AND METHOD OF FORMING BIPOLAR TRANSISTOR HAVING A SELF-ALIGNED RAISED EXTRINSIC BASE USING SELF-ALIGNED ETCH STOP LAYER
26
Patent #:
6972443
Issue Dt:
12/06/2005
Application #:
10709222
Filing Dt:
04/22/2004
Publication #:
US20050236647
Pub Dt:
10/27/2005
Title:
STRUCTURE AND METHOD OF FORMING A BIPOLAR TRANSISTOR HAVING A SELF-ALIGNED RAISED EXTRINSIC BASE USING A LINK-UP REGION FORMED FROM AN OPENING THEREIN
27
Patent #:
7504693
Issue Dt:
03/17/2009
Application #:
10709239
Filing Dt:
04/23/2004
Publication #:
US20050236668
Pub Dt:
10/27/2005
Title:
DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI CMOS DEVICES BY GATE STRESS ENGINEERING
28
Patent #:
NONE
Issue Dt:
Application #:
10709285
Filing Dt:
04/27/2004
Publication #:
US20040256698
Pub Dt:
12/23/2004
Title:
METHOD FOR IMAGE REVERSAL OF IMPLANT RESIST USING A SINGLE PHOTOLITHOGRAPHY EXPOSURE AND STRUCTURES FORMED THEREBY
29
Patent #:
7260790
Issue Dt:
08/21/2007
Application #:
10709292
Filing Dt:
04/27/2004
Publication #:
US20060150130
Pub Dt:
07/06/2006
Title:
INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS
30
Patent #:
7143371
Issue Dt:
11/28/2006
Application #:
10709293
Filing Dt:
04/27/2004
Publication #:
US20050240839
Pub Dt:
10/27/2005
Title:
CRITICAL AREA COMPUTATION OF COMPOSITE FAULT MECHANISMS USING VORONOI DIAGRAMS
31
Patent #:
NONE
Issue Dt:
Application #:
10709294
Filing Dt:
04/27/2004
Publication #:
US20050240884
Pub Dt:
10/27/2005
Title:
VIA SPACING VIOLATION CORRECTION METHOD, SYSTEM AND PROGRAM PRODUCT
32
Patent #:
6965808
Issue Dt:
11/15/2005
Application #:
10709319
Filing Dt:
04/28/2004
Publication #:
US20050246044
Pub Dt:
11/03/2005
Title:
SYSTEM AND METHOD FOR OPTIMIZING METROLOGY SAMPLING IN APC APPLICATIONS
33
Patent #:
7056773
Issue Dt:
06/06/2006
Application #:
10709323
Filing Dt:
04/28/2004
Publication #:
US20050245009
Pub Dt:
11/03/2005
Title:
BACKGATED FINFET HAVING DIFERENT OXIDE THICKNESSES
34
Patent #:
7110195
Issue Dt:
09/19/2006
Application #:
10709326
Filing Dt:
04/28/2004
Publication #:
US20050243452
Pub Dt:
11/03/2005
Title:
MONOLITHIC HARD PELLICLE
35
Patent #:
7353477
Issue Dt:
04/01/2008
Application #:
10709327
Filing Dt:
04/28/2004
Publication #:
US20050243869
Pub Dt:
11/03/2005
Title:
METHOD OF IDENTIFYING PATHS WITH DELAYS DOMINATED BY A PARTICULAR FACTOR
36
Patent #:
7005371
Issue Dt:
02/28/2006
Application #:
10709357
Filing Dt:
04/29/2004
Publication #:
US20050245063
Pub Dt:
11/03/2005
Title:
METHOD FOR FORMING SUSPENDED TRANSMISSION LINE STRUCTURES IN BACK END OF LINE PROCESSING
37
Patent #:
7089143
Issue Dt:
08/08/2006
Application #:
10709361
Filing Dt:
04/29/2004
Publication #:
US20050246116
Pub Dt:
11/03/2005
Title:
METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGRATED CIRCUIT
38
Patent #:
7280939
Issue Dt:
10/09/2007
Application #:
10709362
Filing Dt:
04/29/2004
Publication #:
US20050246117
Pub Dt:
11/03/2005
Title:
SYSTEM AND METHOD OF ANALYZING TIMING EFFECTS OF SPATIAL DISTRIBUTION IN CIRCUITS
39
Patent #:
7009237
Issue Dt:
03/07/2006
Application #:
10709450
Filing Dt:
05/06/2004
Publication #:
US20050247966
Pub Dt:
11/10/2005
Title:
OUT OF THE BOX VERTICAL TRANSISTOR FOR EDRAM ON SOI
40
Patent #:
7497959
Issue Dt:
03/03/2009
Application #:
10709514
Filing Dt:
05/11/2004
Publication #:
US20050255386
Pub Dt:
11/17/2005
Title:
METHODS AND STRUCTURES FOR PROTECTING ONE AREA WHILE PROCESSING ANOTHER AREA ON A CHIP
41
Patent #:
7129169
Issue Dt:
10/31/2006
Application #:
10709534
Filing Dt:
05/12/2004
Publication #:
US20050255699
Pub Dt:
11/17/2005
Title:
METHOD FOR CONTROLLING VOIDING AND BRIDGING IN SILICIDE FORMATION
42
Patent #:
7235487
Issue Dt:
06/26/2007
Application #:
10709562
Filing Dt:
05/13/2004
Publication #:
US20050253265
Pub Dt:
11/17/2005
Title:
METAL SEED LAYER DEPOSITION
43
Patent #:
NONE
Issue Dt:
Application #:
10709596
Filing Dt:
05/17/2004
Publication #:
US20040194813
Pub Dt:
10/07/2004
Title:
PROCESS FOR REMOVING DOPANT IONS FROM A SUBSTRATE
44
Patent #:
7118995
Issue Dt:
10/10/2006
Application #:
10709644
Filing Dt:
05/19/2004
Publication #:
US20050260826
Pub Dt:
11/24/2005
Title:
YIELD IMPROVEMENT IN SILICON-GERMANIUM EPITAXIAL GROWTH
45
Patent #:
7091081
Issue Dt:
08/15/2006
Application #:
10709673
Filing Dt:
05/21/2004
Publication #:
US20050260859
Pub Dt:
11/24/2005
Title:
METHOD FOR PATTERNING A SEMICONDUCTOR REGION
46
Patent #:
7145218
Issue Dt:
12/05/2006
Application #:
10709692
Filing Dt:
05/24/2004
Publication #:
US20050258513
Pub Dt:
11/24/2005
Title:
THIN-FILM RESISTOR AND METHOD OF MANUFACTURING THE SAME
47
Patent #:
6943409
Issue Dt:
09/13/2005
Application #:
10709699
Filing Dt:
05/24/2004
Title:
TRENCH OPTICAL DEVICE
48
Patent #:
7078814
Issue Dt:
07/18/2006
Application #:
10709722
Filing Dt:
05/25/2004
Publication #:
US20050275104
Pub Dt:
12/15/2005
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AIR GAPS AND THE STRUCTURE SO FORMED
49
Patent #:
7084483
Issue Dt:
08/01/2006
Application #:
10709727
Filing Dt:
05/25/2004
Publication #:
US20050263850
Pub Dt:
12/01/2005
Title:
TRENCH TYPE BURIED ON-CHIP PRECISION PROGRAMMABLE RESISTOR
50
Patent #:
7253650
Issue Dt:
08/07/2007
Application #:
10709729
Filing Dt:
05/25/2004
Publication #:
US20050267706
Pub Dt:
12/01/2005
Title:
INCREASE PRODUCTIVITY AT WAFER TEST USING PROBE RETEST DATA ANALYSIS
51
Patent #:
7198872
Issue Dt:
04/03/2007
Application #:
10709733
Filing Dt:
05/25/2004
Publication #:
US20050266317
Pub Dt:
12/01/2005
Title:
LIGHT SCATTERING EUVL MASK
52
Patent #:
7015150
Issue Dt:
03/21/2006
Application #:
10709747
Filing Dt:
05/26/2004
Publication #:
US20050266698
Pub Dt:
12/01/2005
Title:
EXPOSED PORE SEALING POST PATTERNING
53
Patent #:
7726016
Issue Dt:
06/01/2010
Application #:
10709752
Filing Dt:
05/26/2004
Publication #:
US20040222015
Pub Dt:
11/11/2004
Title:
MANUFACTURING METHOD OF PRINTED CIRCUIT BOARD
54
Patent #:
7373567
Issue Dt:
05/13/2008
Application #:
10709754
Filing Dt:
05/26/2004
Publication #:
US20050278588
Pub Dt:
12/15/2005
Title:
A SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA
55
Patent #:
6961403
Issue Dt:
11/01/2005
Application #:
10709804
Filing Dt:
05/28/2004
Title:
PROGRAMMABLE FREQUENCY DIVIDER WITH SYMMETRICAL OUTPUT
56
Patent #:
7282404
Issue Dt:
10/16/2007
Application #:
10709829
Filing Dt:
06/01/2004
Publication #:
US20050274987
Pub Dt:
12/15/2005
Title:
INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME
57
Patent #:
7211507
Issue Dt:
05/01/2007
Application #:
10709865
Filing Dt:
06/02/2004
Publication #:
US20050269703
Pub Dt:
12/08/2005
Title:
PE-ALD OF TAN DIFFUSION BARRIER REGION ON LOW-K MATERIALS
58
Patent #:
7426555
Issue Dt:
09/16/2008
Application #:
10709867
Filing Dt:
06/02/2004
Publication #:
US20050273519
Pub Dt:
12/08/2005
Title:
METHOD, SYSTEM, AND STORAGE MEDIUM FOR PROVIDING CONTINUOUS COMMUNICATION BETWEEN PROCESS EQUIPMENT AND AN AUTOMATED MATERIAL HANDLING SYSTEM
59
Patent #:
7041553
Issue Dt:
05/09/2006
Application #:
10709869
Filing Dt:
06/02/2004
Publication #:
US20050272201
Pub Dt:
12/08/2005
Title:
IMPROVED PROCESS FOR FORMING A BURIED PLATE
60
Patent #:
7217988
Issue Dt:
05/15/2007
Application #:
10709905
Filing Dt:
06/04/2004
Publication #:
US20050269664
Pub Dt:
12/08/2005
Title:
BIPOLAR TRANSISTOR WITH ISOLATION AND DIRECT CONTACTS
61
Patent #:
7301752
Issue Dt:
11/27/2007
Application #:
10709907
Filing Dt:
06/04/2004
Publication #:
US20050272219
Pub Dt:
12/08/2005
Title:
FORMATION OF METAL-INSULATOR-METAL CAPACITOR SIMULTANEOUSLY WITH ALUMINUM METAL WIRING LEVEL USING A HARDMASK
62
Patent #:
6965171
Issue Dt:
11/15/2005
Application #:
10709931
Filing Dt:
06/07/2004
Publication #:
US20050269716
Pub Dt:
12/08/2005
Title:
METHOD AND STRUCTURE FOR SELECTIVE THERMAL PASTE DEPOSITION AND RETENTION ON INTEGRATED CIRCUIT CHIP MODULES
63
Patent #:
7403884
Issue Dt:
07/22/2008
Application #:
10709949
Filing Dt:
06/08/2004
Publication #:
US20050273307
Pub Dt:
12/08/2005
Title:
TRANSIENT SIMULATION USING ADAPTIVE PIECEWISE CONSTANT MODEL
64
Patent #:
7037794
Issue Dt:
05/02/2006
Application #:
10709963
Filing Dt:
06/09/2004
Publication #:
US20050277271
Pub Dt:
12/15/2005
Title:
RAISED STI PROCESS FOR MULTIPLE GATE OX AND SIDEWALL PROTECTION ON STRAINED SI/SGOI STRUCTURE WITH ELEVATED SOURCE/DRAIN
65
Patent #:
7084461
Issue Dt:
08/01/2006
Application #:
10709998
Filing Dt:
06/11/2004
Publication #:
US20050275040
Pub Dt:
12/15/2005
Title:
BACK GATE FINFET SRAM
66
Patent #:
7071072
Issue Dt:
07/04/2006
Application #:
10710001
Filing Dt:
06/11/2004
Publication #:
US20050277263
Pub Dt:
12/15/2005
Title:
FORMING SHALLOW TRENCH ISOLATION WITHOUT THE USE OF CMP
67
Patent #:
7009265
Issue Dt:
03/07/2006
Application #:
10710007
Filing Dt:
06/11/2004
Publication #:
US20050275045
Pub Dt:
12/15/2005
Title:
LOW CAPACITANCE FET FOR OPERATION AT SUBTHRESHOLD VOLTAGES
68
Patent #:
7303994
Issue Dt:
12/04/2007
Application #:
10710034
Filing Dt:
06/14/2004
Publication #:
US20050277266
Pub Dt:
12/15/2005
Title:
PROCESS FOR INTERFACIAL ADHESION IN LAMINATE STRUCTURES THROUGH PATTERNED ROUGHING OF A SURFACE
69
Patent #:
7223653
Issue Dt:
05/29/2007
Application #:
10710045
Filing Dt:
06/15/2004
Publication #:
US20050277264
Pub Dt:
12/15/2005
Title:
IMPROVED PROCESS FOR FORMING A BURIED PLATE
70
Patent #:
7078710
Issue Dt:
07/18/2006
Application #:
10710051
Filing Dt:
06/15/2004
Publication #:
US20050274910
Pub Dt:
12/15/2005
Title:
ION BEAM SYSTEM
71
Patent #:
7118986
Issue Dt:
10/10/2006
Application #:
10710060
Filing Dt:
06/16/2004
Publication #:
US20050282392
Pub Dt:
12/22/2005
Title:
STI FORMATION IN SEMICONDUCTOR DEVICE INCLUDING SOI AND BULK SILICON REGIONS
72
Patent #:
7223669
Issue Dt:
05/29/2007
Application #:
10710061
Filing Dt:
06/16/2004
Publication #:
US20050282393
Pub Dt:
12/22/2005
Title:
STRUCTURE AND METHOD FOR COLLAR SELF-ALIGNED TO BURIED PLATE
73
Patent #:
7023064
Issue Dt:
04/04/2006
Application #:
10710063
Filing Dt:
06/16/2004
Publication #:
US20050280099
Pub Dt:
12/22/2005
Title:
TEMPERATURE STABLE METAL NITRIDE GATE ELECTRODE
74
Patent #:
7584077
Issue Dt:
09/01/2009
Application #:
10710113
Filing Dt:
06/18/2004
Publication #:
US20040221250
Pub Dt:
11/04/2004
Title:
PHYSICAL DESIGN CHARACTERIZATION SYSTEM
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7180187
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02/20/2007
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10710147
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06/22/2004
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Pub Dt:
12/22/2005
Title:
INTERLAYER CONNECTOR FOR PREVENTING DELAMINATION OF SEMICONDUCTOR DEVICE
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06/23/2004
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Pub Dt:
12/29/2005
Title:
METHODS AND SYSTEMS FOR LAYOUT AND ROUTING USING ALTERNATING APERTURE PHASE SHIFT MASKS
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Pub Dt:
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Title:
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Filing Dt:
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Pub Dt:
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Title:
STRUCTURE AND METHOD TO IMPROVE SRAM STABILITY WITHOUT INCREASING CELL AREA OR OFF CURRENT
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Pub Dt:
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Title:
SYSTEM FOR COLORING A PARTIALLY COLORED DESIGN IN AN ALTERNATING PHASE SHIFT MASK
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7404874
Issue Dt:
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Filing Dt:
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Pub Dt:
12/29/2005
Title:
METHOD AND APPARATUS FOR TREATING WAFER EDGE REGION WITH TOROIDAL PLASMA
81
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Issue Dt:
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Filing Dt:
06/28/2004
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Pub Dt:
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Title:
PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE
82
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Issue Dt:
10/30/2007
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Filing Dt:
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Pub Dt:
12/29/2005
Title:
STRUCTURES AND METHODS FOR MANUFACTURING P-TYPE MOSFET WITHGRADED EMBEDDED SILICON-GERMANIUM SOURCE-DRAIN AND/OR EXTENSION
83
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NONE
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10710245
Filing Dt:
06/29/2004
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Pub Dt:
12/29/2005
Title:
DOPED NITRIDE FILM, DOPED OXIDE FILM AND OTHER DOPED FILMS
84
Patent #:
6893936
Issue Dt:
05/17/2005
Application #:
10710255
Filing Dt:
06/29/2004
Title:
METHOD OF FORMING STRAINED SI/SIGE ON INSULATOR WITH SILICON GERMANIUM BUFFER
85
Patent #:
7102204
Issue Dt:
09/05/2006
Application #:
10710256
Filing Dt:
06/29/2004
Publication #:
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Pub Dt:
12/29/2005
Title:
INTEGRATED SOI FINGERED DECOUPLING CAPACITOR
86
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8669145
Issue Dt:
03/11/2014
Application #:
10710272
Filing Dt:
06/30/2004
Publication #:
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Pub Dt:
01/19/2006
Title:
METHOD AND STRUCTURE FOR STRAINED FINFET DEVICES
87
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7091069
Issue Dt:
08/15/2006
Application #:
10710273
Filing Dt:
06/30/2004
Publication #:
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Pub Dt:
01/05/2006
Title:
ULTRA THIN BODY FULLY-DEPLETED SOI MOSFETS
88
Patent #:
6972461
Issue Dt:
12/06/2005
Application #:
10710274
Filing Dt:
06/30/2004
Title:
CHANNEL MOSFET WITH STRAINED SILICON CHANNEL ON STRAINED SIGE
89
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7094634
Issue Dt:
08/22/2006
Application #:
10710277
Filing Dt:
06/30/2004
Publication #:
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Pub Dt:
01/05/2006
Title:
STRUCTURE AND METHOD FOR MANUFACTURING PLANAR SOI SUBSTRATE WITH MULTIPLE ORIENTATIONS
90
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6906905
Issue Dt:
06/14/2005
Application #:
10710283
Filing Dt:
06/30/2004
Title:
MICRO ELECTRO-MECHANICAL VARIABLE CAPACITOR
91
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7249206
Issue Dt:
07/24/2007
Application #:
10710414
Filing Dt:
07/08/2004
Publication #:
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Pub Dt:
11/25/2004
Title:
DYNAMIC MEMORY ALLOCATION BETWEEN INBOUND AND OUTBOUND BUFFERS IN A PROTOCOL HANDLER
92
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7084667
Issue Dt:
08/01/2006
Application #:
10710453
Filing Dt:
07/13/2004
Publication #:
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Pub Dt:
01/19/2006
Title:
LOW LEAKAGE MONOTONIC CMOS LOGIC
93
Patent #:
7071559
Issue Dt:
07/04/2006
Application #:
10710510
Filing Dt:
07/16/2004
Publication #:
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Pub Dt:
01/19/2006
Title:
DESIGN OF BEOL PATTERNS TO REDUCE THE STRESSES ON STRUCTURES BELOW CHIP BONDPADS
94
Patent #:
7176583
Issue Dt:
02/13/2007
Application #:
10710562
Filing Dt:
07/21/2004
Publication #:
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Pub Dt:
01/26/2006
Title:
DAMASCENE PATTERNING OF BARRIER LAYER METAL FOR C4 SOLDER BUMPS
95
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7601646
Issue Dt:
10/13/2009
Application #:
10710566
Filing Dt:
07/21/2004
Publication #:
US20060019443
Pub Dt:
01/26/2006
Title:
TOP-OXIDE-EARLY PROCESS AND ARRAY TOP OXIDE PLANARIZATION
96
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7384829
Issue Dt:
06/10/2008
Application #:
10710608
Filing Dt:
07/23/2004
Publication #:
US20060019462
Pub Dt:
01/26/2006
Title:
PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE
97
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7404174
Issue Dt:
07/22/2008
Application #:
10710648
Filing Dt:
07/27/2004
Publication #:
US20060023932
Pub Dt:
02/02/2006
Title:
METHOD FOR GENERATING A SET OF TEST PATTERNS FOR AN OPTICAL PROXIMITY CORRECTION ALGORITHM
98
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7457097
Issue Dt:
11/25/2008
Application #:
10710653
Filing Dt:
07/27/2004
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Pub Dt:
02/02/2006
Title:
PRESSURE ASSISTED WAFER HOLDING APPARATUS AND CONTROL METHOD
99
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7074666
Issue Dt:
07/11/2006
Application #:
10710675
Filing Dt:
07/28/2004
Publication #:
US20060024940
Pub Dt:
02/02/2006
Title:
BORDERLESS CONTACT STRUCTURES
100
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7259420
Issue Dt:
08/21/2007
Application #:
10710680
Filing Dt:
07/28/2004
Publication #:
US20060022253
Pub Dt:
02/02/2006
Title:
MULTIPLE-GATE DEVICE WITH FLOATING BACK GATE
Assignors
1
GLOBALFOUNDRIES U.S. 2 LLC
Exec Dt:
09/10/2015
2
GLOBALFOUNDRIES U.S. INC.
Exec Dt:
09/10/2015
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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