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06/07/2011
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04/15/2005
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10/19/2006
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10/20/2009
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11107611
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10/19/2006
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HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT
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09/25/2007
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11108012
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04/15/2005
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10/19/2006
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HYBRID BULK-SOI 6T-SRAM CELL FOR IMPROVED CELL STABILITY AND PERFORMANCE
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06/09/2009
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11108392
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04/18/2005
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10/19/2006
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ELECTROMAGNETIC RESPONSE MODEL WITH IMPROVED HIGH FREQUENCY STABILITY
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01/27/2009
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11111055
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04/20/2005
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10/26/2006
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NANOPOROUS MEDIA WITH LAMELLAR STRUCTURES
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12/04/2007
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11111454
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04/21/2005
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10/26/2006
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ALIGNMENT INSENSITIVE D-CACHE CELL
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10/06/2009
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11111592
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04/21/2005
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10/26/2006
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USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
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11/06/2007
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11112527
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04/22/2005
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10/26/2006
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Title:
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METHOD TO DIFFERENTIALLY CONTROL LC VOLTAGE-CONTROLLED OSCILLATORS
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03/25/2008
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11112820
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04/22/2005
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10/26/2006
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Title:
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STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF
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08/21/2007
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11115606
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04/27/2005
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11/02/2006
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METHOD AND APPARATUS TO DISABLE COMPACTION OF TEST RESPONSES IN DETERMINISTIC TEST-SET EMBEDDING-BASED BIST
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12/16/2008
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11116053
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04/27/2005
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11/02/2006
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FIELD EFFECT TRANSISTOR WITH MIXED-CRYSTAL-ORIENTATION CHANNEL AND SOURCE/DRAIN REGIONS
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10/30/2007
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11116625
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04/28/2005
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11/02/2006
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METHODS AND APPARATUS FOR REDUCING MEMORY ERRORS
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06/10/2008
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11116700
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04/27/2005
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11/02/2006
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Title:
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MEMORY AND LOGIC DEVICES USING ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICES
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04/01/2008
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11117276
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04/27/2005
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11/02/2006
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Title:
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ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
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11/04/2008
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11118521
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04/29/2005
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11/02/2006
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Title:
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STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS
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12/02/2008
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11119505
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04/29/2005
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11/02/2006
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Title:
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METHOD FOR PERFORMING HIGH SPEED SERIAL LINK OUTPUT STAGE HAVING SELF ADAPTATION FOR VARIOUS IMPAIRMENTS
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04/10/2007
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11121454
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05/04/2005
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10/20/2005
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Title:
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SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION
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12/10/2013
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11122152
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05/04/2005
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09/08/2005
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Title:
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Method and apparatus for dynamic manipulation and dispersion in photonic crystal devices
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07/31/2007
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11122193
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05/04/2005
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12/01/2005
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Title:
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HYBRID PLANAR AND FINFET CMOS DEVICES
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NONE
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11123086
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05/06/2005
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11/09/2006
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Title:
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Method and structure for Peltier-controlled phase change memory
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NONE
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11123117
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05/06/2005
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09/15/2005
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Title:
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Method for electroplating on resistive substrates
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09/23/2008
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11124247
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05/06/2005
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10/06/2005
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Title:
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HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
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10/21/2008
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11124324
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05/06/2005
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09/08/2005
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Title:
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METHOD OF CREATING DEEP TRENCH CAPACITOR USING A P+ METAL ELECTRODE
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NONE
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11124325
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05/06/2005
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11/09/2006
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Title:
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Field effect transistor device including an array of channel elements and methods for forming
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05/27/2008
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11124978
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05/09/2005
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09/15/2005
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Title:
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SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK
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10/30/2007
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11125063
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05/09/2005
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10/06/2005
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Title:
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DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
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03/17/2009
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11125499
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05/10/2005
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11/16/2006
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Title:
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APPARATUS AND METHODS FOR CONSTRUCTING BALANCED CHIP PACKAGES TO REDUCE THERMALLY INDUCED MECHANICAL STRAIN
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09/05/2006
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11125549
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05/10/2005
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09/15/2005
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Title:
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METHOD TO GENERATE POROUS ORGANIC DIELECTRIC
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11/06/2007
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11125696
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05/10/2005
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11/16/2006
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Title:
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METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS
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04/08/2008
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11125971
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05/09/2005
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11/09/2006
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PHOTORESISTS FOR VISIBLE LIGHT IMAGING
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01/22/2008
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11126675
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05/11/2005
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09/29/2005
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METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
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12/18/2007
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11127616
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05/12/2005
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11/16/2006
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Title:
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METHOD OF INSPECTING INTEGRATED CIRCUITS DURING FABRICATION
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06/17/2008
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11128069
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05/12/2005
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11/16/2006
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INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS
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12/11/2007
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11129325
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05/16/2005
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09/15/2005
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Title:
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STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING THE DIELECTRIC CHAMBER
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04/08/2008
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11129784
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05/16/2005
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01/12/2006
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GENIE: A METHOD FOR CLASSIFICATION AND GRAPHICAL DISPLAY OF NEGATIVE SLACK TIMING TEST FAILURES
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12/04/2007
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11129785
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05/16/2005
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01/19/2006
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NEGATIVE SLACK RECOVERABILITY FACTOR - A NET WEIGHT TO ENHANCE TIMING CLOSURE BEHAVIOR
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05/13/2008
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11130078
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05/16/2005
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11/16/2006
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PROCESS FOR PREPARING ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTILAYER HARDMASK SCHEME
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11/28/2006
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11130313
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05/16/2005
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11/16/2006
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Title:
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METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR HAVING UNIPOLAR CHARACTERISTICS
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04/03/2007
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11131534
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05/18/2005
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11/23/2006
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CIRCUITS AND METHODS FOR IMPLEMENTING POWER AMPLIFIERS FOR MILLIMETER WAVE APPLICATIONS
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06/12/2007
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11135227
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05/23/2005
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12/07/2006
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VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT
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04/28/2009
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11135739
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05/24/2005
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11/30/2006
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METHODS FOR RECONSTRUCTING DATA FROM SIMULATION MODELS
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12/25/2007
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11136256
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05/24/2005
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11/30/2006
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SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
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11/25/2008
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11136872
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05/25/2005
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11/30/2006
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METHOD FOR AN EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE
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10/28/2008
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11137234
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05/25/2005
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11/30/2006
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METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
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02/26/2008
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11137245
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05/25/2005
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11/30/2006
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CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING
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07/24/2007
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11137957
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05/26/2005
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09/29/2005
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SUPPORTED GREENSHEET STRUCTURE AND METHOD IN MLC PROCESSING
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07/29/2008
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11138797
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05/26/2005
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05/18/2006
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DEVICE COMPRISING DOPED NANO-COMPONENT AND METHOD OF FORMING THE DEVICE
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03/17/2009
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11138835
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05/26/2005
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11/30/2006
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METHOD FOR ISOLATING PROBLEM NETWORKS WITHIN AN INTEGRATED CIRCUIT DESIGN
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08/14/2007
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11140780
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05/31/2005
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11/30/2006
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Title:
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MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS
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07/06/2010
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11141932
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06/01/2005
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12/01/2005
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PATTERNED STRUCTURE FOR A THERMAL INTERFACE
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05/12/2009
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11142248
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06/02/2005
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12/07/2006
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SEMICONDUCTOR DEVICE INCLUDING BACK-GATED TRANSISTORS AND METHOD OF FABRICATING THE DEVICE
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03/04/2008
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11142566
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06/01/2005
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12/07/2006
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SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR REDUCED LEAKAGE AND IMPROVED PERFORMANCE
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11/06/2007
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11142646
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06/01/2005
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12/07/2006
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Title:
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AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES
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NONE
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11143793
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06/02/2005
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10/20/2005
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Title:
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Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
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10/05/2010
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11144857
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06/03/2005
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12/07/2006
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Title:
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IMMERSION LITHOGRAPHY CONTAMINATION GETTERING LAYER
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06/01/2010
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11145866
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06/06/2005
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01/11/2007
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PROBABILISTIC REGRESSION SUITES FOR FUNCTIONAL VERIFICATION
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10/07/2008
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11146441
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06/06/2005
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Pub Dt:
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12/07/2006
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Title:
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APPARATUS AND METHOD FOR FAR END NOISE REDUCTION USING CAPACITIVE CANCELLATION BY OFFSET WIRING
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Patent #:
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Issue Dt:
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10/16/2007
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Application #:
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11146495
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Filing Dt:
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06/06/2005
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Publication #:
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Pub Dt:
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12/07/2006
| | | | |
Title:
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PLANAR ARRAY CONTACT MEMORY CARDS
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Patent #:
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Issue Dt:
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08/21/2007
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Application #:
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11146624
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Filing Dt:
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06/07/2005
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Publication #:
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Pub Dt:
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12/01/2005
| | | | |
Title:
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SELF-ALIGNED ISOLATION DOUBLE-GATE FET
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11148737
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Filing Dt:
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06/09/2005
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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11148923
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Filing Dt:
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06/08/2005
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
Title:
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EXTENSION OF FATIGUE LIFE FOR C4 SOLDER BALL TO CHIP CONNECTION
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Patent #:
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Issue Dt:
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05/02/2006
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Application #:
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11150059
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Filing Dt:
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06/10/2005
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Publication #:
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Pub Dt:
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12/08/2005
| | | | |
Title:
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METHOD FOR FABRICATING A SELF-ALIGNED NANOCOLUMNAR AIRBRIDGE AND STRUCTURE PRODUCED THEREBY
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Patent #:
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Issue Dt:
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12/02/2008
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Application #:
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11150184
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
Title:
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PHASE-CHANGE MEMORY CELL AND METHOD OF FABRICATING THE PHASE-CHANGE MEMORY CELL
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Patent #:
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Issue Dt:
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05/22/2007
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Application #:
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11150188
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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METHOD AND STRUCTURE FOR HIGH PERFORMANCE PHASE CHANGE MEMORY
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Patent #:
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Issue Dt:
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06/02/2009
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Application #:
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11150565
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Filing Dt:
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06/10/2005
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Publication #:
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Pub Dt:
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12/15/2005
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Title:
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ANTIREFLECTIVE FILM-FORMING COMPOSITION, METHOD FOR MANUFACTURING THE SAME, AND ANTIREFLECTIVE FILM AND PATTERN FORMATION METHOD USING THE SAME
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Patent #:
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Issue Dt:
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11/03/2009
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Application #:
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11150894
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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10/20/2005
| | | | |
Title:
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BIPOLAR TRANSISTOR SELF-ALIGNMENT WITH RAISED EXTRINSIC BASE EXTENSION AND METHODS OF FORMING SAME
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Patent #:
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Issue Dt:
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12/19/2006
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Application #:
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11151007
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Filing Dt:
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06/14/2005
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
Title:
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MEMORY DEVICE AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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11151470
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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10/13/2005
| | | | |
Title:
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MAGNETIC TUNNEL JUNCTIONS WITH IMPROVED TUNNELING MAGNETO-RESISTANCE
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Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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11151480
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
Title:
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LITHOGRAPHY TOOL IMAGE QUALITY EVALUATING AND CORRECTING
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11151506
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE TO PRESERVE SHALLOW TRENCH ISOLATION DURING ETCHING
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|
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Patent #:
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Issue Dt:
|
04/08/2008
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Application #:
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11151830
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Filing Dt:
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06/14/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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11151843
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Filing Dt:
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06/14/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS WITH FINS
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|
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11151905
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Filing Dt:
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06/14/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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COOLING STRUCTURE USING RIGID MOVABLE ELEMENTS
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|
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Patent #:
|
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Issue Dt:
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11/27/2007
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Application #:
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11152580
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Filing Dt:
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06/14/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES
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|
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Patent #:
|
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Issue Dt:
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06/17/2008
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Application #:
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11152750
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Filing Dt:
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06/14/2005
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Publication #:
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Pub Dt:
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12/14/2006
| | | | |
Title:
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REPROGRAMMABLE FUSE STRUCTURE AND METHOD
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|
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Patent #:
|
|
Issue Dt:
|
12/11/2007
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Application #:
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11153047
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Filing Dt:
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06/15/2005
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Publication #:
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Pub Dt:
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12/21/2006
| | | | |
Title:
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CAPACITANCE MODELING
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|
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Patent #:
|
|
Issue Dt:
|
02/12/2008
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Application #:
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11153570
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Filing Dt:
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06/13/2005
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Publication #:
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Pub Dt:
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10/20/2005
| | | | |
Title:
|
SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
08/17/2010
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Application #:
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11154794
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Filing Dt:
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06/15/2005
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Publication #:
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Pub Dt:
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11/10/2005
| | | | |
Title:
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UNDERFILLING WITH ACID-CLEAVABLE ACETAL AND KETAL EPOXY OLIGOMERS
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|
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Patent #:
|
|
Issue Dt:
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09/23/2008
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Application #:
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11154905
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Filing Dt:
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06/16/2005
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Publication #:
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Pub Dt:
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01/04/2007
| | | | |
Title:
|
METHOD AND APPARATUS TO SIMULATE AND VERIFY SIGNAL GLITCHING
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|
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Patent #:
|
|
Issue Dt:
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07/28/2009
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Application #:
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11155029
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Filing Dt:
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06/16/2005
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Publication #:
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Pub Dt:
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12/21/2006
| | | | |
Title:
|
PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
10/21/2008
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Application #:
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11155030
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Filing Dt:
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06/16/2005
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Publication #:
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Pub Dt:
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12/21/2006
| | | | |
Title:
|
COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME
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|
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Patent #:
|
|
Issue Dt:
|
06/24/2008
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Application #:
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11157090
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Filing Dt:
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06/20/2005
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Publication #:
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Pub Dt:
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12/21/2006
| | | | |
Title:
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METHOD AND APPARATUS OF CAPACITY LEARNING FOR COMPUTER SYSTEMS AND APPLICATIONS
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|
|
Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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11158372
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Filing Dt:
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06/22/2005
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Publication #:
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Pub Dt:
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12/28/2006
| | | | |
Title:
|
Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof
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|
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Patent #:
|
|
Issue Dt:
|
08/04/2009
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Application #:
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11158726
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Filing Dt:
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06/22/2005
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Publication #:
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Pub Dt:
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10/27/2005
| | | | |
Title:
|
HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF
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|
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Patent #:
|
|
Issue Dt:
|
01/06/2009
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Application #:
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11159477
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Filing Dt:
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06/23/2005
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Publication #:
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Pub Dt:
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12/28/2006
| | | | |
Title:
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PREPARATION OF TOPCOAT COMPOSITIONS AND METHODS OF USE THEREOF
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|
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Patent #:
|
|
Issue Dt:
|
09/05/2006
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Application #:
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11159913
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Filing Dt:
|
06/23/2005
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Title:
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PACKAGING RELIABILITY SUPERCHIPS
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|
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Patent #:
|
|
Issue Dt:
|
09/25/2007
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Application #:
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11159915
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Filing Dt:
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06/23/2005
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Publication #:
|
|
Pub Dt:
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12/28/2006
| | | | |
Title:
|
AUTO CONNECTION ASSIGNMENT SYSTEM AND METHOD
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|
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Patent #:
|
|
Issue Dt:
|
04/15/2008
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Application #:
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11159946
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Filing Dt:
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06/23/2005
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Publication #:
|
|
Pub Dt:
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12/28/2006
| | | | |
Title:
|
TOPCOAT COMPOSITIONS AND METHODS OF USE THEREOF
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|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
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Application #:
|
11160054
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Filing Dt:
|
06/07/2005
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Title:
|
SENSE AMPLIFIER INCLUDING MULTIPLE CONDUCTION STATE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
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Application #:
|
11160055
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Filing Dt:
|
06/07/2005
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Publication #:
|
|
Pub Dt:
|
12/07/2006
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
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Application #:
|
11160111
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Filing Dt:
|
06/09/2005
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Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR STEERING TRANSPORT VEHICLES IN SEMICONDUCTOR PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
11160151
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Filing Dt:
|
06/10/2005
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Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
SECURE ELECTRICALLY PROGRAMMABLE FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2008
|
Application #:
|
11160156
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Filing Dt:
|
06/10/2005
|
Publication #:
|
|
Pub Dt:
|
12/28/2006
| | | | |
Title:
|
IMMERSION LITHOGRAPHY WITH EQUALIZED PRESSURE ON AT LEAST PROJECTION OPTICS COMPONENT AND WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11160184
|
Filing Dt:
|
08/19/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
SELECTIVELY CHANGEABLE LINE WIDTH MEMORY
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11160213
|
Filing Dt:
|
06/14/2005
|
Publication #:
|
|
Pub Dt:
|
12/14/2006
| | | | |
Title:
|
METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11160268
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Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
ENABLING MEMORY REDUNDANCY DURING TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
11160273
|
Filing Dt:
|
06/16/2005
|
Publication #:
|
|
Pub Dt:
|
12/21/2006
| | | | |
Title:
|
SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11160307
|
Filing Dt:
|
06/17/2005
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
Title:
|
NESTED DESIGN APPROACH
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
11160339
|
Filing Dt:
|
06/20/2005
|
Publication #:
|
|
Pub Dt:
|
12/08/2005
| | | | |
Title:
|
IC TILING PATTERN METHOD, IC SO FORMED AND ANALYSIS METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11160360
|
Filing Dt:
|
06/21/2005
|
Publication #:
|
|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
THERMAL DISSIPATION STRUCTURES FOR FINFETS
|
|