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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
06/07/2011
Application #:
11106913
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
10/19/2006
Title:
HIGH-DENSITY LOW-POWER DATA RETENTION POWER GATING WITH DOUBLE-GATE DEVICES
2
Patent #:
Issue Dt:
10/20/2009
Application #:
11107611
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
10/19/2006
Title:
HYBRID CRYSTAL ORIENTATION CMOS STRUCTURE FOR ADAPTIVE WELL BIASING AND FOR POWER AND PERFORMANCE ENHANCEMENT
3
Patent #:
Issue Dt:
09/25/2007
Application #:
11108012
Filing Dt:
04/15/2005
Publication #:
Pub Dt:
10/19/2006
Title:
HYBRID BULK-SOI 6T-SRAM CELL FOR IMPROVED CELL STABILITY AND PERFORMANCE
4
Patent #:
Issue Dt:
06/09/2009
Application #:
11108392
Filing Dt:
04/18/2005
Publication #:
Pub Dt:
10/19/2006
Title:
ELECTROMAGNETIC RESPONSE MODEL WITH IMPROVED HIGH FREQUENCY STABILITY
5
Patent #:
Issue Dt:
01/27/2009
Application #:
11111055
Filing Dt:
04/20/2005
Publication #:
Pub Dt:
10/26/2006
Title:
NANOPOROUS MEDIA WITH LAMELLAR STRUCTURES
6
Patent #:
Issue Dt:
12/04/2007
Application #:
11111454
Filing Dt:
04/21/2005
Publication #:
Pub Dt:
10/26/2006
Title:
ALIGNMENT INSENSITIVE D-CACHE CELL
7
Patent #:
Issue Dt:
10/06/2009
Application #:
11111592
Filing Dt:
04/21/2005
Publication #:
Pub Dt:
10/26/2006
Title:
USING METAL/METAL NITRIDE BILAYERS AS GATE ELECTRODES IN SELF-ALIGNED AGGRESSIVELY SCALED CMOS DEVICES
8
Patent #:
Issue Dt:
11/06/2007
Application #:
11112527
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
METHOD TO DIFFERENTIALLY CONTROL LC VOLTAGE-CONTROLLED OSCILLATORS
9
Patent #:
Issue Dt:
03/25/2008
Application #:
11112820
Filing Dt:
04/22/2005
Publication #:
Pub Dt:
10/26/2006
Title:
STRAINED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ON ROTATED WAFERS AND METHODS THEREOF
10
Patent #:
Issue Dt:
08/21/2007
Application #:
11115606
Filing Dt:
04/27/2005
Publication #:
Pub Dt:
11/02/2006
Title:
METHOD AND APPARATUS TO DISABLE COMPACTION OF TEST RESPONSES IN DETERMINISTIC TEST-SET EMBEDDING-BASED BIST
11
Patent #:
Issue Dt:
12/16/2008
Application #:
11116053
Filing Dt:
04/27/2005
Publication #:
Pub Dt:
11/02/2006
Title:
FIELD EFFECT TRANSISTOR WITH MIXED-CRYSTAL-ORIENTATION CHANNEL AND SOURCE/DRAIN REGIONS
12
Patent #:
Issue Dt:
10/30/2007
Application #:
11116625
Filing Dt:
04/28/2005
Publication #:
Pub Dt:
11/02/2006
Title:
METHODS AND APPARATUS FOR REDUCING MEMORY ERRORS
13
Patent #:
Issue Dt:
06/10/2008
Application #:
11116700
Filing Dt:
04/27/2005
Publication #:
Pub Dt:
11/02/2006
Title:
MEMORY AND LOGIC DEVICES USING ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICES
14
Patent #:
Issue Dt:
04/01/2008
Application #:
11117276
Filing Dt:
04/27/2005
Publication #:
Pub Dt:
11/02/2006
Title:
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
15
Patent #:
Issue Dt:
11/04/2008
Application #:
11118521
Filing Dt:
04/29/2005
Publication #:
Pub Dt:
11/02/2006
Title:
STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS
16
Patent #:
Issue Dt:
12/02/2008
Application #:
11119505
Filing Dt:
04/29/2005
Publication #:
Pub Dt:
11/02/2006
Title:
METHOD FOR PERFORMING HIGH SPEED SERIAL LINK OUTPUT STAGE HAVING SELF ADAPTATION FOR VARIOUS IMPAIRMENTS
17
Patent #:
Issue Dt:
04/10/2007
Application #:
11121454
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
10/20/2005
Title:
SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION
18
Patent #:
Issue Dt:
12/10/2013
Application #:
11122152
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
09/08/2005
Title:
Method and apparatus for dynamic manipulation and dispersion in photonic crystal devices
19
Patent #:
Issue Dt:
07/31/2007
Application #:
11122193
Filing Dt:
05/04/2005
Publication #:
Pub Dt:
12/01/2005
Title:
HYBRID PLANAR AND FINFET CMOS DEVICES
20
Patent #:
NONE
Issue Dt:
Application #:
11123086
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
11/09/2006
Title:
Method and structure for Peltier-controlled phase change memory
21
Patent #:
NONE
Issue Dt:
Application #:
11123117
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
09/15/2005
Title:
Method for electroplating on resistive substrates
22
Patent #:
Issue Dt:
09/23/2008
Application #:
11124247
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
10/06/2005
Title:
HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
23
Patent #:
Issue Dt:
10/21/2008
Application #:
11124324
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
09/08/2005
Title:
METHOD OF CREATING DEEP TRENCH CAPACITOR USING A P+ METAL ELECTRODE
24
Patent #:
NONE
Issue Dt:
Application #:
11124325
Filing Dt:
05/06/2005
Publication #:
Pub Dt:
11/09/2006
Title:
Field effect transistor device including an array of channel elements and methods for forming
25
Patent #:
Issue Dt:
05/27/2008
Application #:
11124978
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
09/15/2005
Title:
SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK
26
Patent #:
Issue Dt:
10/30/2007
Application #:
11125063
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
10/06/2005
Title:
DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
27
Patent #:
Issue Dt:
03/17/2009
Application #:
11125499
Filing Dt:
05/10/2005
Publication #:
Pub Dt:
11/16/2006
Title:
APPARATUS AND METHODS FOR CONSTRUCTING BALANCED CHIP PACKAGES TO REDUCE THERMALLY INDUCED MECHANICAL STRAIN
28
Patent #:
Issue Dt:
09/05/2006
Application #:
11125549
Filing Dt:
05/10/2005
Publication #:
Pub Dt:
09/15/2005
Title:
METHOD TO GENERATE POROUS ORGANIC DIELECTRIC
29
Patent #:
Issue Dt:
11/06/2007
Application #:
11125696
Filing Dt:
05/10/2005
Publication #:
Pub Dt:
11/16/2006
Title:
METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS
30
Patent #:
Issue Dt:
04/08/2008
Application #:
11125971
Filing Dt:
05/09/2005
Publication #:
Pub Dt:
11/09/2006
Title:
PHOTORESISTS FOR VISIBLE LIGHT IMAGING
31
Patent #:
Issue Dt:
01/22/2008
Application #:
11126675
Filing Dt:
05/11/2005
Publication #:
Pub Dt:
09/29/2005
Title:
METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
32
Patent #:
Issue Dt:
12/18/2007
Application #:
11127616
Filing Dt:
05/12/2005
Publication #:
Pub Dt:
11/16/2006
Title:
METHOD OF INSPECTING INTEGRATED CIRCUITS DURING FABRICATION
33
Patent #:
Issue Dt:
06/17/2008
Application #:
11128069
Filing Dt:
05/12/2005
Publication #:
Pub Dt:
11/16/2006
Title:
INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS
34
Patent #:
Issue Dt:
12/11/2007
Application #:
11129325
Filing Dt:
05/16/2005
Publication #:
Pub Dt:
09/15/2005
Title:
STRUCTURE AND METHOD FOR FORMING A DIELECTRIC CHAMBER AND ELECTRONIC DEVICE INCLUDING THE DIELECTRIC CHAMBER
35
Patent #:
Issue Dt:
04/08/2008
Application #:
11129784
Filing Dt:
05/16/2005
Publication #:
Pub Dt:
01/12/2006
Title:
GENIE: A METHOD FOR CLASSIFICATION AND GRAPHICAL DISPLAY OF NEGATIVE SLACK TIMING TEST FAILURES
36
Patent #:
Issue Dt:
12/04/2007
Application #:
11129785
Filing Dt:
05/16/2005
Publication #:
Pub Dt:
01/19/2006
Title:
NEGATIVE SLACK RECOVERABILITY FACTOR - A NET WEIGHT TO ENHANCE TIMING CLOSURE BEHAVIOR
37
Patent #:
Issue Dt:
05/13/2008
Application #:
11130078
Filing Dt:
05/16/2005
Publication #:
Pub Dt:
11/16/2006
Title:
PROCESS FOR PREPARING ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTILAYER HARDMASK SCHEME
38
Patent #:
Issue Dt:
11/28/2006
Application #:
11130313
Filing Dt:
05/16/2005
Publication #:
Pub Dt:
11/16/2006
Title:
METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR HAVING UNIPOLAR CHARACTERISTICS
39
Patent #:
Issue Dt:
04/03/2007
Application #:
11131534
Filing Dt:
05/18/2005
Publication #:
Pub Dt:
11/23/2006
Title:
CIRCUITS AND METHODS FOR IMPLEMENTING POWER AMPLIFIERS FOR MILLIMETER WAVE APPLICATIONS
40
Patent #:
Issue Dt:
06/12/2007
Application #:
11135227
Filing Dt:
05/23/2005
Publication #:
Pub Dt:
12/07/2006
Title:
VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT
41
Patent #:
Issue Dt:
04/28/2009
Application #:
11135739
Filing Dt:
05/24/2005
Publication #:
Pub Dt:
11/30/2006
Title:
METHODS FOR RECONSTRUCTING DATA FROM SIMULATION MODELS
42
Patent #:
Issue Dt:
12/25/2007
Application #:
11136256
Filing Dt:
05/24/2005
Publication #:
Pub Dt:
11/30/2006
Title:
SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
43
Patent #:
Issue Dt:
11/25/2008
Application #:
11136872
Filing Dt:
05/25/2005
Publication #:
Pub Dt:
11/30/2006
Title:
METHOD FOR AN EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE
44
Patent #:
Issue Dt:
10/28/2008
Application #:
11137234
Filing Dt:
05/25/2005
Publication #:
Pub Dt:
11/30/2006
Title:
METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
45
Patent #:
Issue Dt:
02/26/2008
Application #:
11137245
Filing Dt:
05/25/2005
Publication #:
Pub Dt:
11/30/2006
Title:
CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING
46
Patent #:
Issue Dt:
07/24/2007
Application #:
11137957
Filing Dt:
05/26/2005
Publication #:
Pub Dt:
09/29/2005
Title:
SUPPORTED GREENSHEET STRUCTURE AND METHOD IN MLC PROCESSING
47
Patent #:
Issue Dt:
07/29/2008
Application #:
11138797
Filing Dt:
05/26/2005
Publication #:
Pub Dt:
05/18/2006
Title:
DEVICE COMPRISING DOPED NANO-COMPONENT AND METHOD OF FORMING THE DEVICE
48
Patent #:
Issue Dt:
03/17/2009
Application #:
11138835
Filing Dt:
05/26/2005
Publication #:
Pub Dt:
11/30/2006
Title:
METHOD FOR ISOLATING PROBLEM NETWORKS WITHIN AN INTEGRATED CIRCUIT DESIGN
49
Patent #:
Issue Dt:
08/14/2007
Application #:
11140780
Filing Dt:
05/31/2005
Publication #:
Pub Dt:
11/30/2006
Title:
MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS
50
Patent #:
Issue Dt:
07/06/2010
Application #:
11141932
Filing Dt:
06/01/2005
Publication #:
Pub Dt:
12/01/2005
Title:
PATTERNED STRUCTURE FOR A THERMAL INTERFACE
51
Patent #:
Issue Dt:
05/12/2009
Application #:
11142248
Filing Dt:
06/02/2005
Publication #:
Pub Dt:
12/07/2006
Title:
SEMICONDUCTOR DEVICE INCLUDING BACK-GATED TRANSISTORS AND METHOD OF FABRICATING THE DEVICE
52
Patent #:
Issue Dt:
03/04/2008
Application #:
11142566
Filing Dt:
06/01/2005
Publication #:
Pub Dt:
12/07/2006
Title:
SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR REDUCED LEAKAGE AND IMPROVED PERFORMANCE
53
Patent #:
Issue Dt:
11/06/2007
Application #:
11142646
Filing Dt:
06/01/2005
Publication #:
Pub Dt:
12/07/2006
Title:
AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES
54
Patent #:
NONE
Issue Dt:
Application #:
11143793
Filing Dt:
06/02/2005
Publication #:
Pub Dt:
10/20/2005
Title:
Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same
55
Patent #:
Issue Dt:
10/05/2010
Application #:
11144857
Filing Dt:
06/03/2005
Publication #:
Pub Dt:
12/07/2006
Title:
IMMERSION LITHOGRAPHY CONTAMINATION GETTERING LAYER
56
Patent #:
Issue Dt:
06/01/2010
Application #:
11145866
Filing Dt:
06/06/2005
Publication #:
Pub Dt:
01/11/2007
Title:
PROBABILISTIC REGRESSION SUITES FOR FUNCTIONAL VERIFICATION
57
Patent #:
Issue Dt:
10/07/2008
Application #:
11146441
Filing Dt:
06/06/2005
Publication #:
Pub Dt:
12/07/2006
Title:
APPARATUS AND METHOD FOR FAR END NOISE REDUCTION USING CAPACITIVE CANCELLATION BY OFFSET WIRING
58
Patent #:
Issue Dt:
10/16/2007
Application #:
11146495
Filing Dt:
06/06/2005
Publication #:
Pub Dt:
12/07/2006
Title:
PLANAR ARRAY CONTACT MEMORY CARDS
59
Patent #:
Issue Dt:
08/21/2007
Application #:
11146624
Filing Dt:
06/07/2005
Publication #:
Pub Dt:
12/01/2005
Title:
SELF-ALIGNED ISOLATION DOUBLE-GATE FET
60
Patent #:
Issue Dt:
09/18/2007
Application #:
11148737
Filing Dt:
06/09/2005
Publication #:
Pub Dt:
12/15/2005
Title:
SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY
61
Patent #:
Issue Dt:
10/10/2006
Application #:
11148923
Filing Dt:
06/08/2005
Publication #:
Pub Dt:
10/13/2005
Title:
EXTENSION OF FATIGUE LIFE FOR C4 SOLDER BALL TO CHIP CONNECTION
62
Patent #:
Issue Dt:
05/02/2006
Application #:
11150059
Filing Dt:
06/10/2005
Publication #:
Pub Dt:
12/08/2005
Title:
METHOD FOR FABRICATING A SELF-ALIGNED NANOCOLUMNAR AIRBRIDGE AND STRUCTURE PRODUCED THEREBY
63
Patent #:
Issue Dt:
12/02/2008
Application #:
11150184
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
10/13/2005
Title:
PHASE-CHANGE MEMORY CELL AND METHOD OF FABRICATING THE PHASE-CHANGE MEMORY CELL
64
Patent #:
Issue Dt:
05/22/2007
Application #:
11150188
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
12/14/2006
Title:
METHOD AND STRUCTURE FOR HIGH PERFORMANCE PHASE CHANGE MEMORY
65
Patent #:
Issue Dt:
06/02/2009
Application #:
11150565
Filing Dt:
06/10/2005
Publication #:
Pub Dt:
12/15/2005
Title:
ANTIREFLECTIVE FILM-FORMING COMPOSITION, METHOD FOR MANUFACTURING THE SAME, AND ANTIREFLECTIVE FILM AND PATTERN FORMATION METHOD USING THE SAME
66
Patent #:
Issue Dt:
11/03/2009
Application #:
11150894
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
10/20/2005
Title:
BIPOLAR TRANSISTOR SELF-ALIGNMENT WITH RAISED EXTRINSIC BASE EXTENSION AND METHODS OF FORMING SAME
67
Patent #:
Issue Dt:
12/19/2006
Application #:
11151007
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
10/27/2005
Title:
MEMORY DEVICE AND METHOD OF MAKING THE SAME
68
Patent #:
Issue Dt:
10/02/2007
Application #:
11151470
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
10/13/2005
Title:
MAGNETIC TUNNEL JUNCTIONS WITH IMPROVED TUNNELING MAGNETO-RESISTANCE
69
Patent #:
Issue Dt:
06/24/2008
Application #:
11151480
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
10/27/2005
Title:
LITHOGRAPHY TOOL IMAGE QUALITY EVALUATING AND CORRECTING
70
Patent #:
NONE
Issue Dt:
Application #:
11151506
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
12/15/2005
Title:
SEMICONDUCTOR STRUCTURE TO PRESERVE SHALLOW TRENCH ISOLATION DURING ETCHING
71
Patent #:
Issue Dt:
04/08/2008
Application #:
11151830
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
12/14/2006
Title:
COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS
72
Patent #:
Issue Dt:
08/05/2008
Application #:
11151843
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
12/14/2006
Title:
COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS WITH FINS
73
Patent #:
Issue Dt:
04/22/2008
Application #:
11151905
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
12/14/2006
Title:
COOLING STRUCTURE USING RIGID MOVABLE ELEMENTS
74
Patent #:
Issue Dt:
11/27/2007
Application #:
11152580
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
12/14/2006
Title:
EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES
75
Patent #:
Issue Dt:
06/17/2008
Application #:
11152750
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
12/14/2006
Title:
REPROGRAMMABLE FUSE STRUCTURE AND METHOD
76
Patent #:
Issue Dt:
12/11/2007
Application #:
11153047
Filing Dt:
06/15/2005
Publication #:
Pub Dt:
12/21/2006
Title:
CAPACITANCE MODELING
77
Patent #:
Issue Dt:
02/12/2008
Application #:
11153570
Filing Dt:
06/13/2005
Publication #:
Pub Dt:
10/20/2005
Title:
SYSTEM AND METHOD FOR REMOTE OPTICAL DIGITAL NETWORKING OF COMPUTING DEVICES
78
Patent #:
Issue Dt:
08/17/2010
Application #:
11154794
Filing Dt:
06/15/2005
Publication #:
Pub Dt:
11/10/2005
Title:
UNDERFILLING WITH ACID-CLEAVABLE ACETAL AND KETAL EPOXY OLIGOMERS
79
Patent #:
Issue Dt:
09/23/2008
Application #:
11154905
Filing Dt:
06/16/2005
Publication #:
Pub Dt:
01/04/2007
Title:
METHOD AND APPARATUS TO SIMULATE AND VERIFY SIGNAL GLITCHING
80
Patent #:
Issue Dt:
07/28/2009
Application #:
11155029
Filing Dt:
06/16/2005
Publication #:
Pub Dt:
12/21/2006
Title:
PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME
81
Patent #:
Issue Dt:
10/21/2008
Application #:
11155030
Filing Dt:
06/16/2005
Publication #:
Pub Dt:
12/21/2006
Title:
COPLANAR SILICON-ON-INSULATOR (SOI) REGIONS OF DIFFERENT CRYSTAL ORIENTATIONS AND METHODS OF MAKING THE SAME
82
Patent #:
Issue Dt:
06/24/2008
Application #:
11157090
Filing Dt:
06/20/2005
Publication #:
Pub Dt:
12/21/2006
Title:
METHOD AND APPARATUS OF CAPACITY LEARNING FOR COMPUTER SYSTEMS AND APPLICATIONS
83
Patent #:
NONE
Issue Dt:
Application #:
11158372
Filing Dt:
06/22/2005
Publication #:
Pub Dt:
12/28/2006
Title:
Method to control flatband/threshold voltage in high-k metal gated stacks and structures thereof
84
Patent #:
Issue Dt:
08/04/2009
Application #:
11158726
Filing Dt:
06/22/2005
Publication #:
Pub Dt:
10/27/2005
Title:
HIGH SPEED LATERAL HETEROJUNCTION MISFETS REALIZED BY 2-DIMENSIONAL BANDGAP ENGINEERING AND METHODS THEREOF
85
Patent #:
Issue Dt:
01/06/2009
Application #:
11159477
Filing Dt:
06/23/2005
Publication #:
Pub Dt:
12/28/2006
Title:
PREPARATION OF TOPCOAT COMPOSITIONS AND METHODS OF USE THEREOF
86
Patent #:
Issue Dt:
09/05/2006
Application #:
11159913
Filing Dt:
06/23/2005
Title:
PACKAGING RELIABILITY SUPERCHIPS
87
Patent #:
Issue Dt:
09/25/2007
Application #:
11159915
Filing Dt:
06/23/2005
Publication #:
Pub Dt:
12/28/2006
Title:
AUTO CONNECTION ASSIGNMENT SYSTEM AND METHOD
88
Patent #:
Issue Dt:
04/15/2008
Application #:
11159946
Filing Dt:
06/23/2005
Publication #:
Pub Dt:
12/28/2006
Title:
TOPCOAT COMPOSITIONS AND METHODS OF USE THEREOF
89
Patent #:
Issue Dt:
10/17/2006
Application #:
11160054
Filing Dt:
06/07/2005
Title:
SENSE AMPLIFIER INCLUDING MULTIPLE CONDUCTION STATE FIELD EFFECT TRANSISTOR
90
Patent #:
Issue Dt:
03/26/2013
Application #:
11160055
Filing Dt:
06/07/2005
Publication #:
Pub Dt:
12/07/2006
Title:
FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES
91
Patent #:
Issue Dt:
03/16/2010
Application #:
11160111
Filing Dt:
06/09/2005
Publication #:
Pub Dt:
12/14/2006
Title:
APPARATUS AND METHOD FOR STEERING TRANSPORT VEHICLES IN SEMICONDUCTOR PROCESSING
92
Patent #:
Issue Dt:
06/24/2008
Application #:
11160151
Filing Dt:
06/10/2005
Publication #:
Pub Dt:
12/14/2006
Title:
SECURE ELECTRICALLY PROGRAMMABLE FUSE
93
Patent #:
Issue Dt:
06/10/2008
Application #:
11160156
Filing Dt:
06/10/2005
Publication #:
Pub Dt:
12/28/2006
Title:
IMMERSION LITHOGRAPHY WITH EQUALIZED PRESSURE ON AT LEAST PROJECTION OPTICS COMPONENT AND WAFER
94
Patent #:
Issue Dt:
07/29/2008
Application #:
11160184
Filing Dt:
08/19/2005
Publication #:
Pub Dt:
12/08/2005
Title:
SELECTIVELY CHANGEABLE LINE WIDTH MEMORY
95
Patent #:
NONE
Issue Dt:
Application #:
11160213
Filing Dt:
06/14/2005
Publication #:
Pub Dt:
12/14/2006
Title:
METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR
96
Patent #:
Issue Dt:
12/04/2007
Application #:
11160268
Filing Dt:
06/16/2005
Publication #:
Pub Dt:
12/08/2005
Title:
ENABLING MEMORY REDUNDANCY DURING TESTING
97
Patent #:
Issue Dt:
12/05/2006
Application #:
11160273
Filing Dt:
06/16/2005
Publication #:
Pub Dt:
12/21/2006
Title:
SINGLE CYCLE REFRESH OF MULTI-PORT DYNAMIC RANDOM ACCESS MEMORY (DRAM)
98
Patent #:
Issue Dt:
01/29/2008
Application #:
11160307
Filing Dt:
06/17/2005
Publication #:
Pub Dt:
12/15/2005
Title:
NESTED DESIGN APPROACH
99
Patent #:
Issue Dt:
02/23/2010
Application #:
11160339
Filing Dt:
06/20/2005
Publication #:
Pub Dt:
12/08/2005
Title:
IC TILING PATTERN METHOD, IC SO FORMED AND ANALYSIS METHOD
100
Patent #:
Issue Dt:
09/11/2007
Application #:
11160360
Filing Dt:
06/21/2005
Publication #:
Pub Dt:
01/11/2007
Title:
THERMAL DISSIPATION STRUCTURES FOR FINFETS
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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