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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
12/11/2007
Application #:
11380799
Filing Dt:
04/28/2006
Publication #:
Pub Dt:
11/01/2007
Title:
STRUCTURE AND METHOD FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES
2
Patent #:
Issue Dt:
10/18/2011
Application #:
11381373
Filing Dt:
05/03/2006
Publication #:
Pub Dt:
11/08/2007
Title:
OPTIMIZING THERMAL PERFORMANCE USING THERMAL FLOW ANALYSIS
3
Patent #:
Issue Dt:
06/23/2009
Application #:
11381380
Filing Dt:
05/03/2006
Publication #:
Pub Dt:
11/08/2007
Title:
DYNAMICALLY ADAPTING SOFTWARE FOR REDUCING A THERMAL STATE OF A PROCESSOR CORE BASED ON ITS THERMAL INDEX
4
Patent #:
Issue Dt:
09/29/2009
Application #:
11381391
Filing Dt:
05/03/2006
Publication #:
Pub Dt:
11/08/2007
Title:
SELECTION OF PROCESSOR CORES FOR OPTIMAL THERMAL PERFORMANCE
5
Patent #:
Issue Dt:
05/04/2010
Application #:
11381437
Filing Dt:
05/03/2006
Publication #:
Pub Dt:
11/08/2007
Title:
SIGNALS FOR SIMULATION RESULT VIEWING
6
Patent #:
NONE
Issue Dt:
Application #:
11381861
Filing Dt:
05/05/2006
Publication #:
Pub Dt:
11/08/2007
Title:
STRUCTURE HAVING ISOLATION STRUCTURE INCLUDING DEUTERIUM WITHIN A SUBSTRATE AND RELATED METHOD
7
Patent #:
Issue Dt:
06/01/2010
Application #:
11382544
Filing Dt:
05/10/2006
Publication #:
Pub Dt:
11/15/2007
Title:
METHOD AND STRUCTURE FOR CREATION OF A METAL INSULATOR METAL CAPACITOR
8
Patent #:
Issue Dt:
07/10/2007
Application #:
11382720
Filing Dt:
07/06/2006
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE
9
Patent #:
Issue Dt:
01/13/2009
Application #:
11382963
Filing Dt:
05/12/2006
Publication #:
Pub Dt:
11/15/2007
Title:
IMPROVED EQUIVALENT GATE COUNT YIELD ESTIMATION FOR INTEGRATED CIRCUIT DEVICES
10
Patent #:
Issue Dt:
10/28/2008
Application #:
11383353
Filing Dt:
05/15/2006
Publication #:
Pub Dt:
08/31/2006
Title:
METHOD AND SYSTEM FOR EVALUATING TIMING IN AN INTEGATED CIRCUIT
11
Patent #:
Issue Dt:
01/27/2009
Application #:
11383544
Filing Dt:
05/16/2006
Publication #:
Pub Dt:
11/22/2007
Title:
BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS
12
Patent #:
NONE
Issue Dt:
Application #:
11383548
Filing Dt:
05/16/2006
Publication #:
Pub Dt:
11/22/2007
Title:
NEW SUB 40 NM RESOLUTION SI CONTAINING RESIST SYSTEM
13
Patent #:
Issue Dt:
10/23/2007
Application #:
11383563
Filing Dt:
05/16/2006
Title:
DUAL WIRED INTEGRATED CIRCUIT CHIPS
14
Patent #:
NONE
Issue Dt:
Application #:
11383565
Filing Dt:
05/16/2006
Publication #:
Pub Dt:
11/22/2007
Title:
STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS
15
Patent #:
Issue Dt:
03/02/2010
Application #:
11383586
Filing Dt:
05/16/2006
Publication #:
Pub Dt:
11/22/2007
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
16
Patent #:
Issue Dt:
12/09/2008
Application #:
11383595
Filing Dt:
05/16/2006
Publication #:
Pub Dt:
11/22/2007
Title:
DUAL-SIDED CHIP ATTACHED MODULES
17
Patent #:
Issue Dt:
07/08/2008
Application #:
11383770
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
11/22/2007
Title:
TRACE EQUIVALENCE IDENTIFICATION THROUGH STRUCTURAL ISOMORPHISM DETECTION WITH ON THE FLY LOGIC WRITING
18
Patent #:
Issue Dt:
02/03/2009
Application #:
11383821
Filing Dt:
05/17/2006
Publication #:
Pub Dt:
11/22/2007
Title:
SIGNAL DETECTOR WITH CALIBRATION CIRCUIT ARRANGEMENT
19
Patent #:
Issue Dt:
10/28/2008
Application #:
11383965
Filing Dt:
05/18/2006
Publication #:
Pub Dt:
11/22/2007
Title:
METHOD OF FORMING SUBSTANTIALLY L-SHAPED SILICIDE CONTACT FOR A SEMICONDUCTOR DEVICE
20
Patent #:
NONE
Issue Dt:
Application #:
11384718
Filing Dt:
03/15/2006
Publication #:
Pub Dt:
09/20/2007
Title:
Structure and method for controlling the behavior of dislocations in strained semiconductor layers
21
Patent #:
Issue Dt:
10/16/2007
Application #:
11385121
Filing Dt:
03/21/2006
Publication #:
Pub Dt:
09/27/2007
Title:
METHOD FOR PRECISION ASSEMBLY OF INTEGRATED CIRCUIT CHIP PACKAGES
22
Patent #:
Issue Dt:
11/27/2007
Application #:
11385928
Filing Dt:
03/21/2006
Publication #:
Pub Dt:
01/11/2007
Title:
METHOD AND SYSTEM FOR PERFORMING FUNCTIONAL VERIFICATION OF LOGIC CIRCUITS
23
Patent #:
Issue Dt:
12/07/2010
Application #:
11387873
Filing Dt:
03/24/2006
Publication #:
Pub Dt:
04/29/2010
Title:
HEATER AND MEMORY CELL, MEMORY DEVICE AND RECORDING HEAD INCLUDING THE HEATER
24
Patent #:
Issue Dt:
08/11/2009
Application #:
11388132
Filing Dt:
03/23/2006
Publication #:
Pub Dt:
09/27/2007
Title:
MONOLITHIC HIGH ASPECT RATIO NANO-SIZE SCANNING PROBE MICROSCOPE (SPM) TIP FORMED BY NANOWIRE GROWTH
25
Patent #:
Issue Dt:
02/07/2012
Application #:
11389344
Filing Dt:
03/24/2006
Publication #:
Pub Dt:
09/27/2007
Title:
RESOURCE ADAPTIVE SPECTRUM ESTIMATION OF STREAMING DATA
26
Patent #:
Issue Dt:
10/14/2008
Application #:
11390390
Filing Dt:
03/27/2006
Publication #:
Pub Dt:
09/27/2007
Title:
DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
27
Patent #:
Issue Dt:
06/10/2008
Application #:
11390510
Filing Dt:
03/27/2006
Publication #:
Pub Dt:
04/19/2007
Title:
FLEXIBLE CAPACITIVE COUPLER ASSEMBLY AND METHOD OF MANUFACTURE
28
Patent #:
Issue Dt:
11/30/2010
Application #:
11390527
Filing Dt:
03/27/2006
Publication #:
Pub Dt:
09/27/2007
Title:
COMPUTER-IMPLEMENTED METHOD, SYSTEM AND PROGRAM PRODUCT FOR APPROXIMATING RESOURCE CONSUMPTION OF COMPUTER SYSTEM
29
Patent #:
Issue Dt:
03/04/2008
Application #:
11390533
Filing Dt:
03/28/2006
Publication #:
Pub Dt:
10/04/2007
Title:
METHOD AND APPARATUS FOR RECOGNITION AND TAGGING OF MULTIPLE LAYERED ENTROPY CODING SYSTEM
30
Patent #:
Issue Dt:
12/02/2008
Application #:
11391050
Filing Dt:
03/28/2006
Publication #:
Pub Dt:
07/27/2006
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING AIR GAPS AND THE STRUCTURE SO FORMED
31
Patent #:
NONE
Issue Dt:
Application #:
11391880
Filing Dt:
03/29/2006
Publication #:
Pub Dt:
10/04/2007
Title:
Multiple mode approach to building static timing models for digital transistor circuits
32
Patent #:
Issue Dt:
04/22/2008
Application #:
11392071
Filing Dt:
03/29/2006
Publication #:
Pub Dt:
10/11/2007
Title:
ASYMMETRICAL MEMORY CELLS AND MEMORIES USING THE CELLS
33
Patent #:
NONE
Issue Dt:
Application #:
11392405
Filing Dt:
03/29/2006
Publication #:
Pub Dt:
10/04/2007
Title:
A method of creating a load balanced spatial partitioning of a structured, diffusing system of particles
34
Patent #:
Issue Dt:
01/12/2010
Application #:
11393259
Filing Dt:
03/30/2006
Publication #:
Pub Dt:
10/11/2007
Title:
THREE-TERMINAL CASCADE SWITCH FOR CONTROLLING STATIC POWER CONSUMPTION IN INTEGRATED CIRCUITS
35
Patent #:
Issue Dt:
06/09/2009
Application #:
11393270
Filing Dt:
03/30/2006
Publication #:
Pub Dt:
10/11/2007
Title:
PROGRAMMABLE VIA STRUCTURE FOR THREE DIMENSIONAL INTEGRATION TECHNOLOGY
36
Patent #:
Issue Dt:
01/20/2009
Application #:
11395098
Filing Dt:
03/31/2006
Publication #:
Pub Dt:
10/04/2007
Title:
APPARATUS AND METHODS FOR CONSTRUCTING AND PACKAGING WAVEGUIDE TO PLANAR TRANSMISSION LINE TRANSITIONS FOR MILLIMETER WAVE APPLICATIONS
37
Patent #:
Issue Dt:
01/06/2009
Application #:
11395355
Filing Dt:
03/31/2006
Publication #:
Pub Dt:
10/04/2007
Title:
SPACE TRANSFORMING LAND GRID ARRAY INTERPOSERS
38
Patent #:
Issue Dt:
05/15/2012
Application #:
11395857
Filing Dt:
03/31/2006
Publication #:
Pub Dt:
10/04/2007
Title:
HEAT TRANSFER CONTROL STRUCTURES USING THERMAL PHONON SPECTRAL OVERLAP
39
Patent #:
Issue Dt:
11/11/2008
Application #:
11397034
Filing Dt:
04/03/2006
Publication #:
Pub Dt:
10/04/2007
Title:
METHOD AND SYSTEM TO DEVELOP A PROCESS IMPROVEMENT METHODOLOGY
40
Patent #:
NONE
Issue Dt:
Application #:
11397586
Filing Dt:
04/04/2006
Publication #:
Pub Dt:
10/04/2007
Title:
CELL PLACEMENT IN CIRCUIT DESIGN
41
Patent #:
Issue Dt:
12/23/2008
Application #:
11398135
Filing Dt:
04/05/2006
Publication #:
Pub Dt:
10/11/2007
Title:
IMPRINT PROCESS USING POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS
42
Patent #:
NONE
Issue Dt:
Application #:
11400390
Filing Dt:
04/10/2006
Publication #:
Pub Dt:
10/11/2007
Title:
Embedded nanoparticle films and method for their formation in selective areas on a surface
43
Patent #:
NONE
Issue Dt:
Application #:
11400596
Filing Dt:
04/07/2006
Publication #:
Pub Dt:
10/11/2007
Title:
SIMULTANEOUS CONDITIONING OF A PLURALITY OF MEMORY CELLS THROUGH SERIES RESISTORS
44
Patent #:
NONE
Issue Dt:
Application #:
11401672
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
10/11/2007
Title:
CMOS process with Si gates for nFETs and SiGe gates for pFETs
45
Patent #:
Issue Dt:
02/17/2009
Application #:
11401786
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
08/17/2006
Title:
BACK GATE FINFET SRAM
46
Patent #:
Issue Dt:
01/06/2009
Application #:
11402177
Filing Dt:
04/11/2006
Publication #:
Pub Dt:
10/11/2007
Title:
CONTROL OF POLY-SI DEPLETION IN CMOS VIA GAS PHASE DOPING
47
Patent #:
Issue Dt:
03/23/2010
Application #:
11402400
Filing Dt:
04/12/2006
Publication #:
Pub Dt:
10/18/2007
Title:
DYNAMIC CONTROL OF BACK GATE BIAS IN A FINFET SRAM CELL
48
Patent #:
Issue Dt:
03/01/2011
Application #:
11402401
Filing Dt:
04/12/2006
Publication #:
Pub Dt:
10/18/2007
Title:
STATIC RANDOM ACCESS MEMORY (SRAM) CELLS
49
Patent #:
Issue Dt:
11/25/2008
Application #:
11403332
Filing Dt:
04/13/2006
Publication #:
Pub Dt:
08/24/2006
Title:
BUILDING METAL PILLARS IN A CHIP FOR STRUCTURE SUPPORT
50
Patent #:
NONE
Issue Dt:
Application #:
11403665
Filing Dt:
04/13/2006
Publication #:
Pub Dt:
06/21/2007
Title:
PHASE-LOCKED LOOP
51
Patent #:
Issue Dt:
12/18/2007
Application #:
11405283
Filing Dt:
04/17/2006
Publication #:
Pub Dt:
11/30/2006
Title:
METHOD OF FORMING CLOSED AIR GAP INTERCONNECTS AND STRUCTURES FORMED THEREBY
52
Patent #:
Issue Dt:
07/01/2008
Application #:
11405287
Filing Dt:
04/17/2006
Publication #:
Pub Dt:
11/16/2006
Title:
METHOD OF FORMING CLOSED AIR GAP INTERCONNECTS AND STRUCTURES FORMED THEREBY
53
Patent #:
Issue Dt:
07/21/2009
Application #:
11405879
Filing Dt:
04/18/2006
Publication #:
Pub Dt:
10/18/2007
Title:
WET DEVELOPABLE BOTTOM ANTIREFLECTIVE COATING COMPOSITION AND METHOD FOR USE THEREOF
54
Patent #:
Issue Dt:
10/05/2010
Application #:
11405997
Filing Dt:
04/18/2006
Publication #:
Pub Dt:
10/18/2007
Title:
ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY
55
Patent #:
Issue Dt:
06/16/2009
Application #:
11406122
Filing Dt:
04/18/2006
Publication #:
Pub Dt:
12/07/2006
Title:
LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS
56
Patent #:
Issue Dt:
07/08/2008
Application #:
11406123
Filing Dt:
04/18/2006
Publication #:
Pub Dt:
10/18/2007
Title:
TRENCH-EDGE-DEFECT-FREE RECRYSTALLIZATION BY EDGE-ANGLE-OPTIMIZED SOLID PHASE EPITAXY: METHOD AND APPLICATIONS TO HYBRID ORIENTATION SUBSTRATES
57
Patent #:
Issue Dt:
02/15/2011
Application #:
11406595
Filing Dt:
04/19/2006
Publication #:
Pub Dt:
08/24/2006
Title:
STRUCTURES WITH IMPROVED INTERFACIAL STRENGTH OF SICOH DIELECTRICS AND METHOD FOR PREPARING THE SAME
58
Patent #:
Issue Dt:
06/17/2008
Application #:
11407176
Filing Dt:
04/19/2006
Publication #:
Pub Dt:
09/21/2006
Title:
SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
59
Patent #:
Issue Dt:
08/12/2008
Application #:
11407313
Filing Dt:
04/19/2006
Publication #:
Pub Dt:
08/24/2006
Title:
CMOS SILICIDE METAL GATE INTEGRATION
60
Patent #:
Issue Dt:
03/25/2008
Application #:
11407473
Filing Dt:
04/20/2006
Publication #:
Pub Dt:
10/25/2007
Title:
METAL GATED ULTRA SHORT MOSFET DEVICES
61
Patent #:
Issue Dt:
03/06/2007
Application #:
11407543
Filing Dt:
04/19/2006
Publication #:
Pub Dt:
12/28/2006
Title:
METROLOGY TOOL ERROR LOG ANALYSIS METHODOLOGY AND SYSTEM
62
Patent #:
Issue Dt:
08/12/2008
Application #:
11408522
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE FIELD EFFECT TRANSISTORS
63
Patent #:
Issue Dt:
05/15/2012
Application #:
11408557
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
07/21/2011
Title:
RIBONUCLEIC ACID INTERFERENCE MOLECULES AND BINDING SITES DERIVED BY ANALYZING INTERGENIC AND INTRONIC REGIONS OF GENOMES
64
Patent #:
Issue Dt:
02/11/2014
Application #:
11408752
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
DYNAMIC MEMORY CELL STRUCTURES
65
Patent #:
Issue Dt:
08/26/2008
Application #:
11409232
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
ROTATIONAL FILL TECHNIQUES FOR INJECTION MOLDING OF SOLDER
66
Patent #:
Issue Dt:
08/12/2008
Application #:
11409233
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
FILL HEAD FOR INJECTION MOLDING OF SOLDER
67
Patent #:
Issue Dt:
04/13/2010
Application #:
11409242
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
UNIVERSAL MOLD FOR INJECTION MOLDING OF SOLDER
68
Patent #:
Issue Dt:
08/12/2008
Application #:
11409244
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
CONDUCTIVE BONDING MATERIAL FILL TECHNIQUES
69
Patent #:
Issue Dt:
01/29/2008
Application #:
11409440
Filing Dt:
04/21/2006
Publication #:
Pub Dt:
10/25/2007
Title:
NON-VOLATILE MEMORY ARCHITECTURE EMPLOYING BIPOLAR PROGRAMMABLE RESISTANCE STORAGE ELEMENTS
70
Patent #:
Issue Dt:
07/08/2008
Application #:
11409858
Filing Dt:
04/24/2006
Publication #:
Pub Dt:
10/25/2007
Title:
STATIC RANDOM ACCESS MEMORY CELL WITH IMPROVED STABILITY
71
Patent #:
Issue Dt:
07/24/2007
Application #:
11410829
Filing Dt:
04/24/2006
Publication #:
Pub Dt:
08/24/2006
Title:
WIRELESS COMMUNICATION SYSTEM WITHIN A SYSTEM ON A CHIP
72
Patent #:
Issue Dt:
06/10/2008
Application #:
11411280
Filing Dt:
04/26/2006
Publication #:
Pub Dt:
11/01/2007
Title:
HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME
73
Patent #:
Issue Dt:
01/20/2009
Application #:
11413010
Filing Dt:
04/28/2006
Publication #:
Pub Dt:
11/01/2007
Title:
METHOD TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE
74
Patent #:
NONE
Issue Dt:
Application #:
11413532
Filing Dt:
04/29/2006
Publication #:
Pub Dt:
09/14/2006
Title:
Thin germanium oxynitride gate dielectric for germanium-based devices
75
Patent #:
Issue Dt:
04/29/2008
Application #:
11414020
Filing Dt:
04/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
LAND GRID ARRAY STRUCTURES AND METHODS FOR ENGINEERING CHANGE
76
Patent #:
Issue Dt:
01/06/2009
Application #:
11414030
Filing Dt:
04/28/2006
Publication #:
Pub Dt:
11/01/2007
Title:
SELECTIVE REWORK PROCESS AND APPARATUS FOR SURFACE MOUNT COMPONENTS
77
Patent #:
Issue Dt:
03/15/2011
Application #:
11414091
Filing Dt:
04/28/2006
Publication #:
Pub Dt:
08/31/2006
Title:
ABRUPT "DELTA-LIKE" DOPING IN SI AND SIGE FILMS BY UHV-CVD
78
Patent #:
Issue Dt:
11/10/2009
Application #:
11415787
Filing Dt:
05/02/2006
Publication #:
Pub Dt:
09/21/2006
Title:
DUAL GATE DIELECTRIC THICKNESS DEVICES AND CIRCUITS USING DUAL GATE DIELECTRIC THICKNESS DEVICES
79
Patent #:
Issue Dt:
11/17/2009
Application #:
11415922
Filing Dt:
05/01/2006
Publication #:
Pub Dt:
11/01/2007
Title:
METHOD FOR FORMING SELF-ALIGNED METAL SILICIDE CONTACTS
80
Patent #:
Issue Dt:
11/20/2007
Application #:
11415923
Filing Dt:
05/01/2006
Publication #:
Pub Dt:
11/01/2007
Title:
WAVEGUIDE POLARIZATION BEAM SPLITTERS AND METHOD OF FABRICATING A WAVEGUIDE WIRE-GRID POLARIZATION BEAM SPLITTER
81
Patent #:
Issue Dt:
12/30/2008
Application #:
11416028
Filing Dt:
05/02/2006
Publication #:
Pub Dt:
09/07/2006
Title:
METHOD OF FABRICATING A MULTILAYERED DIELECTRIC DIFFUSION BARRIER LAYER.
82
Patent #:
Issue Dt:
05/06/2008
Application #:
11416762
Filing Dt:
05/03/2006
Publication #:
Pub Dt:
11/08/2007
Title:
APPARATUSES FOR DISSIPATING HEAT FROM SEMICONDUCTOR DEVICES
83
Patent #:
NONE
Issue Dt:
Application #:
11417146
Filing Dt:
05/04/2006
Publication #:
Pub Dt:
11/08/2007
Title:
Apparatus and method for electrochemical processing of thin films on resistive substrates
84
Patent #:
Issue Dt:
02/19/2008
Application #:
11417626
Filing Dt:
05/04/2006
Publication #:
Pub Dt:
01/17/2008
Title:
SERIAL LINK RECEIVER WITH WIDE INPUT VOLTAGE RANGE AND TOLERANCE TO HIGH POWER VOLTAGE SUPPLY
85
Patent #:
NONE
Issue Dt:
Application #:
11417846
Filing Dt:
05/04/2006
Publication #:
Pub Dt:
11/08/2007
Title:
Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors
86
Patent #:
Issue Dt:
12/18/2007
Application #:
11418052
Filing Dt:
05/04/2006
Publication #:
Pub Dt:
11/08/2007
Title:
METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
87
Patent #:
Issue Dt:
04/15/2008
Application #:
11418921
Filing Dt:
05/05/2006
Publication #:
Pub Dt:
09/14/2006
Title:
ADJUSTABLE SELF-ALIGNED AIR GAP DIELECTRIC FOR LOW CAPACITANCE WIRING
88
Patent #:
Issue Dt:
04/22/2008
Application #:
11419008
Filing Dt:
05/18/2006
Publication #:
Pub Dt:
11/22/2007
Title:
RADIATION HARDENED LATCH
89
Patent #:
Issue Dt:
10/21/2008
Application #:
11419077
Filing Dt:
05/18/2006
Publication #:
Pub Dt:
12/13/2007
Title:
ENHANCED MECHANICAL STRENGTH VIA CONTACTS
90
Patent #:
Issue Dt:
04/07/2009
Application #:
11419217
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF
91
Patent #:
Issue Dt:
11/04/2008
Application #:
11419219
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
METHOD AND SYSTEM FOR UNFOLDING/REPLICATING LOGIC PATHS TO FACILITATE MODELING OF METASTABLE VALUE PROPAGATION
92
Patent #:
Issue Dt:
09/15/2009
Application #:
11419271
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
12/06/2007
Title:
APPARATUS, SYSTEM, AND METHOD FOR DYNAMIC RECOVERY AND RESTORATION FROM DESIGN DEFECTS IN AN INTEGRATED CIRCUIT
93
Patent #:
Issue Dt:
10/14/2008
Application #:
11419308
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES
94
Patent #:
Issue Dt:
10/21/2008
Application #:
11419312
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
STRAINED HOT (HYBRID ORIENTATION TECHNOLOGY) MOSFETS
95
Patent #:
Issue Dt:
09/29/2009
Application #:
11419323
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
METHOD AND APPARATUS FOR COMPENSATING FOR VARIANCES OF A BURIED RESISTOR IN AN INTEGRATED CIRCUIT
96
Patent #:
Issue Dt:
08/24/2010
Application #:
11419329
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
07/29/2010
Title:
ENCLOSED NANOTUBE STRUCTURE AND METHOD FOR FORMING
97
Patent #:
Issue Dt:
04/27/2010
Application #:
11419341
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
ON-CHIP HEATER AND METHODS FOR FABRICATION THEREOF AND USE THEREOF
98
Patent #:
NONE
Issue Dt:
Application #:
11419388
Filing Dt:
05/19/2006
Publication #:
Pub Dt:
11/22/2007
Title:
SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT
99
Patent #:
Issue Dt:
04/01/2008
Application #:
11419811
Filing Dt:
05/23/2006
Publication #:
Pub Dt:
03/20/2008
Title:
HIGH-RESOLUTION OPTICAL CHANNEL FOR NON-DESTRUCTIVE NAVIGATION AND PROCESSING OF INTEGRATED CIRCUITS
100
Patent #:
Issue Dt:
10/09/2007
Application #:
11420047
Filing Dt:
05/24/2006
Title:
N-CHANNEL MOSFETS COMPRISING DUAL STRESSORS, AND METHODS FOR FORMING THE SAME
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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