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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14854
Page 56 of 149
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149
1
Patent #:
7808028
Issue Dt:
10/05/2010
Application #:
11736796
Filing Dt:
04/18/2007
Publication #:
US20080258268
Pub Dt:
10/23/2008
Title:
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
2
Patent #:
7937604
Issue Dt:
05/03/2011
Application #:
11737289
Filing Dt:
04/19/2007
Publication #:
US20080263488
Pub Dt:
10/23/2008
Title:
METHOD FOR GENERATING A SKEW SCHEDULE FOR A CLOCK DISTRIBUTION NETWORK CONTAINING GATING ELEMENTS
3
Patent #:
NONE
Issue Dt:
Application #:
11737304
Filing Dt:
04/19/2007
Publication #:
US20070187800
Pub Dt:
08/16/2007
Title:
RESISTOR TUNING
4
Patent #:
8808453
Issue Dt:
08/19/2014
Application #:
11737447
Filing Dt:
04/19/2007
Publication #:
US20120125260
Pub Dt:
05/24/2012
Title:
SYSTEM FOR ABATING THE SIMULTANEOUS FLOW OF SILANE AND ARSINE
5
Patent #:
7723207
Issue Dt:
05/25/2010
Application #:
11737598
Filing Dt:
04/19/2007
Publication #:
US20070287224
Pub Dt:
12/13/2007
Title:
THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN
6
Patent #:
8027083
Issue Dt:
09/27/2011
Application #:
11737879
Filing Dt:
04/20/2007
Publication #:
US20080259443
Pub Dt:
10/23/2008
Title:
CONTACT MICROSCOPE USING POINT SOURCE ILLUMINATION
7
Patent #:
8372744
Issue Dt:
02/12/2013
Application #:
11737926
Filing Dt:
04/20/2007
Publication #:
US20080261066
Pub Dt:
10/23/2008
Title:
FABRICATING A CONTACT RHODIUM STRUCTURE BY ELECTROPLATING AND ELECTROPLATING COMPOSITION
8
Patent #:
7651902
Issue Dt:
01/26/2010
Application #:
11737989
Filing Dt:
04/20/2007
Publication #:
US20080258181
Pub Dt:
10/23/2008
Title:
HYBRID SUBSTRATES AND METHODS FOR FORMING SUCH HYBRID SUBSTRATES
9
Patent #:
8901685
Issue Dt:
12/02/2014
Application #:
11738032
Filing Dt:
04/20/2007
Publication #:
US20070224454
Pub Dt:
09/27/2007
Title:
MAGNETIC MATERIALS HAVING SUPERPARAMAGNETIC PARTICLES
10
Patent #:
7870417
Issue Dt:
01/11/2011
Application #:
11738142
Filing Dt:
04/20/2007
Publication #:
US20080263255
Pub Dt:
10/23/2008
Title:
APPARATUS, SYSTEM, AND METHOD FOR ADAPTER CARD FAILOVER
11
Patent #:
NONE
Issue Dt:
Application #:
11738150
Filing Dt:
04/20/2007
Publication #:
US20080263391
Pub Dt:
10/23/2008
Title:
Apparatus, System, and Method For Adapter Card Failover
12
Patent #:
7897480
Issue Dt:
03/01/2011
Application #:
11738837
Filing Dt:
04/23/2007
Publication #:
US20080261055
Pub Dt:
10/23/2008
Title:
PREPARATION OF HIGH QUALITY STRAINED-SEMICONDUCTOR DIRECTLY-ON-INSULATOR SUBSTRATES
13
Patent #:
NONE
Issue Dt:
Application #:
11739251
Filing Dt:
04/24/2007
Publication #:
US20080270965
Pub Dt:
10/30/2008
Title:
METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM
14
Patent #:
NONE
Issue Dt:
Application #:
11739723
Filing Dt:
04/25/2007
Publication #:
US20080266735
Pub Dt:
10/30/2008
Title:
Implementing APS Voltage Level Activation With Secondary Chip in Stacked-Chip Technology
15
Patent #:
7405940
Issue Dt:
07/29/2008
Application #:
11739773
Filing Dt:
04/25/2007
Title:
PISTON RESET APPARATUS FOR A MULTICHIP MODULE AND METHOD FOR RESETTING PISTONS IN THE SAME
16
Patent #:
7354805
Issue Dt:
04/08/2008
Application #:
11739979
Filing Dt:
04/25/2007
Publication #:
US20070190697
Pub Dt:
08/16/2007
Title:
METHOD OF MAKING ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY
17
Patent #:
NONE
Issue Dt:
Application #:
11740325
Filing Dt:
04/26/2007
Publication #:
US20080265428
Pub Dt:
10/30/2008
Title:
VIA AND SOLDER BALL SHAPES TO MAXIMIZE CHIP OR SILICON CARRIER STRENGTH RELATIVE TO THERMAL OR BENDING LOAD ZERO POINT
18
Patent #:
NONE
Issue Dt:
Application #:
11740442
Filing Dt:
04/26/2007
Publication #:
US20080265343
Pub Dt:
10/30/2008
Title:
FIELD EFFECT TRANSISTOR WITH INVERTED T SHAPED GATE ELECTRODE AND METHODS FOR FABRICATION THEREOF
19
Patent #:
7937618
Issue Dt:
05/03/2011
Application #:
11740556
Filing Dt:
04/26/2007
Publication #:
US20080270838
Pub Dt:
10/30/2008
Title:
DISTRIBUTED, FAULT-TOLERANT AND HIGHLY AVAILABLE COMPUTING SYSTEM
20
Patent #:
8025812
Issue Dt:
09/27/2011
Application #:
11741017
Filing Dt:
04/27/2007
Publication #:
US20080264898
Pub Dt:
10/30/2008
Title:
SELECTIVE ETCH OF TIW FOR CAPTURE PAD FORMATION
21
Patent #:
7446004
Issue Dt:
11/04/2008
Application #:
11741034
Filing Dt:
04/27/2007
Publication #:
US20070254443
Pub Dt:
11/01/2007
Title:
METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
22
Patent #:
7688095
Issue Dt:
03/30/2010
Application #:
11741345
Filing Dt:
04/27/2007
Publication #:
US20080030209
Pub Dt:
02/07/2008
Title:
INTERPOSER STRUCTURES AND METHODS OF MANUFACTURING THE SAME
23
Patent #:
7898061
Issue Dt:
03/01/2011
Application #:
11741436
Filing Dt:
04/27/2007
Publication #:
US20070200201
Pub Dt:
08/30/2007
Title:
STRUCTURE FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS
24
Patent #:
7312134
Issue Dt:
12/25/2007
Application #:
11741441
Filing Dt:
04/27/2007
Publication #:
US20070202639
Pub Dt:
08/30/2007
Title:
DUAL STRESSED SOI SUBSTRATES
25
Patent #:
7937250
Issue Dt:
05/03/2011
Application #:
11741555
Filing Dt:
04/27/2007
Publication #:
US20080270087
Pub Dt:
10/30/2008
Title:
METHOD AND SYSTEM FOR ADDRESSING NON-FUNCTIONAL CONCERNS
26
Patent #:
NONE
Issue Dt:
Application #:
11741781
Filing Dt:
04/30/2007
Publication #:
US20080265234
Pub Dt:
10/30/2008
Title:
METHOD OF FORMING PHASE CHANGE MEMORY CELL WITH REDUCED SWITCHABLE VOLUME
27
Patent #:
8115251
Issue Dt:
02/14/2012
Application #:
11741898
Filing Dt:
04/30/2007
Publication #:
US20080268588
Pub Dt:
10/30/2008
Title:
RECESSED GATE CHANNEL WITH LOW VT CORNER
28
Patent #:
NONE
Issue Dt:
Application #:
11741908
Filing Dt:
04/30/2007
Publication #:
US20080265377
Pub Dt:
10/30/2008
Title:
AIR GAP WITH SELECTIVE PINCHOFF USING AN ANTI-NUCLEATION LAYER
29
Patent #:
7835564
Issue Dt:
11/16/2010
Application #:
11742095
Filing Dt:
04/30/2007
Publication #:
US20080270081
Pub Dt:
10/30/2008
Title:
NON-DESTRUCTIVE, BELOW-SURFACE DEFECT RENDERING USING IMAGE INTENSITY ANALYSIS
30
Patent #:
7945433
Issue Dt:
05/17/2011
Application #:
11742100
Filing Dt:
04/30/2007
Publication #:
US20080270748
Pub Dt:
10/30/2008
Title:
HARDWARE SIMULATION ACCELERATOR DESIGN AND METHOD THAT EXPLOITS A PARALLEL STRUCTURE OF USER MODELS TO SUPPORT A LARGER USER MODEL SIZE
31
Patent #:
7390730
Issue Dt:
06/24/2008
Application #:
11742147
Filing Dt:
04/30/2007
Publication #:
US20070202637
Pub Dt:
08/30/2007
Title:
METHOD OF FABRICATING A BODY CAPACITOR FOR SOI MEMORY
32
Patent #:
7898076
Issue Dt:
03/01/2011
Application #:
11742161
Filing Dt:
04/30/2007
Publication #:
US20080265404
Pub Dt:
10/30/2008
Title:
STRUCTURE AND METHODS OF PROCESSING FOR SOLDER THERMAL INTERFACE MATERIALS FOR CHIP COOLING
33
Patent #:
7446025
Issue Dt:
11/04/2008
Application #:
11742180
Filing Dt:
04/30/2007
Publication #:
US20070202674
Pub Dt:
08/30/2007
Title:
METHOD OF FORMING VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT
34
Patent #:
8140301
Issue Dt:
03/20/2012
Application #:
11742227
Filing Dt:
04/30/2007
Publication #:
US20080270088
Pub Dt:
10/30/2008
Title:
METHOD AND SYSTEM FOR CAUSAL MODELING AND OUTLIER DETECTION
35
Patent #:
8081280
Issue Dt:
12/20/2011
Application #:
11742474
Filing Dt:
04/30/2007
Publication #:
US20080266502
Pub Dt:
10/30/2008
Title:
METHOD OF PRODUCING UV STABLE LIQUID CRYSTAL ALIGNMENT
36
Patent #:
NONE
Issue Dt:
Application #:
11743101
Filing Dt:
05/01/2007
Publication #:
US20080272437
Pub Dt:
11/06/2008
Title:
Threshold Adjustment for High-K Gate Dielectric CMOS
37
Patent #:
7408800
Issue Dt:
08/05/2008
Application #:
11743686
Filing Dt:
05/03/2007
Title:
APPARATUS AND METHOD FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY
38
Patent #:
7872334
Issue Dt:
01/18/2011
Application #:
11744234
Filing Dt:
05/04/2007
Publication #:
US20080273280
Pub Dt:
11/06/2008
Title:
CARBON NANOTUBE DIODES AND ELECTROSTATIC DISCHARGE CIRCUITS AND METHODS
39
Patent #:
7791166
Issue Dt:
09/07/2010
Application #:
11744248
Filing Dt:
05/04/2007
Publication #:
US20080272457
Pub Dt:
11/06/2008
Title:
FORMATION OF DUMMY FEATURES AND INDUCTORS IN SEMICONDUCTOR FABRICATION
40
Patent #:
7414878
Issue Dt:
08/19/2008
Application #:
11744288
Filing Dt:
05/04/2007
Title:
METHOD FOR IMPLEMENTING DOMINO SRAM LEAKAGE CURRENT REDUCTION
41
Patent #:
NONE
Issue Dt:
Application #:
11744482
Filing Dt:
05/04/2007
Publication #:
US20070204246
Pub Dt:
08/30/2007
Title:
METHOD AND SYSTEM FOR LOGIC VERIFICATION USING MIRROR INTERFACE
42
Patent #:
7445977
Issue Dt:
11/04/2008
Application #:
11744600
Filing Dt:
05/04/2007
Publication #:
US20070218647
Pub Dt:
09/20/2007
Title:
METHOD OF CREATING DEFECT FREE HIGH GE CONTENT (> 25%) SIGE-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES
43
Patent #:
7877712
Issue Dt:
01/25/2011
Application #:
11744980
Filing Dt:
05/07/2007
Publication #:
US20080282209
Pub Dt:
11/13/2008
Title:
SYSTEM FOR AND METHOD OF VERIFYING IC AUTHENTICITY
44
Patent #:
7809542
Issue Dt:
10/05/2010
Application #:
11745085
Filing Dt:
05/07/2007
Publication #:
US20080281574
Pub Dt:
11/13/2008
Title:
SYSTEM AND METHOD FOR GLITCH ANALYSIS IN CIRCUITS
45
Patent #:
7521808
Issue Dt:
04/21/2009
Application #:
11745610
Filing Dt:
05/08/2007
Publication #:
US20070207604
Pub Dt:
09/06/2007
Title:
WIRING PATERNS FORMED BY SELECTIVE METAL PLATING
46
Patent #:
7608851
Issue Dt:
10/27/2009
Application #:
11745811
Filing Dt:
05/08/2007
Publication #:
US20080277644
Pub Dt:
11/13/2008
Title:
SWITCH ARRAY CIRCUIT AND SYSTEM USING PROGRAMMABLE VIA STRUCTURES WITH PHASE CHANGE MATERIALS
47
Patent #:
7375657
Issue Dt:
05/20/2008
Application #:
11745970
Filing Dt:
05/08/2007
Publication #:
US20070205924
Pub Dt:
09/06/2007
Title:
METHOD AND SYSTEM FOR PERFORMING STREAMING OF ENCODED DATA
48
Patent #:
NONE
Issue Dt:
Application #:
11746508
Filing Dt:
05/09/2007
Publication #:
US20070205515
Pub Dt:
09/06/2007
Title:
DEVICE HAVING A REDUNDANT STRUCTURE
49
Patent #:
NONE
Issue Dt:
Application #:
11746680
Filing Dt:
05/10/2007
Publication #:
US20080277778
Pub Dt:
11/13/2008
Title:
Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
50
Patent #:
7955955
Issue Dt:
06/07/2011
Application #:
11746684
Filing Dt:
05/10/2007
Publication #:
US20080277765
Pub Dt:
11/13/2008
Title:
USING CRACK ARRESTOR FOR INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES
51
Patent #:
7863124
Issue Dt:
01/04/2011
Application #:
11746759
Filing Dt:
05/10/2007
Publication #:
US20080280404
Pub Dt:
11/13/2008
Title:
RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES
52
Patent #:
7885798
Issue Dt:
02/08/2011
Application #:
11746976
Filing Dt:
05/10/2007
Publication #:
US20080281570
Pub Dt:
11/13/2008
Title:
CLOSED-LOOP MODELING OF GATE LEAKAGE FOR FAST SIMULATORS
53
Patent #:
7821110
Issue Dt:
10/26/2010
Application #:
11747342
Filing Dt:
05/11/2007
Publication #:
US20080277773
Pub Dt:
11/13/2008
Title:
CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYER(S) CONFIGURED TO BLOCK ELECTROMAGNETIC INTERFERENCE
54
Patent #:
8108750
Issue Dt:
01/31/2012
Application #:
11747887
Filing Dt:
05/11/2007
Publication #:
US20080016413
Pub Dt:
01/17/2008
Title:
RAID 3 + 3
55
Patent #:
7750429
Issue Dt:
07/06/2010
Application #:
11748521
Filing Dt:
05/15/2007
Publication #:
US20080283962
Pub Dt:
11/20/2008
Title:
SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE
56
Patent #:
7864502
Issue Dt:
01/04/2011
Application #:
11748560
Filing Dt:
05/15/2007
Publication #:
US20080285202
Pub Dt:
11/20/2008
Title:
IN SITU MONITORING OF WAFER CHARGE DISTRIBUTION IN PLASMA PROCESSING
57
Patent #:
7415695
Issue Dt:
08/19/2008
Application #:
11748575
Filing Dt:
05/15/2007
Publication #:
US20070211933
Pub Dt:
09/13/2007
Title:
SYSTEM FOR SEARCH AND ANALYSIS OF SYSTEMATIC DEFECTS IN INTEGRATED CIRCUITS
58
Patent #:
8679918
Issue Dt:
03/25/2014
Application #:
11748576
Filing Dt:
05/15/2007
Publication #:
US20070212834
Pub Dt:
09/13/2007
Title:
MULTIPLE-GATE DEVICE WITH FLOATING BACK GATE
59
Patent #:
7378678
Issue Dt:
05/27/2008
Application #:
11748579
Filing Dt:
05/15/2007
Publication #:
US20070212810
Pub Dt:
09/13/2007
Title:
MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS
60
Patent #:
7823035
Issue Dt:
10/26/2010
Application #:
11748736
Filing Dt:
05/15/2007
Publication #:
US20080288841
Pub Dt:
11/20/2008
Title:
SYSTEM AND METHODS OF BALANCING SCAN CHAINS AND INSERTING THE BALANCED-LENGTH SCAN CHAINS INTO HIERARCHICALLY DESIGNED INTEGRATED CIRCUITS.
61
Patent #:
8341612
Issue Dt:
12/25/2012
Application #:
11749295
Filing Dt:
05/16/2007
Publication #:
US20080288929
Pub Dt:
11/20/2008
Title:
METHOD AND APPARATUS FOR RUN-TIME STATISTICS DEPENDENT PROGRAM EXECUTION USING SOURCE-CODING
62
Patent #:
7781733
Issue Dt:
08/24/2010
Application #:
11749350
Filing Dt:
05/16/2007
Publication #:
US20080283777
Pub Dt:
11/20/2008
Title:
IN-SITU HIGH-RESOLUTION LIGHT-OPTICAL CHANNEL FOR OPTICAL VIEWING AND SURFACE PROCESSING IN PARALLEL WITH CHARGED PARTICLE (FIB AND SEM) TECHNIQUES
63
Patent #:
8110321
Issue Dt:
02/07/2012
Application #:
11749384
Filing Dt:
05/16/2007
Publication #:
US20080286660
Pub Dt:
11/20/2008
Title:
METHOD OF MANUFACTURE OF DAMASCENE RETICLE
64
Patent #:
7682941
Issue Dt:
03/23/2010
Application #:
11749417
Filing Dt:
05/16/2007
Publication #:
US20070212857
Pub Dt:
09/13/2007
Title:
INTEGRATED CIRCUIT WITH BULK AND SOI DEVICES CONNECTED WITH AN EPITAXIAL REGION
65
Patent #:
7486208
Issue Dt:
02/03/2009
Application #:
11749711
Filing Dt:
05/16/2007
Publication #:
US20080284624
Pub Dt:
11/20/2008
Title:
HIGH-RATE RLL ENCODING
66
Patent #:
7560345
Issue Dt:
07/14/2009
Application #:
11749775
Filing Dt:
05/17/2007
Publication #:
US20070212799
Pub Dt:
09/13/2007
Title:
METHOD OF ASSESSING POTENTIAL FOR CHARGING DAMAGE IN INTEGRATED CIRCUIT DESIGNS AND STRUCTURES FOR PREVENTING CHARGING DAMAGE
67
Patent #:
7790611
Issue Dt:
09/07/2010
Application #:
11749898
Filing Dt:
05/17/2007
Publication #:
US20080284021
Pub Dt:
11/20/2008
Title:
METHOD FOR FEOL AND BEOL WIRING
68
Patent #:
7799503
Issue Dt:
09/21/2010
Application #:
11750026
Filing Dt:
05/17/2007
Publication #:
US20080286683
Pub Dt:
11/20/2008
Title:
COMPOSITE STRUCTURES TO PREVENT PATTERN COLLAPSE
69
Patent #:
8009430
Issue Dt:
08/30/2011
Application #:
11750322
Filing Dt:
05/17/2007
Publication #:
US20080285232
Pub Dt:
11/20/2008
Title:
TECHNIQUES FOR DATA CENTER COOLING
70
Patent #:
7682896
Issue Dt:
03/23/2010
Application #:
11750355
Filing Dt:
05/18/2007
Publication #:
US20070218625
Pub Dt:
09/20/2007
Title:
TRENCH METAL-INSULATOR-METAL (MIM) CAPACITORS INTEGRATED WITH MIDDLE-OF-LINE METAL CONTACTS, AND METHOD OF FABRICATING SAME
71
Patent #:
7867689
Issue Dt:
01/11/2011
Application #:
11750356
Filing Dt:
05/18/2007
Publication #:
US20080286467
Pub Dt:
11/20/2008
Title:
METHOD OF USE FOR PHOTOPATTERNABLE DIELECTRIC MATERIALS FOR BEOL APPLICATIONS
72
Patent #:
NONE
Issue Dt:
Application #:
11750423
Filing Dt:
05/18/2007
Publication #:
US20070222015
Pub Dt:
09/27/2007
Title:
TRENCH PHOTODETECTOR
73
Patent #:
8636931
Issue Dt:
01/28/2014
Application #:
11750559
Filing Dt:
05/18/2007
Publication #:
US20080284052
Pub Dt:
11/20/2008
Title:
VACUUM EXTRUSION METHOD OF MANUFACTURING A THERMAL PASTE
74
Patent #:
8513791
Issue Dt:
08/20/2013
Application #:
11750631
Filing Dt:
05/18/2007
Publication #:
US20080283995
Pub Dt:
11/20/2008
Title:
COMPACT MULTI-PORT CAM CELL IMPLEMENTED IN 3D VERTICAL INTEGRATION
75
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
SOI FET WITH SOURCE-SIDE BODY DOPING
Assignors
1
GLOBALFOUNDRIES U.S. 2 LLC
Exec Dt:
09/10/2015
2
GLOBALFOUNDRIES U.S. INC.
Exec Dt:
09/10/2015
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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