|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11757660
|
Filing Dt:
|
06/04/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
METHOD OF DOPING A GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/10/2009
|
Application #:
|
11758128
|
Filing Dt:
|
06/05/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
OPTIMIZED THERMALLY CONDUCTIVE PLATE AND ATTACHMENT METHOD FOR ENHANCED THERMAL PERFORMANCE AND RELIABILITY OF FLIP CHIP ORGANIC PACKAGES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11758265
|
Filing Dt:
|
06/05/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11758277
|
Filing Dt:
|
06/05/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MAPPING A LOGICAL DESIGN ONTO AN INTEGRATED CIRCUIT WITH SLACK APPORTIONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11758291
|
Filing Dt:
|
06/05/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
DUAL STRESS MEMORIZATION TECHNIQUE FOR CMOS APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
11758457
|
Filing Dt:
|
06/05/2007
|
Publication #:
|
|
Pub Dt:
|
08/23/2012
| | | | |
Title:
|
SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
11758746
|
Filing Dt:
|
06/06/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
CHANGING AN ELECTRICAL RESISTANCE OF A RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
11758752
|
Filing Dt:
|
06/06/2007
|
Publication #:
|
|
Pub Dt:
|
10/25/2007
| | | | |
Title:
|
GLOBAL VACUUM INJECTION MOLDED SOLDER SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11759332
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN FOR ATTAINING POWER CLOSURE WHILE MAINTAINING EXISTING DESIGN CONSTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
11759396
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
OUT OF BAND SIGNALING ENHANCEMENT FOR HIGH SPEED SERIAL DRIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11759426
|
Filing Dt:
|
06/07/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11759981
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
WELL ISOLATION TRENCHES (WIT) FOR CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
11760030
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR USING CARBON BASED STRESS LINER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11760253
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
STRUCTURE FOR LATCHUP SUPPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
11760288
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/2009
|
Application #:
|
11760477
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SIO2
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11760575
|
Filing Dt:
|
06/08/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
CHANGING CHIP FUNCTION BASED ON FUSE STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11760813
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
AIR BEARING GAP CONTROL FOR INJECTION MOLDED SOLDER HEADS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
11760856
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
LOW VOLTAGE HEAD ROOM DETECTION FOR RELIABLE START-UP OF SELF-BIASED ANALOG CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11760885
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
TWO STEP PHOTORESIST STRIPPING METHOD SEQUENTIALLY USING ION ACTIVATED AND NON-ION ACTIVATED NITROGEN CONTAINING PLASMAS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11760992
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
MULTI-LAYER MASK METHOD FOR PATTERNED STRUCTURE ETHCING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
11761043
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
USE OF A SYMMETRIC RESISTIVE MEMORY MATERIAL AS A DIODE TO DRIVE SYMMETRIC OR ASYMMETRIC RESISTIVE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11761234
|
Filing Dt:
|
06/11/2007
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
METHOD FOR DIRECT HEAT SINK ATTACHMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11761403
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
ELECTRICAL FUSE WITH SUBLITHOGRAPHIC DIMENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/2010
|
Application #:
|
11761438
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11761485
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
MASK LAYOUT EDITOR SHAPE QUERY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2009
|
Application #:
|
11761568
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
11761610
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
11761655
|
Filing Dt:
|
06/12/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11762130
|
Filing Dt:
|
06/13/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR COUPLED NOISE TIMING VIOLATION AVOIDANCE IN DETAILED ROUTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
11762229
|
Filing Dt:
|
06/13/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR COMPONENT ASSOCIATION INFERENCE, FAILURE DIAGNOSIS AND MISCONFIGURATION DETECTION BASED ON HISTORICAL FAILURE DATA
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11762339
|
Filing Dt:
|
06/13/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
3-D SRAM ARRAY TO IMPROVE STABILITY AND PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11762376
|
Filing Dt:
|
06/13/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
STRUCTURE AND METHOD OF INTEGRATING COMPOUND AND ELEMENTAL SEMICONDUCTORS FOR HIGH-PERFORMANCE CMOS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11762405
|
Filing Dt:
|
06/13/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
|
Application #:
|
11762811
|
Filing Dt:
|
06/14/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
VERTICAL CURRENT CONTROLLED SILICON ON INSULATOR (SOI) DEVICE SUCH AS A SILICON CONTROLLED RECTIFIER AND METHOD OF FORMING VERTICAL SOI CURRENT CONTROLLED DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11763047
|
Filing Dt:
|
06/14/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
CMOS TRANSISTORS WITH DIFFERENTIAL OXYGEN CONTENT HIGH-K DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
11763135
|
Filing Dt:
|
06/14/2007
|
Publication #:
|
|
Pub Dt:
|
10/04/2007
| | | | |
Title:
|
RELIABLE BEOL INTEGRATION PROCESS WITH DIRECT CMP OF POROUS SICOH DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11763411
|
Filing Dt:
|
06/14/2007
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11763499
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
PIN GRID ARRAY ZERO INSERTION FORCE CONNECTORS CONFIGURABLE FOR SUPPORTING LARGE PIN COUNTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11763669
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
01/31/2008
| | | | |
Title:
|
SELF-REFERENCED MATCH-LINE SENSE AMPLIFIER FOR CONTENT ADDRESSABLE MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2008
|
Application #:
|
11763687
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
VOLTAGE CONTROLLED STATIC RANDOM ACCESS MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
11763781
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11763808
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
11/15/2007
| | | | |
Title:
|
SYSTEM AND METHOD OF AUTOMATICALLY GENERATING KERF DESIGN DATA
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11763829
|
Filing Dt:
|
06/15/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
DIFFUSION BARRIER WITH LOW DIELECTRIC CONSTANT AND SEMICONDUCTOR DEVICE CONTAINING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11764237
|
Filing Dt:
|
06/18/2007
|
Publication #:
|
|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
SENSE-AMPLIFIER ASSIST (SAA) WITH POWER-REDUCTION TECHNIQUE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
11764388
|
Filing Dt:
|
06/18/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH MINIMIZED PARASITICS AND METHOD OF FABRICATING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11764571
|
Filing Dt:
|
06/18/2007
|
Publication #:
|
|
Pub Dt:
|
10/18/2007
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION AND METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11764678
|
Filing Dt:
|
06/18/2007
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE WITH PILLAR BOTTOM ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
11764817
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
DEVICE, SYSTEM AND METHOD OF GENERATING A HARDWARE-VERIFICATION TEST CASE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
11764876
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
METHOD AND APPARATUS FOR RATELESS SOURCE CODING WITH/WITHOUT DECODER SIDE INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
11764948
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR INCORPORATING AT LEAST ONE STRUCTURE FOR IMPARTING TEMPERATURE-DEPENDENT STRAIN ON THE CHANNEL REGION AND ASSOCIATED METHOD OF FORMING THE TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
11765055
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
DIRECT EDGE CONNECTION FOR MULTI-CHIP INTEGRATED CIRCUITS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11765142
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
Method for Fabricating an Electrolytic Device Based on a Solution-Processed Electrolyte
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
11765396
|
Filing Dt:
|
06/19/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
PROCEDURE SUMMARIES FOR POINTER ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11765485
|
Filing Dt:
|
06/20/2007
|
Publication #:
|
|
Pub Dt:
|
10/11/2007
| | | | |
Title:
|
BODY POTENTIAL IMAGER CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
11765931
|
Filing Dt:
|
06/20/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
|
FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11766261
|
Filing Dt:
|
06/21/2007
|
Publication #:
|
|
Pub Dt:
|
12/25/2008
| | | | |
Title:
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METAL CAP WITH ULTRA-LOW K DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS
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Patent #:
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Issue Dt:
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12/21/2010
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Application #:
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11766268
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Filing Dt:
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06/21/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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ROBUST CABLE CONNECTIVITY TEST RECEIVER FOR HIGH-SPEED DATA RECEIVER
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Patent #:
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Issue Dt:
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08/10/2010
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Application #:
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11766475
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Filing Dt:
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06/21/2007
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Publication #:
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Pub Dt:
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10/25/2007
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Title:
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SYSTEM AND PROGRAM PRODUCT FOR FACILITATING FORWARDING OF DATA PACKETS THROUGH A NODE OF A DATA TRANSFER NETWORK USING MULTIPLE TYPES OF FORWARDING TABLES
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Patent #:
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Issue Dt:
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10/18/2011
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Application #:
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11766533
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Filing Dt:
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06/21/2007
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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METHOD AND APPARATUS FOR CHIP COOLING
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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11766820
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Filing Dt:
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06/22/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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DETERMINING AZIMUTH ANGLE OF INCIDENT BEAM TO WAFER
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Patent #:
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Issue Dt:
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10/26/2010
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Application #:
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11766869
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Filing Dt:
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06/22/2007
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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METHOD AND STRUCTURE FOR A PULL TEST FOR CONTROLLED COLLAPSE CHIP CONNECTIONS AND BALL LIMITING METALLURGY
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11767188
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Filing Dt:
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06/22/2007
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Publication #:
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Pub Dt:
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01/03/2008
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Title:
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BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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11767545
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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SYSTEM AND METHOD TO PROTECT COMPUTING SYSTEMS
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Patent #:
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Issue Dt:
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10/12/2010
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Application #:
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11767616
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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11767627
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11767789
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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PROVIDING GAPS IN CAPPING LAYER TO REDUCE TENSILE STRESS FOR BEOL FABRICATION OF INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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11767796
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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SEGREGATING WAFER CARRIER TYPES IN SEMICONDUCTOR STORAGE DEVICES
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Patent #:
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Issue Dt:
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06/09/2009
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Application #:
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11767850
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
| | | | |
Title:
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THERMAL ENERGY REMOVAL STRUCTURE AND METHOD
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11768208
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Filing Dt:
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06/26/2007
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Publication #:
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Pub Dt:
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12/27/2007
| | | | |
Title:
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PROGRAMMABLE SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/02/2010
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Application #:
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11768254
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Filing Dt:
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06/26/2007
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Publication #:
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Pub Dt:
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10/25/2007
| | | | |
Title:
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ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND METHODS OF FABRICATION THEREOF
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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11768266
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Filing Dt:
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06/26/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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METHOD OF DOPING FIELD-EFFECT-TRANSISTORS (FETS) WITH REDUCED STRESS/STRAIN RELAXATION AND RESULTING FET DEVICES
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11769064
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Filing Dt:
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06/27/2007
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Publication #:
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Pub Dt:
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11/15/2007
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Title:
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SELF HEATING MONITOR FOR SIGE AND SOI CMOS DEVICES
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Patent #:
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Issue Dt:
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07/28/2009
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Application #:
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11769089
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Filing Dt:
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06/27/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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FUSED AROMATIC STRUCTURES AND METHODS FOR PHOTOLITHOGRAPHIC APPLICATIONS
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Patent #:
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Issue Dt:
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07/10/2012
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Application #:
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11769128
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Filing Dt:
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06/27/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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TRANSMITTER BANDWIDTH OPTIMIZATION CIRCUIT
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11769408
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Filing Dt:
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06/27/2007
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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METHOD AND SYSTEM FOR HIGH FREQUENCY CLOCK SIGNAL GATING
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11770013
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Filing Dt:
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06/28/2007
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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METHOD AND SYSTEM FOR DETERMINISTIC BIST
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Patent #:
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|
Issue Dt:
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10/05/2010
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Application #:
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11770105
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Filing Dt:
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06/28/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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WAFER AND STAGE ALIGNMENT USING PHOTONIC DEVICES
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|
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Patent #:
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|
Issue Dt:
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10/12/2010
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Application #:
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11770303
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Filing Dt:
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06/28/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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SELECTABLE DEVICE OPTIONS FOR CHARACTERIZING SEMICONDUCTOR DEVICES
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|
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Patent #:
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Issue Dt:
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03/30/2010
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Application #:
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11770455
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Filing Dt:
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06/28/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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CMOS-PROCESS-COMPATIBLE PROGRAMMABLE VIA DEVICE
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|
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11770783
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
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Integrated Fin-Local Interconnect Structure
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|
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Patent #:
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NONE
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Issue Dt:
|
|
Application #:
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11770798
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Filing Dt:
|
06/29/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures
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|
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11770843
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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CHARGE CARRIER BARRIER FOR IMAGE SENSOR
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Patent #:
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NONE
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Issue Dt:
|
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Application #:
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11770867
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
Phase Locked Loop with Stabilized Dynamic Response
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|
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Patent #:
|
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Issue Dt:
|
08/02/2011
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Application #:
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11770908
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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METHODS OF FORMING ALTERNATING REGIONS OF SI AND SIGE OR SIGEC ON A BURIED OXIDE LAYER ON A SUBSTRATE
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|
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Patent #:
|
|
Issue Dt:
|
05/18/2010
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Application #:
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11770928
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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METAL INTERCONNECT FORMING METHODS AND IC CHIP INCLUDING METAL INTERCONNECT
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|
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Patent #:
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Issue Dt:
|
08/17/2010
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Application #:
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11770993
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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12/13/2007
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Title:
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METHOD OF CONTROLLING GRAIN SIZE IN A POLYSILICON LAYER AND IN SEMICONDUCTOR DEVICES HAVING POLYSILICON STRUCTURE
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Patent #:
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Issue Dt:
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09/14/2010
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Application #:
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11771033
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
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PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR
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|
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Patent #:
|
|
Issue Dt:
|
05/11/2010
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Application #:
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11771390
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
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01/01/2009
| | | | |
Title:
|
SYSTEM AND METHOD FOR FAULT MAPPING OF EXCEPTIONS ACROSS PROGRAMMING MODELS
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|
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Patent #:
|
|
Issue Dt:
|
04/26/2011
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Application #:
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11771457
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Filing Dt:
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06/29/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL WITH VERTICAL TRANSISTOR
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|
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Patent #:
|
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Issue Dt:
|
03/15/2011
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Application #:
|
11771501
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Filing Dt:
|
06/29/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
PHASE CHANGE MEMORY WITH TAPERED HEATER
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|
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Patent #:
|
|
Issue Dt:
|
04/26/2011
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Application #:
|
11771854
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Filing Dt:
|
06/29/2007
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Publication #:
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Pub Dt:
|
01/01/2009
| | | | |
Title:
|
POLYMERIC MATERIAL, METHOD OF FORMING THE POLYMERIC MATERIAL, AND METHOD OF FORMING A THIN FILM USING THE POLYMERIC MATERIAL
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|
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Patent #:
|
|
Issue Dt:
|
06/28/2011
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Application #:
|
11772347
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Filing Dt:
|
07/02/2007
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Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
MULTI-BIT ERROR CORRECTION SCHEME IN MULTI-LEVEL MEMORY STORAGE SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11772356
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Filing Dt:
|
07/02/2007
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Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
MULTI-BIT ERROR CORRECTION SCHEME IN MULTI-LEVEL MEMORY STORAGE SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
11772418
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Filing Dt:
|
07/02/2007
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Publication #:
|
|
Pub Dt:
|
12/06/2007
| | | | |
Title:
|
DIGITAL RELIABILITY MONITOR HAVING AUTONOMIC REPAIR AND NOTIFICATION CAPABILITY
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|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
11772464
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Filing Dt:
|
07/02/2007
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Publication #:
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|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
ANTENNA ARRAY FEED LINE STRUCTURES FOR MILLIMETER WAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11772592
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Filing Dt:
|
07/02/2007
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Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
SHIFT REGISTER LATCH WITH EMBEDDED DYNAMIC RANDOM ACCESS MEMORY SCAN ONLY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11772899
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Filing Dt:
|
07/03/2007
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Publication #:
|
|
Pub Dt:
|
11/01/2007
| | | | |
Title:
|
AIR-GAP INSULATED INTERCONNECTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
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Application #:
|
11772908
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Filing Dt:
|
07/03/2007
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Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
EFFICIENT UTILIZATION OF A MULTI-SOURCE NETWORK OF CONTROL LOGIC TO ACHIEVE TIMING CLOSURE IN A CLOCKED LOGIC CIRCUIT
|
|
|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
11773160
|
Filing Dt:
|
07/03/2007
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
METHOD FOR DEPOSITION OF AN ULTRA-THIN ELECTROPOSITIVE METAL-CONTAINING CAP LAYER
|
|