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Reel/Frame:	036779/0001			Pages:	985
		Recorded:	10/05/2015
Attorney Dkt #:	3718.266
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 14854
Page 58 of 149
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Patent #:	7485520	Issue Dt:	02/03/2009	Application #:	11773607	Filing Dt:	07/05/2007
Publication #:	US20090008705	Pub Dt:	01/08/2009
Title:	BODY-CONTACTED FINFET

Patent #:	7670497	Issue Dt:	03/02/2010	Application #:	11774041	Filing Dt:	07/06/2007
Publication #:	US20090008361	Pub Dt:	01/08/2009
Title:	OXIDANT AND PASSIVANT COMPOSITION AND METHOD FOR USE IN TREATING A MICROELECTRONIC STRUCTURE

Patent #:	7816747	Issue Dt:	10/19/2010	Application #:	11774087	Filing Dt:	07/06/2007
Publication #:	US20080251870	Pub Dt:	10/16/2008
Title:	DETECTOR FOR DETECTING ELECTROMAGNETIC WAVES

Patent #:	NONE	Issue Dt:		Application #:	11774105	Filing Dt:	07/06/2007
Publication #:	US20090011577	Pub Dt:	01/08/2009
Title:	METHOD OF MAKING PHASE CHANGE MATERIALS ELECTROCHEMICAL ATOMIC LAYER DEPOSITION

Patent #:	7720800	Issue Dt:	05/18/2010	Application #:	11774163	Filing Dt:	07/06/2007
Publication #:	US20090013010	Pub Dt:	01/08/2009
Title:	METHOD AND APPROACH TO HOSTING VERSIONED WEB SERVICES

Patent #:	7723750	Issue Dt:	05/25/2010	Application #:	11774221	Filing Dt:	07/06/2007
Publication #:	US20070252203	Pub Dt:	11/01/2007
Title:	MOSFET WITH SUPER-STEEP RETROGRADED ISLAND

Patent #:	7979724	Issue Dt:	07/12/2011	Application #:	11774245	Filing Dt:	07/06/2007
Publication #:	US20070255970	Pub Dt:	11/01/2007
Title:	SYSTEM AND METHOD FOR DYNAMICALLY MANAGING POWER CONSUMPTION OF INTEGRATED CIRCUITRY

Patent #:	7606067	Issue Dt:	10/20/2009	Application #:	11774539	Filing Dt:	07/06/2007
Publication #:	US20090013146	Pub Dt:	01/08/2009
Title:	METHOD TO CREATE A UNIFORMLY DISTRIBUTED MULTI-LEVEL CELL (MLC) BITSTREAM FROM A NON-UNIFORM MLC BITSTREAM

Patent #:	7645650	Issue Dt:	01/12/2010	Application #:	11774663	Filing Dt:	07/09/2007
Publication #:	US20070254438	Pub Dt:	11/01/2007
Title:	DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION

Patent #:	7381627	Issue Dt:	06/03/2008	Application #:	11774853	Filing Dt:	07/09/2007
Publication #:	US20070267698	Pub Dt:	11/22/2007
Title:	DUAL WIRED INTEGRATED CIRCUIT CHIPS

Patent #:	7833893	Issue Dt:	11/16/2010	Application #:	11775257	Filing Dt:	07/10/2007
Publication #:	US20090017616	Pub Dt:	01/15/2009
Title:	METHOD FOR FORMING CONDUCTIVE STRUCTURES

Patent #:	7895028	Issue Dt:	02/22/2011	Application #:	11775531	Filing Dt:	07/10/2007
Publication #:	US20090016129	Pub Dt:	01/15/2009
Title:	DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD

Patent #:	7521760	Issue Dt:	04/21/2009	Application #:	11775607	Filing Dt:	07/10/2007
Publication #:	US20070257314	Pub Dt:	11/08/2007
Title:	INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF

Patent #:	7622737	Issue Dt:	11/24/2009	Application #:	11776114	Filing Dt:	07/11/2007
Publication #:	US20090015285	Pub Dt:	01/15/2009
Title:	TEST STRUCTURES FOR ELECTRICALLY DETECTING BACK END OF THE LINE FAILURES AND METHODS OF MAKING AND USING THE SAME

Patent #:	7737501	Issue Dt:	06/15/2010	Application #:	11776118	Filing Dt:	07/11/2007
Publication #:	US20090014798	Pub Dt:	01/15/2009
Title:	FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF

Patent #:	7772582	Issue Dt:	08/10/2010	Application #:	11776295	Filing Dt:	07/11/2007
Publication #:	US20090014885	Pub Dt:	01/15/2009
Title:	FOUR-TERMINAL RECONFIGURABLE DEVICES

Patent #:	7476578	Issue Dt:	01/13/2009	Application #:	11776710	Filing Dt:	07/12/2007
Publication #:	US20090017584	Pub Dt:	01/15/2009
Title:	PROCESS FOR FINFET SPACER FORMATION

Patent #:	7855104	Issue Dt:	12/21/2010	Application #:	11776738	Filing Dt:	07/12/2007
Publication #:	US20070259490	Pub Dt:	11/08/2007
Title:	STRUCTURE AND METHOD FOR LATCHUP SUPPRESSION

Patent #:	7542599	Issue Dt:	06/02/2009	Application #:	11776769	Filing Dt:	07/12/2007
Publication #:	US20080019585	Pub Dt:	01/24/2008
Title:	REDUCING NUMBER OF RELATIVELY UNIMPORTANT SHAPES FROM A SET OF SHAPES

Patent #:	8020073	Issue Dt:	09/13/2011	Application #:	11776810	Filing Dt:	07/12/2007
Publication #:	US20090019341	Pub Dt:	01/15/2009
Title:	DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA

Patent #:	7548822	Issue Dt:	06/16/2009	Application #:	11777329	Filing Dt:	07/13/2007
Publication #:	US20090018787	Pub Dt:	01/15/2009
Title:	APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT

Patent #:	7882890	Issue Dt:	02/08/2011	Application #:	11777837	Filing Dt:	07/13/2007
Publication #:	US20090014155	Pub Dt:	01/15/2009
Title:	THERMALLY PUMPED LIQUID/GAS HEAT EXCHANGER FOR COOLING HEAT-GENERATING DEVICES

Patent #:	7911001	Issue Dt:	03/22/2011	Application #:	11778045	Filing Dt:	07/15/2007
Publication #:	US20090014808	Pub Dt:	01/15/2009
Title:	METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES

Patent #:	NONE	Issue Dt:		Application #:	11778155	Filing Dt:	07/16/2007
Publication #:	US20070278654	Pub Dt:	12/06/2007
Title:	Method of making an electronic package

Patent #:	7915670	Issue Dt:	03/29/2011	Application #:	11778185	Filing Dt:	07/16/2007
Publication #:	US20090020806	Pub Dt:	01/22/2009
Title:	ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD

Patent #:	7692254	Issue Dt:	04/06/2010	Application #:	11778217	Filing Dt:	07/16/2007
Publication #:	US20090020819	Pub Dt:	01/22/2009
Title:	FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE

Patent #:	8709887	Issue Dt:	04/29/2014	Application #:	11778238	Filing Dt:	07/16/2007
Publication #:	US20080014692	Pub Dt:	01/17/2008
Title:	METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC

Patent #:	7541247	Issue Dt:	06/02/2009	Application #:	11778414	Filing Dt:	07/16/2007
Publication #:	US20090020811	Pub Dt:	01/22/2009
Title:	GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION

Patent #:	NONE	Issue Dt:		Application #:	11778428	Filing Dt:	07/16/2007
Publication #:	US20090020813	Pub Dt:	01/22/2009
Title:	FORMATION OF LATERAL TRENCH FETS (FIELD EFFECT TRANSISTORS) USING STEPS OF LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) TECHNOLOGY

Patent #:	7709924	Issue Dt:	05/04/2010	Application #:	11778439	Filing Dt:	07/16/2007
Publication #:	US20090020818	Pub Dt:	01/22/2009
Title:	SEMICONDUCTOR DIODE STRUCTURES

Patent #:	7562281	Issue Dt:	07/14/2009	Application #:	11778641	Filing Dt:	07/16/2007
Publication #:	US20080016416	Pub Dt:	01/17/2008
Title:	AUTONOMIC PARITY EXCHANGE

Patent #:	7788569	Issue Dt:	08/31/2010	Application #:	11778644	Filing Dt:	07/16/2007
Publication #:	US20080126890	Pub Dt:	05/29/2008
Title:	AUTONOMIC PARITY EXCHANGE

Patent #:	7592817	Issue Dt:	09/22/2009	Application #:	11778679	Filing Dt:	07/17/2007
Publication #:	US20090021236	Pub Dt:	01/22/2009
Title:	ALIGNMENT CORRECTION SYSTEM AND METHOD OF USE

Patent #:	7811923	Issue Dt:	10/12/2010	Application #:	11778876	Filing Dt:	07/17/2007
Publication #:	US20090023284	Pub Dt:	01/22/2009
Title:	INTEGRATED WAFER PROCESSING SYSTEM FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS

Patent #:	NONE	Issue Dt:		Application #:	11778902	Filing Dt:	07/17/2007
Publication #:	US20090020856	Pub Dt:	01/22/2009
Title:	SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR SHIELDING A BOND PAD FROM ELECTRICAL NOISE

Patent #:	NONE	Issue Dt:		Application #:	11778926	Filing Dt:	07/17/2007
Publication #:	US20090024975	Pub Dt:	01/22/2009
Title:	SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING DESIGN HIERARCHY USING A SCROLL MECHANISM

Patent #:	8055925	Issue Dt:	11/08/2011	Application #:	11779432	Filing Dt:	07/18/2007
Publication #:	US20090024862	Pub Dt:	01/22/2009
Title:	STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS

Patent #:	7655967	Issue Dt:	02/02/2010	Application #:	11780022	Filing Dt:	07/19/2007
Publication #:	US20070257294	Pub Dt:	11/08/2007
Title:	DRAM (DYNAMIC RANDOM ACCESS MEMORY) CELLS

Patent #:	7493229	Issue Dt:	02/17/2009	Application #:	11780498	Filing Dt:	07/20/2007
Publication #:	US20090024349	Pub Dt:	01/22/2009
Title:	ADJUSTING VOLTAGE FOR A PHASE LOCKED LOOP BASED ON TEMPERATURE

Patent #:	7906390	Issue Dt:	03/15/2011	Application #:	11780519	Filing Dt:	07/20/2007
Publication #:	US20090020827	Pub Dt:	01/22/2009
Title:	THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME

Patent #:	8016482	Issue Dt:	09/13/2011	Application #:	11780530	Filing Dt:	07/20/2007
Publication #:	US20090022203	Pub Dt:	01/22/2009
Title:	METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT

Patent #:	7818696	Issue Dt:	10/19/2010	Application #:	11780712	Filing Dt:	07/20/2007
Publication #:	US20080027664	Pub Dt:	01/31/2008
Title:	ARCHITECTURAL LEVEL THROUGHPUT BASED POWER MODELING METHODOLOGY AND APPARATUS FOR PERVASIVELY CLOCK-GATED PROCESSOR CORES

Patent #:	7783998	Issue Dt:	08/24/2010	Application #:	11780919	Filing Dt:	07/20/2007
Publication #:	US20080209378	Pub Dt:	08/28/2008
Title:	METHOD AND SYSTEM FOR PROTOTYPING ELECTRONIC DEVICES WITH MULTI-CONFIGURATION CHIP CARRIERS

Patent #:	8036860	Issue Dt:	10/11/2011	Application #:	11781363	Filing Dt:	07/23/2007
Publication #:	US20090031305	Pub Dt:	01/29/2009
Title:	MODELING HOMOGENEOUS PARALLELISM

Patent #:	7399665	Issue Dt:	07/15/2008	Application #:	11781370	Filing Dt:	07/23/2007
Publication #:	US20070262345	Pub Dt:	11/15/2007
Title:	ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME

Patent #:	8037034	Issue Dt:	10/11/2011	Application #:	11781833	Filing Dt:	07/23/2007
Publication #:	US20070285958	Pub Dt:	12/13/2007
Title:	METHODS OF CREATING A DICTIONARY FOR DATA COMPRESSION

Patent #:	7525047	Issue Dt:	04/28/2009	Application #:	11781850	Filing Dt:	07/23/2007
Publication #:	US20070284133	Pub Dt:	12/13/2007
Title:	CABLE HAVING TRANSLUCENT, SEMI-TRANSPARENT OR TRANSPARENT ESD DISSIPATIVE LAYER AND/OR METALLIC LAYER

Patent #:	7645641	Issue Dt:	01/12/2010	Application #:	11781854	Filing Dt:	07/23/2007
Publication #:	US20090027860	Pub Dt:	01/29/2009
Title:	COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE

Patent #:	7760565	Issue Dt:	07/20/2010	Application #:	11781994	Filing Dt:	07/24/2007
Publication #:	US20090027065	Pub Dt:	01/29/2009
Title:	WORDLINE-TO-BITLINE OUTPUT TIMING RING OSCILLATOR CIRCUIT FOR EVALUATING STORAGE ARRAY PERFORMANCE

Patent #:	7751267	Issue Dt:	07/06/2010	Application #:	11782071	Filing Dt:	07/24/2007
Publication #:	US20090027983	Pub Dt:	01/29/2009
Title:	HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT

Patent #:	7859044	Issue Dt:	12/28/2010	Application #:	11782079	Filing Dt:	07/24/2007
Publication #:	US20090026523	Pub Dt:	01/29/2009
Title:	PARTIALLY GATED FINFET WITH GATE DIELECTRIC ON ONLY ONE SIDEWALL

Patent #:	7521345	Issue Dt:	04/21/2009	Application #:	11782351	Filing Dt:	07/24/2007
Publication #:	US20070262348	Pub Dt:	11/15/2007
Title:	HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE

Patent #:	NONE	Issue Dt:		Application #:	11782800	Filing Dt:	07/25/2007
Publication #:	US20090026492	Pub Dt:	01/29/2009
Title:	LATERAL JUNCTION BREAKDOWN TRIGGERED SILICON CONTROLLED RECTIFIER BASED ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Patent #:	7480170	Issue Dt:	01/20/2009	Application #:	11782808	Filing Dt:	07/25/2007
Publication #:	US20090027946	Pub Dt:	01/29/2009
Title:	METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO)

Patent #:	NONE	Issue Dt:		Application #:	11782910	Filing Dt:	07/25/2007
Publication #:	US20080048729	Pub Dt:	02/28/2008
Title:	Comparator Circuit and Method for Operating a Comparator Circuit

Patent #:	7906426	Issue Dt:	03/15/2011	Application #:	11788969	Filing Dt:	04/23/2007
Publication #:	US20080258308	Pub Dt:	10/23/2008
Title:	METHOD OF CONTROLLED LOW-K VIA ETCH FOR CU INTERCONNECTIONS

Patent #:	7550254	Issue Dt:	06/23/2009	Application #:	11789902	Filing Dt:	04/25/2007
Publication #:	US20070202440	Pub Dt:	08/30/2007
Title:	FLUORINATED SILSESQUIOXANE POLYMERS AND USE THEREOF IN LITHOGRAPHIC PHOTORESIST COMPOSITIONS

Patent #:	7387925	Issue Dt:	06/17/2008	Application #:	11799261	Filing Dt:	04/10/2007
Publication #:	US20070218621	Pub Dt:	09/20/2007
Title:	INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY

Patent #:	7865789	Issue Dt:	01/04/2011	Application #:	11819748	Filing Dt:	06/28/2007
Publication #:	US20080215945	Pub Dt:	09/04/2008
Title:	SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION

Patent #:	7760360	Issue Dt:	07/20/2010	Application #:	11820305	Filing Dt:	06/18/2007
Publication #:	US20080158564	Pub Dt:	07/03/2008
Title:	MONITORING A PHOTOLITHOGRAPHIC PROCESS USING A SCATTEROMETRY TARGET

Patent #:	7348252	Issue Dt:	03/25/2008	Application #:	11820713	Filing Dt:	06/19/2007
Publication #:	US20070249144	Pub Dt:	10/25/2007
Title:	METHOD OF FORMING SILICON-ON-INSULATOR WAFER HAVING REENTRANT SHAPE DIELECTRIC TRENCHES

Patent #:	7393624	Issue Dt:	07/01/2008	Application #:	11820862	Filing Dt:	06/20/2007
Publication #:	US20070259274	Pub Dt:	11/08/2007
Title:	NEGATIVE RESISTS BASED ON ACID-CATALYZED ELIMINATION OF POLAR MOLECULES

Patent #:	7512177	Issue Dt:	03/31/2009	Application #:	11828390	Filing Dt:	07/26/2007
Publication #:	US20080150599	Pub Dt:	06/26/2008
Title:	METHOD AND APPARATUS FOR GENERATING RANDOM JITTER

Patent #:	8791572	Issue Dt:	07/29/2014	Application #:	11828455	Filing Dt:	07/26/2007
Publication #:	US20090026623	Pub Dt:	01/29/2009
Title:	BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF

Patent #:	7854202	Issue Dt:	12/21/2010	Application #:	11828657	Filing Dt:	07/26/2007
Publication #:	US20090025598	Pub Dt:	01/29/2009
Title:	OVERHEAD TRANSPORT SERVICE VEHICLE AND METHOD

Patent #:	7477365	Issue Dt:	01/13/2009	Application #:	11828666	Filing Dt:	07/26/2007
Publication #:	US20080024781	Pub Dt:	01/31/2008
Title:	OPTICAL SPOT GEOMETRIC PARAMETER DETERMINATION USING CALIBRATION TARGETS

Patent #:	7761690	Issue Dt:	07/20/2010	Application #:	11828705	Filing Dt:	07/26/2007
Publication #:	US20090031111	Pub Dt:	01/29/2009
Title:	METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS

Patent #:	7720560	Issue Dt:	05/18/2010	Application #:	11828730	Filing Dt:	07/26/2007
Publication #:	US20090030543	Pub Dt:	01/29/2009
Title:	SEMICONDUCTOR MANUFACTURING PROCESS MONITORING

Patent #:	7930592	Issue Dt:	04/19/2011	Application #:	11829187	Filing Dt:	07/27/2007
Publication #:	US20080022149	Pub Dt:	01/24/2008
Title:	ENABLING MEMORY REDUNDANCY DURING TESTING

Patent #:	NONE	Issue Dt:		Application #:	11830069	Filing Dt:	07/30/2007
Publication #:	US20080028357	Pub Dt:	01/31/2008
Title:	METHOD OF AUTOMATIC GENERATION OF MICRO CLOCK GATING FOR REDUCING POWER CONSUMPTION

Patent #:	8173532	Issue Dt:	05/08/2012	Application #:	11830090	Filing Dt:	07/30/2007
Publication #:	US20090032886	Pub Dt:	02/05/2009
Title:	SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS

Patent #:	7496251	Issue Dt:	02/24/2009	Application #:	11830200	Filing Dt:	07/30/2007
Publication #:	US20080019633	Pub Dt:	01/24/2008
Title:	APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES

Patent #:	7928419	Issue Dt:	04/19/2011	Application #:	11830213	Filing Dt:	07/30/2007
Publication #:	US20080314739	Pub Dt:	12/25/2008
Title:	ELECTROLYTIC DEVICE BASED ON A SOLUTION-PROCESSED ELECTROLYTE

Patent #:	7459981	Issue Dt:	12/02/2008	Application #:	11830221	Filing Dt:	07/30/2007
Publication #:	US20080030280	Pub Dt:	02/07/2008
Title:	CIRCUITS AND METHODS FOR IMPLEMENTING TRANSFORMER-COUPLED AMPLIFIERS AT MILLIMETER WAVE FREQUENCIES

Patent #:	7777339	Issue Dt:	08/17/2010	Application #:	11830228	Filing Dt:	07/30/2007
Publication #:	US20090032929	Pub Dt:	02/05/2009
Title:	SEMICONDUCTOR CHIPS WITH REDUCED STRESS FROM UNDERFILL AT EDGE OF CHIP

Patent #:	8378469	Issue Dt:	02/19/2013	Application #:	11830239	Filing Dt:	07/30/2007
Publication #:	US20130016023	Pub Dt:	01/17/2013
Title:	APPARATUS AND METHODS FOR PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS FOR MILLIMETER WAVE APPLICATIONS

Patent #:	7785999	Issue Dt:	08/31/2010	Application #:	11830277	Filing Dt:	07/30/2007
Publication #:	US20080026551	Pub Dt:	01/31/2008
Title:	FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS

Patent #:	NONE	Issue Dt:		Application #:	11830312	Filing Dt:	07/30/2007
Publication #:	US20080023778	Pub Dt:	01/31/2008
Title:	Fully Silicided Gate Electrodes and Method of Making the Same

Patent #:	8110465	Issue Dt:	02/07/2012	Application #:	11830316	Filing Dt:	07/30/2007
Publication #:	US20090032889	Pub Dt:	02/05/2009
Title:	FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE

Patent #:	7619276	Issue Dt:	11/17/2009	Application #:	11830328	Filing Dt:	07/30/2007
Publication #:	US20090032859	Pub Dt:	02/05/2009
Title:	FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE

Patent #:	7751924	Issue Dt:	07/06/2010	Application #:	11830349	Filing Dt:	07/30/2007
Publication #:	US20090037016	Pub Dt:	02/05/2009
Title:	C4NP SERVO CONTROLLED SOLDER FILL HEAD

Patent #:	7521952	Issue Dt:	04/21/2009	Application #:	11830368	Filing Dt:	07/30/2007
Publication #:	US20090033351	Pub Dt:	02/05/2009
Title:	TEST STRUCTURE FOR ELECTROMIGRATION ANALYSIS AND RELATED METHOD

Patent #:	7776704	Issue Dt:	08/17/2010	Application #:	11830376	Filing Dt:	07/30/2007
Publication #:	US20070264787	Pub Dt:	11/15/2007
Title:	METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BICMOS TECHNOLOGY

Patent #:	7423303	Issue Dt:	09/09/2008	Application #:	11830464	Filing Dt:	07/30/2007
Publication #:	US20070262361	Pub Dt:	11/15/2007
Title:	STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS

Patent #:	7425483	Issue Dt:	09/16/2008	Application #:	11830489	Filing Dt:	07/30/2007
Publication #:	US20070269945	Pub Dt:	11/22/2007
Title:	STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES

Patent #:	7700446	Issue Dt:	04/20/2010	Application #:	11830868	Filing Dt:	07/31/2007
Publication #:	US20080176363	Pub Dt:	07/24/2008
Title:	VIRTUAL BODY-CONTACTED TRIGATE

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Title:	DOUBLE GATE ISOLATION

Patent #:	7646039	Issue Dt:	01/12/2010	Application #:	11830972	Filing Dt:	07/31/2007
Publication #:	US20090032845	Pub Dt:	02/05/2009
Title:	SOI FIELD EFFECT TRANSISTOR HAVING ASYMMETRIC JUNCTION LEAKAGE

Patent #:	7960036	Issue Dt:	06/14/2011	Application #:	11831005	Filing Dt:	07/31/2007
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Title:	SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME

Patent #:	7923202	Issue Dt:	04/12/2011	Application #:	11831099	Filing Dt:	07/31/2007
Publication #:	US20090035708	Pub Dt:	02/05/2009
Title:	LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER

Patent #:	8110496	Issue Dt:	02/07/2012	Application #:	11831137	Filing Dt:	07/31/2007
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Title:	METHOD FOR PERFORMING CHEMICAL SHRINK PROCESS OVER BARC (BOTTOM ANTI-REFLECTIVE COATING)

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Title:	ELECTRICAL FUSES AND RESISTORS HAVING SUBLITHOGRAPHIC DIMENSIONS

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Title:	RECESSING TRENCH TO TARGET DEPTH USING FEED FORWARD DATA

100

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Title:	SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS

Assignors

GLOBALFOUNDRIES U.S. 2 LLC

Exec Dt:

09/10/2015

GLOBALFOUNDRIES U.S. INC.

Exec Dt:

09/10/2015

Assignee

GLOBALFOUNDRIES INC.

PO BOX 309

UGLAND HOUSE

GRAND CAYMAN, CAYMAN ISLANDS KY1-1104

Correspondence name and address
	HESLIN ROTHENBERG FARLEY & MESITI P.C.
	5 COLUMBIA CIRCLE
	ALBANY, NY 12203

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