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Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 14854
Page 62 of 149
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149
1
Patent #:
NONE
Issue Dt:
Application #:
11871504
Filing Dt:
10/12/2007
Publication #:
US20080066860
Pub Dt:
03/20/2008
Title:
Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION
2
Patent #:
NONE
Issue Dt:
Application #:
11871533
Filing Dt:
10/12/2007
Publication #:
US20080067683
Pub Dt:
03/20/2008
Title:
TA-TAN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION
3
Patent #:
7704852
Issue Dt:
04/27/2010
Application #:
11871694
Filing Dt:
10/12/2007
Publication #:
US20080108204
Pub Dt:
05/08/2008
Title:
AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES
4
Patent #:
7943437
Issue Dt:
05/17/2011
Application #:
11871713
Filing Dt:
10/12/2007
Publication #:
US20080254609
Pub Dt:
10/16/2008
Title:
APPARATUS AND METHOD FOR ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE
5
Patent #:
7454302
Issue Dt:
11/18/2008
Application #:
11872060
Filing Dt:
10/15/2007
Publication #:
US20080033675
Pub Dt:
02/07/2008
Title:
METHOD OF INSPECTING INTEGRATED CIRCUITS DURING FABRICATION
6
Patent #:
7405990
Issue Dt:
07/29/2008
Application #:
11872085
Filing Dt:
10/15/2007
Publication #:
US20080037350
Pub Dt:
02/14/2008
Title:
METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
7
Patent #:
7397709
Issue Dt:
07/08/2008
Application #:
11872088
Filing Dt:
10/15/2007
Publication #:
US20080080274
Pub Dt:
04/03/2008
Title:
METHOD AND APPARATUS FOR IN-SYSTEM REDUNDANT ARRAY REPAIR ON INTEGRATED CIRCUITS
8
Patent #:
7700378
Issue Dt:
04/20/2010
Application #:
11872098
Filing Dt:
10/15/2007
Publication #:
US20080032428
Pub Dt:
02/07/2008
Title:
METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS
9
Patent #:
7480201
Issue Dt:
01/20/2009
Application #:
11872108
Filing Dt:
10/15/2007
Publication #:
US20080031076
Pub Dt:
02/07/2008
Title:
DAISY CHAINABLE MEMORY CHIP
10
Patent #:
8140919
Issue Dt:
03/20/2012
Application #:
11872168
Filing Dt:
10/15/2007
Publication #:
US20090100440
Pub Dt:
04/16/2009
Title:
DISPLAY OF DATA USED FOR SYSTEM PERFORMANCE ANALYSIS
11
Patent #:
NONE
Issue Dt:
Application #:
11872229
Filing Dt:
10/15/2007
Publication #:
US20080029889
Pub Dt:
02/07/2008
Title:
METHOD TO CREATE FLEXIBLE CONNECTIONS FOR INTEGRATED CIRCUITS
12
Patent #:
7609577
Issue Dt:
10/27/2009
Application #:
11872273
Filing Dt:
10/15/2007
Publication #:
US20080030260
Pub Dt:
02/07/2008
Title:
DESIGN STRUCTURE FOR IMPROVING SENSING MARGIN OF ELECTRICALLY PROGRAMMABLE FUSES
13
Patent #:
8299455
Issue Dt:
10/30/2012
Application #:
11872291
Filing Dt:
10/15/2007
Publication #:
US20120132966
Pub Dt:
05/31/2012
Title:
SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE
14
Patent #:
7615405
Issue Dt:
11/10/2009
Application #:
11872331
Filing Dt:
10/15/2007
Publication #:
US20080182362
Pub Dt:
07/31/2008
Title:
METHOD FOR PRECISION ASSEMBLY OF INTEGRATED CIRCUIT CHIP PACKAGES
15
Patent #:
NONE
Issue Dt:
Application #:
11872693
Filing Dt:
10/15/2007
Publication #:
US20080083697
Pub Dt:
04/10/2008
Title:
POROUS SILICON COMPOSITE STRUCTURE AS LARGE FILTRATION ARRAY
16
Patent #:
7886253
Issue Dt:
02/08/2011
Application #:
11872731
Filing Dt:
10/16/2007
Publication #:
US20090100398
Pub Dt:
04/16/2009
Title:
DESIGN STRUCTURE FOR PERFORMING ITERATIVE SYNTHESIS OF AN INTEGRATED CIRCUIT DESIGN TO ATTAIN POWER CLOSURE
17
Patent #:
7579897
Issue Dt:
08/25/2009
Application #:
11872743
Filing Dt:
10/16/2007
Publication #:
US20080157858
Pub Dt:
07/03/2008
Title:
DESIGN STRUCTURE FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES
18
Patent #:
7689950
Issue Dt:
03/30/2010
Application #:
11872763
Filing Dt:
10/16/2007
Publication #:
US20080169843
Pub Dt:
07/17/2008
Title:
IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE
19
Patent #:
7694262
Issue Dt:
04/06/2010
Application #:
11872787
Filing Dt:
10/16/2007
Publication #:
US20090100388
Pub Dt:
04/16/2009
Title:
DEEP TRENCH CAPACITOR AND METHOD OF MAKING SAME
20
Patent #:
7884475
Issue Dt:
02/08/2011
Application #:
11872796
Filing Dt:
10/16/2007
Publication #:
US20090096102
Pub Dt:
04/16/2009
Title:
CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER
21
Patent #:
7911803
Issue Dt:
03/22/2011
Application #:
11872870
Filing Dt:
10/16/2007
Publication #:
US20090095519
Pub Dt:
04/16/2009
Title:
CURRENT DISTRIBUTION STRUCTURE AND METHOD
22
Patent #:
7645621
Issue Dt:
01/12/2010
Application #:
11872900
Filing Dt:
10/16/2007
Publication #:
US20090097017
Pub Dt:
04/16/2009
Title:
OPTICAL INSPECTION METHODS
23
Patent #:
7861208
Issue Dt:
12/28/2010
Application #:
11872924
Filing Dt:
10/16/2007
Publication #:
US20090100399
Pub Dt:
04/16/2009
Title:
DESIGN STRUCTURE FOR PARTITIONED DUMMY FILL SHAPES FOR REDUCED MASK BIAS WITH ALTERNATING PHASE SHIFT MASKS
24
Patent #:
7745879
Issue Dt:
06/29/2010
Application #:
11872953
Filing Dt:
10/16/2007
Publication #:
US20090096026
Pub Dt:
04/16/2009
Title:
METHOD OF FABRICATING HIGH VOLTAGE FULLY DEPLETED SOI TRANSISTOR AND STRUCTURE THEREOF
25
Patent #:
7951666
Issue Dt:
05/31/2011
Application #:
11872970
Filing Dt:
10/16/2007
Publication #:
US20090095998
Pub Dt:
04/16/2009
Title:
DEEP TRENCH CAPACITOR AND METHOD
26
Patent #:
7733137
Issue Dt:
06/08/2010
Application #:
11873010
Filing Dt:
10/16/2007
Publication #:
US20090096497
Pub Dt:
04/16/2009
Title:
DESIGN STRUCTURES INCLUDING MULTIPLE REFERENCE FREQUENCY FRACTIONAL-N PLL (PHASE LOCKED LOOP)
27
Patent #:
7890202
Issue Dt:
02/15/2011
Application #:
11873092
Filing Dt:
10/16/2007
Publication #:
US20090099681
Pub Dt:
04/16/2009
Title:
METHOD FOR CREATING WAFER BATCHES IN AN AUTOMATED BATCH PROCESS TOOL
28
Patent #:
7785952
Issue Dt:
08/31/2010
Application #:
11873219
Filing Dt:
10/16/2007
Publication #:
US20090096034
Pub Dt:
04/16/2009
Title:
PARTIALLY AND FULLY SILICIDED GATE STACKS
29
Patent #:
7847409
Issue Dt:
12/07/2010
Application #:
11873300
Filing Dt:
10/16/2007
Publication #:
US20080036092
Pub Dt:
02/14/2008
Title:
SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER
30
Patent #:
7977247
Issue Dt:
07/12/2011
Application #:
11873316
Filing Dt:
10/16/2007
Publication #:
US20080213956
Pub Dt:
09/04/2008
Title:
FIELD EFFECT TRANSISTOR DEVICE INCLUDING AN ARRAY OF CHANNEL ELEMENTS
31
Patent #:
8855801
Issue Dt:
10/07/2014
Application #:
11873455
Filing Dt:
10/17/2007
Publication #:
US20090105863
Pub Dt:
04/23/2009
Title:
AUTOMATED INTEGRATION OF FEEDBACK FROM FIELD FAILURE TO ORDER CONFIGURATOR FOR DYNAMIC OPTIMIZATION OF MANUFACTURING TEST PROCESSES
32
Patent #:
7776646
Issue Dt:
08/17/2010
Application #:
11873486
Filing Dt:
10/17/2007
Publication #:
US20080087885
Pub Dt:
04/17/2008
Title:
ORGANIC FIELD-EFFECT TRANSISTOR AND METHOD OF MAKING SAME BASED ON POLYMERIZABLE SELF-ASSEMBLED MONOLAYERS
33
Patent #:
7814449
Issue Dt:
10/12/2010
Application #:
11873515
Filing Dt:
10/17/2007
Publication #:
US20090106707
Pub Dt:
04/23/2009
Title:
DESIGN STRUCTURE FOR MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT
34
Patent #:
7851865
Issue Dt:
12/14/2010
Application #:
11873521
Filing Dt:
10/17/2007
Publication #:
US20090101978
Pub Dt:
04/23/2009
Title:
FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
35
Patent #:
7609542
Issue Dt:
10/27/2009
Application #:
11873534
Filing Dt:
10/17/2007
Publication #:
US20090027945
Pub Dt:
01/29/2009
Title:
IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO)
36
Patent #:
7779375
Issue Dt:
08/17/2010
Application #:
11873543
Filing Dt:
10/17/2007
Publication #:
US20090102507
Pub Dt:
04/23/2009
Title:
DESIGN STRUCTURE FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS CLOCK DOMAINS DURING AT-SPEED TESTING
37
Patent #:
7904868
Issue Dt:
03/08/2011
Application #:
11873711
Filing Dt:
10/17/2007
Publication #:
US20090106726
Pub Dt:
04/23/2009
Title:
DESIGN STRUCTURES INCLUDING MEANS FOR LATERAL CURRENT CARRYING CAPABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
38
Patent #:
7767537
Issue Dt:
08/03/2010
Application #:
11873735
Filing Dt:
10/17/2007
Publication #:
US20090101957
Pub Dt:
04/23/2009
Title:
SIMPLIFIED METHOD OF FABRICATING ISOLATED AND MERGED TRENCH CAPACITORS
39
Patent #:
NONE
Issue Dt:
Application #:
11873754
Filing Dt:
10/17/2007
Publication #:
US20080320423
Pub Dt:
12/25/2008
Title:
SYSTEM AND METHOD TO PROTECT COMPUTING SYSTEMS
40
Patent #:
7795098
Issue Dt:
09/14/2010
Application #:
11873886
Filing Dt:
10/17/2007
Title:
ROTATED FIELD EFFECT TRANSISTORS AND METHOD OF MANUFACTURE
41
Patent #:
7895539
Issue Dt:
02/22/2011
Application #:
11873919
Filing Dt:
10/17/2007
Publication #:
US20090106709
Pub Dt:
04/23/2009
Title:
SYSTEM FOR IMPROVING A LOGIC CIRCUIT AND ASSOCIATED METHODS
42
Patent #:
7550369
Issue Dt:
06/23/2009
Application #:
11873928
Filing Dt:
10/17/2007
Publication #:
US20080057684
Pub Dt:
03/06/2008
Title:
METHOD FOR FABRICATING LOW-DEFECT-DENSITY CHANGED ORIENTATION SI
43
Patent #:
7439174
Issue Dt:
10/21/2008
Application #:
11873936
Filing Dt:
10/17/2007
Publication #:
US20080038917
Pub Dt:
02/14/2008
Title:
MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SICOH DIELECTRICS
44
Patent #:
8122297
Issue Dt:
02/21/2012
Application #:
11874232
Filing Dt:
10/18/2007
Publication #:
US20090106588
Pub Dt:
04/23/2009
Title:
METHOD AND APPARATUS FOR PARALLEL AND SERIAL DATA TRANSFER
45
Patent #:
7761839
Issue Dt:
07/20/2010
Application #:
11874274
Filing Dt:
10/18/2007
Publication #:
US20080059939
Pub Dt:
03/06/2008
Title:
PERFORMANCE IN MODEL-BASED OPC ENGINE UTILIZING EFFICIENT POLYGON PINNING METHOD
46
Patent #:
7840057
Issue Dt:
11/23/2010
Application #:
11874281
Filing Dt:
10/18/2007
Publication #:
US20080037858
Pub Dt:
02/14/2008
Title:
SIMULTANEOUS COMPUTATION OF MULTIPLE POINTS ON ONE OR MULTIPLE CUT LINES
47
Patent #:
8005560
Issue Dt:
08/23/2011
Application #:
11874518
Filing Dt:
10/18/2007
Publication #:
US20090105854
Pub Dt:
04/23/2009
Title:
METHOD OF OPTIMIZING QUEUE TIMES IN A PRODUCTION CYCLE
48
Patent #:
7955950
Issue Dt:
06/07/2011
Application #:
11874565
Filing Dt:
10/18/2007
Publication #:
US20090102026
Pub Dt:
04/23/2009
Title:
SEMICONDUCTOR-ON-INSULATOR SUBSTRATE WITH A DIFFUSION BARRIER
49
Patent #:
8389967
Issue Dt:
03/05/2013
Application #:
11874582
Filing Dt:
10/18/2007
Publication #:
US20090101882
Pub Dt:
04/23/2009
Title:
PROGRAMMABLE VIA DEVICES
50
Patent #:
7877717
Issue Dt:
01/25/2011
Application #:
11874620
Filing Dt:
10/18/2007
Publication #:
US20080040695
Pub Dt:
02/14/2008
Title:
ACCURATELY MODELING AN ASYNCHRONOUS INTERFACE USING EXPANDED LOGIC ELEMENTS
51
Patent #:
NONE
Issue Dt:
Application #:
11874753
Filing Dt:
10/18/2007
Publication #:
US20080042202
Pub Dt:
02/21/2008
Title:
QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS
52
Patent #:
8063483
Issue Dt:
11/22/2011
Application #:
11874861
Filing Dt:
10/18/2007
Publication #:
US20090102046
Pub Dt:
04/23/2009
Title:
ON-CHIP TEMPERATURE GRADIENT MINIMIZATION USING CARBON NANOTUBE COOLING STRUCTURES WITH VARIABLE COOLING CAPACITY
53
Patent #:
NONE
Issue Dt:
Application #:
11874957
Filing Dt:
10/19/2007
Publication #:
US20090101940
Pub Dt:
04/23/2009
Title:
DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES
54
Patent #:
7440348
Issue Dt:
10/21/2008
Application #:
11875004
Filing Dt:
10/19/2007
Publication #:
US20080037339
Pub Dt:
02/14/2008
Title:
MEMORY ARRAY HAVING A REDUNDANT MEMORY ELEMENT
55
Patent #:
7474575
Issue Dt:
01/06/2009
Application #:
11875009
Filing Dt:
10/19/2007
Publication #:
US20080037340
Pub Dt:
02/14/2008
Title:
APPARATUS FOR TESTING A MEMORY OF AN INTEGRATED CIRCUIT
56
Patent #:
7725780
Issue Dt:
05/25/2010
Application #:
11875011
Filing Dt:
10/19/2007
Publication #:
US20080037341
Pub Dt:
02/14/2008
Title:
ENABLING MEMORY REDUNDANCY DURING TESTING
57
Patent #:
7984408
Issue Dt:
07/19/2011
Application #:
11875013
Filing Dt:
10/19/2007
Publication #:
US20080034335
Pub Dt:
02/07/2008
Title:
DESIGN STRUCTURES INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING
58
Patent #:
7823107
Issue Dt:
10/26/2010
Application #:
11875032
Filing Dt:
10/19/2007
Publication #:
US20090106724
Pub Dt:
04/23/2009
Title:
TRANSITION BALANCING FOR NOISE REDUCTION/DI/DT REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN
59
Patent #:
NONE
Issue Dt:
Application #:
11875069
Filing Dt:
10/19/2007
Publication #:
US20080040696
Pub Dt:
02/14/2008
Title:
Design Structures Incorporating Shallow Trench Isolation Filled by Liquid Phase Deposition of SiO2
60
Patent #:
7977714
Issue Dt:
07/12/2011
Application #:
11875190
Filing Dt:
10/19/2007
Publication #:
US20090101941
Pub Dt:
04/23/2009
Title:
WRAPPED GATE JUNCTION FIELD EFFECT TRANSISTOR
61
Patent #:
7984409
Issue Dt:
07/19/2011
Application #:
11875193
Filing Dt:
10/19/2007
Publication #:
US20080120580
Pub Dt:
05/22/2008
Title:
DESIGN STRUCTURES INCORPORATING INTERCONNECT STRUCTURES WITH IMPROVED ELECTROMIGRATION RESISTANCE
62
Patent #:
8298435
Issue Dt:
10/30/2012
Application #:
11875227
Filing Dt:
10/19/2007
Publication #:
US20090101626
Pub Dt:
04/23/2009
Title:
SELECTIVE ETCHING BATH METHODS
63
Patent #:
7521748
Issue Dt:
04/21/2009
Application #:
11875503
Filing Dt:
10/19/2007
Publication #:
US20080035978
Pub Dt:
02/14/2008
Title:
METHOD TO ELIMINATE ARSENIC CONTAMINATION IN TRENCH CAPACITORS
64
Patent #:
7521346
Issue Dt:
04/21/2009
Application #:
11875524
Filing Dt:
10/19/2007
Publication #:
US20080038905
Pub Dt:
02/14/2008
Title:
METHOD OF FORMING HFSIN METAL FOR N-FET APPLICATIONS
65
Patent #:
NONE
Issue Dt:
Application #:
11875798
Filing Dt:
10/19/2007
Publication #:
US20090104566
Pub Dt:
04/23/2009
Title:
Process of multiple exposures with spin castable film
66
Patent #:
8126581
Issue Dt:
02/28/2012
Application #:
11876035
Filing Dt:
10/22/2007
Publication #:
US20080051924
Pub Dt:
02/28/2008
Title:
IMPROVING DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING THROUGH ANALYSIS OF DEFECT DATA
67
Patent #:
NONE
Issue Dt:
Application #:
11876076
Filing Dt:
10/22/2007
Publication #:
US20080256503
Pub Dt:
10/16/2008
Title:
POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY
68
Patent #:
NONE
Issue Dt:
Application #:
11876263
Filing Dt:
10/22/2007
Publication #:
US20090045839
Pub Dt:
02/19/2009
Title:
ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE
69
Patent #:
NONE
Issue Dt:
Application #:
11876400
Filing Dt:
10/22/2007
Publication #:
US20080052655
Pub Dt:
02/28/2008
Title:
Chip Having Timing Analysis of Paths Performed Within the Chip During the Design Process
70
Patent #:
NONE
Issue Dt:
Application #:
11876402
Filing Dt:
10/22/2007
Publication #:
US20090102016
Pub Dt:
04/23/2009
Title:
DESIGN STRUCTURE INCORPORATING VERTICAL PARALLEL PLATE CAPACITOR STRUCTURES
71
Patent #:
7492800
Issue Dt:
02/17/2009
Application #:
11876605
Filing Dt:
10/22/2007
Publication #:
US20080049799
Pub Dt:
02/28/2008
Title:
HIGH SPEED DATA CHANNEL INCLUDING A CMOS VCSEL DRIVER AND A HIGH PERFORMANCE PHOTODETECTOR AND CMOS PHOTORECEIVER
72
Patent #:
NONE
Issue Dt:
Application #:
11876871
Filing Dt:
10/23/2007
Publication #:
US20090102529
Pub Dt:
04/23/2009
Title:
SHIFTING INACTIVE CLOCK EDGE FOR NOISE REDUCTION
73
Patent #:
7915146
Issue Dt:
03/29/2011
Application #:
11877016
Filing Dt:
10/23/2007
Publication #:
US20090102019
Pub Dt:
04/23/2009
Title:
CONTROLLED DOPING OF SEMICONDUCTOR NANOWIRES
74
Patent #:
NONE
Issue Dt:
Application #:
11877048
Filing Dt:
10/23/2007
Publication #:
US20080036028
Pub Dt:
02/14/2008
Title:
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
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7739636
Issue Dt:
06/15/2010
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11877155
Filing Dt:
10/23/2007
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US20090106713
Pub Dt:
04/23/2009
Title:
DESIGN STRUCTURE INCORPORATING SEMICONDUCTOR DEVICE STRUCTURES THAT SHIELD A BOND PAD FROM ELECTRICAL NOISE
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NONE
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11877200
Filing Dt:
10/23/2007
Publication #:
US20080046850
Pub Dt:
02/21/2008
Title:
Integrated Circuit Implementing Improved Timing Driven Placements of Elements of a Circuit
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NONE
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11877305
Filing Dt:
10/23/2007
Publication #:
US20080132025
Pub Dt:
06/05/2008
Title:
ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF
78
Patent #:
7389015
Issue Dt:
06/17/2008
Application #:
11877859
Filing Dt:
10/24/2007
Title:
MECHANICALLY DECOUPLED OPTO-MECHANICAL CONNECTOR FOR FLEXIBLE OPTICAL WAVEGUIDES EMBEDDED AND/OR ATTACHED TO A PRINTED CIRCUIT BOARD
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7750406
Issue Dt:
07/06/2010
Application #:
11877871
Filing Dt:
10/24/2007
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Pub Dt:
10/23/2008
Title:
DESIGN STRUCTURE INCORPORATING A HYBRID SUBSTRATE
80
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7414436
Issue Dt:
08/19/2008
Application #:
11877898
Filing Dt:
10/24/2007
Title:
LIMITED SWITCH DYNAMIC LOGIC CELL BASED REGISTER
81
Patent #:
8008209
Issue Dt:
08/30/2011
Application #:
11877965
Filing Dt:
10/24/2007
Publication #:
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Pub Dt:
04/30/2009
Title:
THERMAL GRADIENT CONTROL OF HIGH ASPECT RATIO ETCHING AND DEPOSITION PROCESSES
82
Patent #:
7569447
Issue Dt:
08/04/2009
Application #:
11879065
Filing Dt:
07/16/2007
Publication #:
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Pub Dt:
11/08/2007
Title:
METHOD OF FORMING TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES
83
Patent #:
7790350
Issue Dt:
09/07/2010
Application #:
11882163
Filing Dt:
07/30/2007
Publication #:
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Pub Dt:
02/05/2009
Title:
METHOD AND MATERIALS FOR PATTERNING A NEUTRAL SURFACE
84
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7646469
Issue Dt:
01/12/2010
Application #:
11899085
Filing Dt:
09/04/2007
Publication #:
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Pub Dt:
12/27/2007
Title:
IMMERSION OPTICAL LITHOGRAPHY SYSTEM HAVING PROTECTIVE OPTICAL COATING
85
Patent #:
8358011
Issue Dt:
01/22/2013
Application #:
11899842
Filing Dt:
09/07/2007
Publication #:
US20130009315
Pub Dt:
01/10/2013
Title:
INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY
86
Patent #:
7709177
Issue Dt:
05/04/2010
Application #:
11906390
Filing Dt:
10/02/2007
Publication #:
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Pub Dt:
05/29/2008
Title:
MULTILAYERED RESIST SYSTEMS USING TUNED POLYMER FILMS AS UNDERLAYERS AND METHODS OF FABRICATION THEREOF
87
Patent #:
7736833
Issue Dt:
06/15/2010
Application #:
11906391
Filing Dt:
10/02/2007
Publication #:
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Pub Dt:
05/29/2008
Title:
MULTILAYERED RESIST SYSTEMS USING TUNED POLYMER FILMS AS UNDERLAYERS AND METHODS OF FABRICATION THEREOF
88
Patent #:
7683833
Issue Dt:
03/23/2010
Application #:
11923152
Filing Dt:
10/24/2007
Publication #:
US20080180324
Pub Dt:
07/31/2008
Title:
PHASE SHIFTING AND COMBINING ARCHITECTURE FOR PHASED ARRAYS
89
Patent #:
7854368
Issue Dt:
12/21/2010
Application #:
11923413
Filing Dt:
10/24/2007
Publication #:
US20080035362
Pub Dt:
02/14/2008
Title:
METHOD AND STRUCTURE FOR CONTROLLED IMPEDANCE WIRE BONDS USING CO-DISPENSING OF DIELECTRIC SPACERS
90
Patent #:
7996799
Issue Dt:
08/09/2011
Application #:
11923663
Filing Dt:
12/03/2007
Publication #:
US20090144676
Pub Dt:
06/04/2009
Title:
DESIGN VERIFICATION TECHNIQUE
91
Patent #:
8187930
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05/29/2012
Application #:
11923686
Filing Dt:
10/25/2007
Publication #:
US20080076212
Pub Dt:
03/27/2008
Title:
STRUCTURE AND LAYOUT OF A FET PRIME CELL
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7668682
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02/23/2010
Application #:
11923701
Filing Dt:
10/25/2007
Publication #:
US20090108863
Pub Dt:
04/30/2009
Title:
METHOD AND CIRCUIT FOR DETECTING AND COMPENSATING FOR A DEGRADATION OF A SEMICONDUCTOR DEVICE
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7915682
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03/29/2011
Application #:
11923717
Filing Dt:
10/25/2007
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Pub Dt:
02/28/2008
Title:
SEMICONDUCTOR FINFET STRUCTURES WITH ENCAPSULATED GATE ELECTRODES AND METHODS FOR FORMING SUCH SEMICONDUCTOR FINFET STRUCTURES
94
Patent #:
NONE
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11923784
Filing Dt:
10/25/2007
Publication #:
US20090113357
Pub Dt:
04/30/2009
Title:
MONITORING IONIZING RADIATION IN SILICON-ON INSULATOR INTEGRATED CIRCUITS
95
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7486586
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02/03/2009
Application #:
11923796
Filing Dt:
10/25/2007
Publication #:
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Pub Dt:
02/28/2008
Title:
VOLTAGE CONTROLLED STATIC RANDOM ACCESS MEMORY
96
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7784009
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08/24/2010
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11923833
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10/25/2007
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US20080052659
Pub Dt:
02/28/2008
Title:
ELECTRICALLY PROGRAMMABLE PI-SHAPED FUSE STRUCTURES AND DESIGN PROCESS THEREFORE
97
Patent #:
NONE
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11923856
Filing Dt:
10/25/2007
Publication #:
US20080050847
Pub Dt:
02/28/2008
Title:
SINGLE IC-CHIP DESIGN ON WAFER WITH AN EMBEDDED SENSOR UTILIZING RF CAPABILITIES TO ENABLE REAL-TIME DATA TRANSMISSION
98
Patent #:
9070791
Issue Dt:
06/30/2015
Application #:
11923864
Filing Dt:
10/25/2007
Publication #:
US20090108320
Pub Dt:
04/30/2009
Title:
TUNABLE CAPACITOR
99
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7474134
Issue Dt:
01/06/2009
Application #:
11923900
Filing Dt:
10/25/2007
Publication #:
US20080048745
Pub Dt:
02/28/2008
Title:
RADIATION HARDENED PROGRAMMABLE PHASE FREQUENCY DIVIDER
100
Patent #:
7548431
Issue Dt:
06/16/2009
Application #:
11923905
Filing Dt:
10/25/2007
Publication #:
US20080107374
Pub Dt:
05/08/2008
Title:
OPTICALLY CONNECTABLE CIRCUIT BOARD WITH OPTICAL COMPONENT(S) MOUNTED THEREON
Assignors
1
GLOBALFOUNDRIES U.S. 2 LLC
Exec Dt:
09/10/2015
2
GLOBALFOUNDRIES U.S. INC.
Exec Dt:
09/10/2015
Assignee
1
GLOBALFOUNDRIES INC.
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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