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Patent #:
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|
Issue Dt:
|
03/29/2011
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Application #:
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11958680
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Filing Dt:
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12/18/2007
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Publication #:
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|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
SYSTEM AND METHOD FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM
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Patent #:
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|
Issue Dt:
|
11/09/2010
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Application #:
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11959525
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Filing Dt:
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12/19/2007
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Publication #:
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|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR A SYSTEM FOR CONTROLLING ACCESS TO ADDRESSABLE INTEGRATED CIRCUITS
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|
Patent #:
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NONE
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Issue Dt:
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|
Application #:
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11959886
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Filing Dt:
|
12/19/2007
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Publication #:
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|
Pub Dt:
|
06/25/2009
| | | | |
Title:
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SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
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|
Patent #:
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|
Issue Dt:
|
04/16/2013
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Application #:
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11960030
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Filing Dt:
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12/19/2007
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Publication #:
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|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HEAT DISSIPATION STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
01/31/2012
|
Application #:
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11960051
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Filing Dt:
|
12/19/2007
|
Publication #:
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|
Pub Dt:
|
04/24/2008
| | | | |
Title:
|
SILICON-ON-INSULATOR BASED RADIATION DETECTION DEVICE AND METHOD
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|
Patent #:
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|
Issue Dt:
|
03/16/2010
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Application #:
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11960832
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Filing Dt:
|
12/20/2007
|
Publication #:
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|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
GLITCHLESS CLOCK MULTIPLEXER OPTIMIZED FOR SYNCHRONOUS AND ASYNCHRONOUS CLOCKS
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|
Patent #:
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|
Issue Dt:
|
12/28/2010
|
Application #:
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11960853
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Filing Dt:
|
12/20/2007
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Publication #:
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|
Pub Dt:
|
06/25/2009
| | | | |
Title:
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DESIGN STRUCTURES INCLUDING INTEGRATED CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT
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|
Patent #:
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|
Issue Dt:
|
05/17/2011
|
Application #:
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11960881
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Filing Dt:
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12/20/2007
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Publication #:
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Pub Dt:
|
06/25/2009
| | | | |
Title:
|
CMOS DEVICES WITH DIFFERENT METALS IN GATE ELECTRODES USING SPIN ON LOW-K MATERIAL AS HARD MASK
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Patent #:
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|
Issue Dt:
|
07/06/2010
|
Application #:
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11961076
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Filing Dt:
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12/20/2007
|
Publication #:
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Pub Dt:
|
06/25/2009
| | | | |
Title:
|
TRENCH METAL-INSULATOR METAL (MIM) CAPACITORS
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|
Patent #:
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|
Issue Dt:
|
03/22/2011
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Application #:
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11961308
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Filing Dt:
|
12/20/2007
|
Publication #:
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Pub Dt:
|
05/08/2008
| | | | |
Title:
|
STRUCTURE AND METHOD OF FABRICATING FINFET WITH BURIED CHANNEL
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|
Patent #:
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|
Issue Dt:
|
05/01/2012
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Application #:
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11961545
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Filing Dt:
|
12/20/2007
|
Publication #:
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|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
LOW JITTER COMMUNICATION SYSTEM
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|
|
Patent #:
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|
Issue Dt:
|
05/25/2010
|
Application #:
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11961593
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Filing Dt:
|
12/20/2007
|
Publication #:
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|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
PROGRAMMABLE-RESISTANCE MEMORY CELL
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11962271
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Filing Dt:
|
12/21/2007
|
Publication #:
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|
Pub Dt:
|
04/24/2008
| | | | |
Title:
|
ETCHING APPARATUS FOR SEMICONDUTOR FABRICATION
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|
|
Patent #:
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|
Issue Dt:
|
05/04/2010
|
Application #:
|
11962276
|
Filing Dt:
|
12/21/2007
|
Publication #:
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|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
DESIGN STRUCTURES AND SYSTEMS INVOLVING DIGITAL TO ANALOG CONVERTERS
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|
|
Patent #:
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|
Issue Dt:
|
12/28/2010
|
Application #:
|
11962718
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Filing Dt:
|
12/21/2007
|
Publication #:
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|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR RECOVERY OF MEMORY TRANSACTIONS
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|
|
Patent #:
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|
Issue Dt:
|
09/07/2010
|
Application #:
|
11962796
|
Filing Dt:
|
12/21/2007
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHOD FOR TUNING EPITAXIAL GROWTH BY INTERFACIAL DOPING AND STRUCTURE INCLUDING SAME
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|
|
Patent #:
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|
Issue Dt:
|
12/14/2010
|
Application #:
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11963267
|
Filing Dt:
|
12/21/2007
|
Publication #:
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|
Pub Dt:
|
06/10/2010
| | | | |
Title:
|
SYSTEM FOR BUILDING BINARY DECISION DIAGRAMS EFFICIENTLY IN A STRUCTURAL NETWORK REPRESENTATION OF A DIGITAL CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
11963325
|
Filing Dt:
|
12/21/2007
|
Publication #:
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|
Pub Dt:
|
06/03/2010
| | | | |
Title:
|
BUILDING BINARY DECISION DIAGRAMS EFFICIENTLY IN A STRUCTURAL NETWORK REPRESENTATION OF A DIGITAL CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11963794
|
Filing Dt:
|
12/22/2007
|
Publication #:
|
|
Pub Dt:
|
04/24/2008
| | | | |
Title:
|
RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11964337
|
Filing Dt:
|
12/26/2007
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
DESIGN METHODOLOGY FOR GUARD RING DESIGN RESISTANCE OPTIMIZATION FOR LATCHUP PREVENTION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11964757
|
Filing Dt:
|
12/27/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
AUTOMATED MIGRATION OF ANALOG AND MIXED-SIGNAL VLSI DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
11965015
|
Filing Dt:
|
12/27/2007
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
METHOD FOR PROVIDING DEFERRED MAINTENANCE ON STORAGE SUBSYSTEMS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11965186
|
Filing Dt:
|
12/27/2007
|
Publication #:
|
|
Pub Dt:
|
07/24/2008
| | | | |
Title:
|
Comparator Circuit and Method for Operating a Comparator Circuit
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2012
|
Application #:
|
11966043
|
Filing Dt:
|
12/28/2007
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
TECHNIQUES FOR SELECTING SPARES TO IMPLEMENT A DESIGN CHANGE IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
11966135
|
Filing Dt:
|
12/28/2007
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
SYSTEMATIC YIELD IN SEMICONDUCTOR MANUFACTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11966171
|
Filing Dt:
|
12/28/2007
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
Design Structure for a Clock System for a Plurality of Functional Blocks
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/2008
|
Application #:
|
11966438
|
Filing Dt:
|
12/28/2007
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
CLOCK DATA RECOVERING SYSTEM WITH EXTERNAL EARLY/LATE INPUT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
11966493
|
Filing Dt:
|
12/28/2007
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR ON-THE-FLY MINIMUM POWER STATE TRANSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11967459
|
Filing Dt:
|
12/31/2007
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11968396
|
Filing Dt:
|
01/02/2008
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
METHOD OF FABRICATING GATE ELECTRODE FOR GATE OF MOSFET AND STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11968444
|
Filing Dt:
|
01/02/2008
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11968479
|
Filing Dt:
|
01/02/2008
|
Publication #:
|
|
Pub Dt:
|
04/24/2008
| | | | |
Title:
|
CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11968669
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
REWORK PROCESS FOR REMOVING RESIDUAL UV ADHESIVE FROM C4 WAFER SURFACES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
11968686
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY OXIDATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11968695
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
VENTS WITH SIGNAL IMAGE FOR SIGNAL RETURN PATH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11968770
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
DATA PROCESSING IN DIGITAL SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
11968771
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHODS OF FORMING TUBULAR OBJECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
11968778
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHODS OF FORMING FEATURES IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
11968831
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
06/05/2008
| | | | |
Title:
|
CARBON DIOXIDE GETTERING FOR A CHIP MODULE ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11968872
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
SYSTEM FOR MEASURING AN EYEWIDTH OF A DATA SIGNAL IN AN ASYNCHRONOUS SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11968885
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
Title:
|
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH AN ELECTROPLATED METAL REPLACEMENT GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
11968898
|
Filing Dt:
|
01/03/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
SRAM DEVICE STRUCTURE INCLUDING SAME BAND GAP TRANSISTORS HAVING GATE STACKS WITH HIGH-K DIELECTRICS AND SAME WORK FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
11969256
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
CACHE INTERVENTION ON A SEPARATE DATA BUS WHEN ON-CHIP BUS HAS SEPARATE READ AND WRITE DATA BUSSES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11969279
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
11969339
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
FINFET TRANSISTOR AND CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11969448
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
HETERO-JUNCTION BIPOLAR TRANSISTOR (HBT) AND STRUCTURE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11969449
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
MEMORY INITIALIZATION TIME REDUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11969495
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD FOR QUANTIFYING THE MANUFACTORING COMPLEXITY OF ELECTRICAL DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
11969496
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
METHODS FOR FORMING IMPROVED SELF-ASSEMBLED PATTERNS OF BLOCK COPOLYMERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
11969502
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
HYBRID ORIENTATION SUBSTRATE COMPATIBLE DEEP TRENCH CAPACITOR EMBEDDED DRAM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11969525
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11969551
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD AND SYSTEM FOR REDUCING TURN AROUND TIME OF COMPLICATED ENGINEERING CHANGE ORDERS AND ASIC DESIGN REUTILIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/2011
|
Application #:
|
11969601
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
STORAGE REDUNDANT ARRAY OF INDEPENDENT DRIVES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11969618
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11969741
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
Method and System for Enhanced Verification Through Structural Target Decomposition
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11969761
|
Filing Dt:
|
01/04/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
Method and System for Enhanced Verification Through Structural Target Decomposition
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
11969981
|
Filing Dt:
|
01/07/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
SRAM DEVICE, AND SRAM DEVICE DESIGN STRUCTURE, WITH ADAPTABLE ACCESS TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
11969986
|
Filing Dt:
|
01/07/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
DRAM HAVING DEEP TRENCH CAPACITORS WITH LIGHTLY DOPED BURIED PLATES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
11969989
|
Filing Dt:
|
01/07/2008
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Publication #:
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|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
PROVIDING ISOLATION FOR WORDLINE PASSING OVER DEEP TRENCH CAPACITOR
|
|
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Patent #:
|
|
Issue Dt:
|
03/29/2011
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Application #:
|
11969991
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Filing Dt:
|
01/07/2008
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Publication #:
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Pub Dt:
|
06/05/2008
| | | | |
Title:
|
METHOD OF SWITCHING EXTERNAL MODELS IN AN AUTOMATED SYSTEM-ON-CHIP INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM
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Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11970100
|
Filing Dt:
|
01/07/2008
|
Publication #:
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Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD FOR FABRICATION OF SINGLE CRYSTAL DIODES FOR RESISTIVE MEMORIES
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|
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Patent #:
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|
Issue Dt:
|
10/12/2010
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Application #:
|
11970130
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Filing Dt:
|
01/07/2008
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Publication #:
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Pub Dt:
|
07/09/2009
| | | | |
Title:
|
VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT (FLI) IN MICROELECTRONICS PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11970149
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Filing Dt:
|
01/07/2008
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Publication #:
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Pub Dt:
|
07/09/2009
| | | | |
Title:
|
SIMULTANEOUS GRAIN MODULATION FOR BEOL APPLICATIONS
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|
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Patent #:
|
|
Issue Dt:
|
06/21/2011
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Application #:
|
11970165
|
Filing Dt:
|
01/07/2008
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Publication #:
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Pub Dt:
|
07/09/2009
| | | | |
Title:
|
STRUCTURE AND METHOD OF CREATING ENTIRELY SELF-ALIGNED METALLIC CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11970207
|
Filing Dt:
|
01/07/2008
|
Title:
|
PHASE CHANGE MEMORY CELL WITH ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
11970353
|
Filing Dt:
|
01/07/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
SILICON HEAT SPREADER MOUNTED IN-PLANE WITH A HEAT SOURCE AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
11970555
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
METHOD OF INTEGRATION OF A MIM CAPACITOR WITH A LOWER PLATE OF METAL GATE MATERIAL FORMED ON AN STI REGION OR A SILICIDE REGION FORMED IN OR ON THE SURFACE OF A DOPED WELL WITH A HIGH K DIELECTRIC MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11970579
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD AND STRUCTURE TO PROTECT FETS FROM PLASMA DAMAGE DURING FEOL PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11970592
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURES AND STRUCTURES THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11970665
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
STRUCTURE FOR SYMMETRICAL CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
11970693
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD AND STRUCTURE TO CONTROL THERMAL GRADIENTS IN SEMICONDUCTOR WAFERS DURING RAPID THERMAL PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11970731
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
IONIC, ORGANIC PHOTOACID GENERATORS FOR DUV, MUV AND OPTICAL LITHOGRAPHY BASED ON PERACEPTOR-SUBSTITUTED AROMATIC ANIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
11970750
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
ANTIFUSE STRUCTURE HAVING AN INTEGRATED HEATING ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
11970761
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
MULTIPLE EXPOSURE PHOTOLITHOGRAPHY METHODS AND PHOTORESIST COMPOSITIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
11970827
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
PHOTOACID GENERATORS FOR EXTREME ULTRAVIOLET LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
11971056
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
METHOD OF RECOVERING FROM SOFTWARE FAILURES USING REPLANNING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
11971179
|
Filing Dt:
|
01/08/2008
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
METHODS, SYSTEMS, AND MEDIA TO IMPROVE MANUFACTURABILITY OF SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
11971283
|
Filing Dt:
|
01/09/2008
|
Publication #:
|
|
Pub Dt:
|
05/01/2008
| | | | |
Title:
|
PARAMETRIC REDUCTION OF SEQUENTIAL DESIGN
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11971295
|
Filing Dt:
|
01/09/2008
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
Method and system for parametric reduction of sequential designs
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11971437
|
Filing Dt:
|
01/09/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
MOSFET HAVING A HIGH STRESS IN THE CHANNEL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2013
|
Application #:
|
11971470
|
Filing Dt:
|
01/09/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
11971761
|
Filing Dt:
|
01/09/2008
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
11971937
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11972118
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
REDUCING INTRODUCTION OF FOREIGN MATERIAL TO WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
11972125
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICE DEFECT TYPE DETERMINATION METHOD AND STRUCTURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11972129
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
Assembly Method For Reworkable Chip Stacking With Conductive Film
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
11972175
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
ADVANCED LOW K CAP FILM FORMATION PROCESS FOR NANO ELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
|
11972233
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
05/15/2008
| | | | |
Title:
|
SET/RESET LATCH WITH MINIMUM SINGLE EVENT UPSET
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
11972412
|
Filing Dt:
|
01/10/2008
|
Publication #:
|
|
Pub Dt:
|
05/29/2008
| | | | |
Title:
|
FIN-TYPE FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
11972678
|
Filing Dt:
|
01/11/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
TWO-LEVEL REPRESENTATIVE WORKLOAD PHASE DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
11972685
|
Filing Dt:
|
01/11/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
SEMICONDUCTOR AUTOMATION BUFFER STORAGE IDENTIFICATION SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
11972811
|
Filing Dt:
|
01/11/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
DOUBLE GATE DEPLETION MODE MOSFET
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
11972895
|
Filing Dt:
|
01/11/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
METHOD FOR PREVENTING BACKSIDE DEFECTS IN DIELECTRIC LAYERS FORMED ON SEMICONDUCTOR SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11972941
|
Filing Dt:
|
01/11/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
DEVICE STRUCTURES FOR A METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
11972964
|
Filing Dt:
|
01/11/2008
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11981882
|
Filing Dt:
|
10/31/2007
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR SRAM ACTIVE WRITE ASSIST FOR IMPROVED OPERATIONAL MARGINS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
11985956
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
STRUCTURE FOR ROBUST CABLE CONNECTIVITY TEST RECEIVER FOR HIGH-SPEED DATA RECEIVER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
11985963
|
Filing Dt:
|
11/19/2007
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR TRANSMITTER BANDWIDTH OPTIMIZATION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
11999627
|
Filing Dt:
|
12/06/2007
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
STRUCTURE FOR APPARATUS FOR REDUCED LOADING OF SIGNAL TRANSMISSION ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12002807
|
Filing Dt:
|
12/19/2007
|
Publication #:
|
|
Pub Dt:
|
05/08/2008
| | | | |
Title:
|
METHOD OF PROVIDING PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
|
|