|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12036664
|
Filing Dt:
|
02/25/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
TOOL ASSEMBLY FOR EXTRACTING AND INSTALLING DUAL IN-LINE MEMORY MODULE CARDLETS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12036697
|
Filing Dt:
|
02/25/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT INVOLVING ERROR THRESHOLDS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12036745
|
Filing Dt:
|
02/25/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROCESSING ERROR INFORMATION IN A SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2009
|
Application #:
|
12037067
|
Filing Dt:
|
02/25/2008
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
COMPLIANT THERMAL INTERFACE STRUCTURE UTILIZING SPRING ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12037113
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
METHOD FOR FABRICATING A FIELD EFFECT TRANSISTOR HAVING A DUAL THICKNESS GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
12037121
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH THIN GATE ELECTRODE AND METHOD OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12037158
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
GATE EFFECTIVE-WORKFUNCTION MODIFICATION FOR CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12037191
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CONNECTION STATE RECOVERY AFTER FAULT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12037421
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12037507
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
PRECURSORS FOR POROUS LOW-DIELECTRIC CONSTANT MATERIALS FOR USE IN ELECTRONIC DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12037725
|
Filing Dt:
|
02/26/2008
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
PROGRAMMABLE CAPACITORS AND METHODS OF USING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
12037956
|
Filing Dt:
|
02/27/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
DESIGN VERIFICATION USING DIRECTIVES HAVING LOCAL VARIABLES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12038195
|
Filing Dt:
|
02/27/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS AND METAL GATE ELECTRODES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12038320
|
Filing Dt:
|
02/27/2008
|
Publication #:
|
|
Pub Dt:
|
08/27/2009
| | | | |
Title:
|
SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12038589
|
Filing Dt:
|
02/27/2008
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
SYSTEM AND METHOD FOR SIMULATING A MULTIPROCESSOR SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12038818
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
MODEL-BASED HARDWARE EXERCISER, DEVICE, SYSTEM AND METHOD THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12038845
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
POWER GATING LOGIC CONES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
12038894
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12038985
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
SRAM CELL HAVING ASYMMETRIC PASS GATES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12039063
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
FIELD EFFECT DEVICE STRUCTURE INCLUDING SELF-ALIGNED SPACER SHAPED CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12039109
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
INTEGRATED CIRCUIT (IC) DESIGN METHOD, SYSTEM AND PROGRAM PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12039177
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
CMOS STRUCTURE INCLUDING NON-PLANAR HYBRID ORIENTATION SUBSTRATE WITH PLANAR GATE ELECTRODES AND METHOD FOR FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
12039309
|
Filing Dt:
|
02/28/2008
|
Publication #:
|
|
Pub Dt:
|
08/28/2008
| | | | |
Title:
|
SELF ORIENTING MICRO PLATES OF THERMALLY CONDUCTING MATERIAL AS COMPONENT IN THERMAL PASTE OR ADHESIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12039829
|
Filing Dt:
|
02/29/2008
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
USING ELECTRICALLY PROGRAMMABLE FUSES TO HIDE ARCHITECTURE, PREVENT REVERSE ENGINEERING, AND MAKE A DEVICE INOPERABLE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12039900
|
Filing Dt:
|
02/29/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
Photovoltaic Devices with Enhanced Efficiencies Using High-Aspect-Ratio Nanostructures
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12039953
|
Filing Dt:
|
02/29/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
Techniques for Enhancing Efficiency of Photovoltaic Devices Using High-Aspect-Ratio Nanostructures
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12039990
|
Filing Dt:
|
02/29/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SENSING OPERATION FOR RESISTIVE MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12040350
|
Filing Dt:
|
02/29/2008
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12040966
|
Filing Dt:
|
03/03/2008
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
ASYMMETRICAL MEMORY CELLS AND MEMORIES USING THE CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12041076
|
Filing Dt:
|
03/03/2008
|
Publication #:
|
|
Pub Dt:
|
09/03/2009
| | | | |
Title:
|
PRE-ALIGNMENT MARKING AND INSPECTION TO IMPROVE MASK SUBSTRATE DEFECT TOLERANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
12041265
|
Filing Dt:
|
03/03/2008
|
Title:
|
CIRCULAR GRATING RESONATOR STRUCTURE WITH INTEGRATED ELECTRO-OPTICAL MODULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2009
|
Application #:
|
12041388
|
Filing Dt:
|
03/03/2008
|
Publication #:
|
|
Pub Dt:
|
06/19/2008
| | | | |
Title:
|
METHODS AND APPARATUS FOR INLINE VARIABILITY MEASUREMENT OF INTEGRATED CIRCUIT COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
12041729
|
Filing Dt:
|
03/04/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
METHOD OF OPTIMIZING POWER USAGE OF AN INTERGRATED CIRCUIT DESIGN BY TUNING SELECTIVE VOLTAGE BINNING CUT POINT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12041878
|
Filing Dt:
|
03/04/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
SEMICONDUCTOR CHIP STACKING FOR REDUNDANCY AND YIELD IMPROVEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12041913
|
Filing Dt:
|
03/04/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
CONDITIONING INPUT BUFFER FOR CLOCK INTERPOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
12041967
|
Filing Dt:
|
03/04/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
12042375
|
Filing Dt:
|
03/05/2008
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
METHOD OF FORMING OPTICAL SENSOR THAT INCLUDES THREE PAIRS OF ELECTRODES FORMED AT DIFFERENT DEPTHS IN A SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2009
|
Application #:
|
12042709
|
Filing Dt:
|
03/05/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
GRADED SPIN-ON ORGANIC ANTIREFLECTIVE COATING FOR PHOTOLITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
12042873
|
Filing Dt:
|
03/05/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
ADVANCED MULTILAYER DIELECTRIC CAP WITH IMPROVED MECHANICAL AND ELECTRICAL PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
12042936
|
Filing Dt:
|
03/05/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
METHOD FOR FABRICATING AN ULTRA THIN SILICON ON INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
|
Application #:
|
12042984
|
Filing Dt:
|
03/05/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
METHOD AND SYSTEM FOR CACHE-BASED DROPPED WRITE PROTECTION IN DATA STORAGE SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
12043209
|
Filing Dt:
|
03/06/2008
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
VERIFICATION OF HIGHLY OPTIMIZED SYNCHRONOUS PIPELINES VIA RANDOM SIMULATION DRIVEN BY CRITICAL RESOURCE SCHEDULING SYSTEM AND PROGRAM PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12043455
|
Filing Dt:
|
03/06/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
METHOD OF MODELING AND EMPLOYING THE CMOS GATE SLEW AND OUTPUT LOAD DEPENDENT PIN CAPACITANCE DURING TIMING ANALYSIS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12043462
|
Filing Dt:
|
03/06/2008
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
ARRANGEMENT FOR OPTIMIZING SERVO CONTROLLER POWER IN TWO-DIMENSIONAL FLEXURE MEMS STORAGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12044032
|
Filing Dt:
|
03/07/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
PHOTOMASK IMAGE INSPECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12044145
|
Filing Dt:
|
03/07/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
RECESSING TRENCH TO TARGET DEPTH USING FEED FORWARD DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12044245
|
Filing Dt:
|
03/07/2008
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12044334
|
Filing Dt:
|
03/07/2008
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
ULTRALOW DIELECTRIC CONSTANT LAYER WITH CONTROLLED BIAXIAL STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12044579
|
Filing Dt:
|
03/07/2008
|
Publication #:
|
|
Pub Dt:
|
09/18/2008
| | | | |
Title:
|
TRENCH-EDGE-DEFECT-FREE RECRYSTALLIZATION BY EDGE-ANGLE-OPTIMIZED SOLID PHASE EPITAXY: METHOD AND APPLICATIONS TO HYBRID ORIENTATION SUBSTRATES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12045053
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
METHOD FOR BUILT IN SELF TEST FOR MEASURING TOTAL TIMING UNCERTAINTY IN A DIGITAL DATA PATH
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12045059
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
DUTY CYCLE MEASURMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12045186
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
OPTICAL TRANSCEIVER MODULE WITH OPTICAL WINDOWS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12045190
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
SOFT ERROR PROTECTION STRUCTURE EMPLOYING A DEEP TRENCH
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
12045290
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
04/02/2009
| | | | |
Title:
|
METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
12045343
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
REDUCING POWER CONSUMPTION IN SIGNAL DETECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12045374
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
REDUNDANT MICRO-LOOP STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT PHYSICAL DESIGN PROCESS AND METHOD OF FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/2010
|
Application #:
|
12045377
|
Filing Dt:
|
03/10/2008
|
Publication #:
|
|
Pub Dt:
|
01/15/2009
| | | | |
Title:
|
WAFER-SCALE PHASED ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12045744
|
Filing Dt:
|
03/11/2008
|
Publication #:
|
|
Pub Dt:
|
06/26/2008
| | | | |
Title:
|
DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12045899
|
Filing Dt:
|
03/11/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
CABLE FOR HIGH SPEED DATA COMMUNICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12045984
|
Filing Dt:
|
03/11/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
VARIABLE PERFORMANCE RANKING AND MODIFICATION IN DESIGN FOR MANUFACTURABILITY OF CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12046237
|
Filing Dt:
|
03/11/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
METHODS, APPARATUS, AND PROGRAM PRODUCTS TO OPTIMIZE SEMICONDUCTOR PRODUCT YIELD PREDICTION FOR PERFORMANCE AND LEAKAGE SCREENS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12046501
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12046508
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
07/17/2008
| | | | |
Title:
|
STRUCTURE FOR REDUNDANCY PROGRAMMING OF A MEMORY DEVICE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12046525
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
PROGRAMMABLE NON-VOLATILE RESISTANCE SWITCHING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12046560
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
CHARGE BREAKDOWN AVOIDANCE FOR MIM ELEMENTS IN SOI BASE TECHNOLOGY AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12046608
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
DESIGN STRUCTURE, FAILURE ANALYSIS TOOL AND METHOD OF DETERMINING WHITE BUMP LOCATION USING FAILURE ANALYSIS TOOL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12046643
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
RESISTOR AND DESIGN STRUCTURE HAVING SUBSTANTIALLY PARALLEL RESISTOR MATERIAL LENGTHS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12046647
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
RESISTOR AND DESIGN STRUCTURE HAVING RESISTOR MATERIAL LENGTH WITH SUB-LITHOGRAPHIC WIDTH
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12046750
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/26/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12046772
|
Filing Dt:
|
03/12/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
METHOD OF UNDERFILL AIR VENT FOR FLIPCHIP BGA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
12047355
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
FIELD EFFECT STRUCTURE INCLUDING CARBON ALLOYED CHANNEL REGION AND SOURCE/DRAIN REGION NOT CARBON ALLOYED
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2012
|
Application #:
|
12047376
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/15/2011
|
Application #:
|
12047379
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12047382
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
SYSTEM AND MEDIUM FOR PLACEMENT WHICH MAINTAIN OPTIMIZED TIMING BEHAVIOR, WHILE IMPROVING WIREABILITY POTENTIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12047435
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
PHOTOPATTERNABLE DIELECTRIC MATERIALS FOR BEOL APPLICATIONS AND METHODS FOR USE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
12047457
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
METHOD OF FORMING LOCAL COLLECTOR IMPLANT STRUCTURE FOR HETEROJUNCTION BIPOLAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
12047459
|
Filing Dt:
|
03/13/2008
|
Title:
|
PHASE CHANGE MATERIALS FOR APPLICATIONS THAT REQUIRE FAST SWITCHING AND HIGH ENDURANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
12047552
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
METHOD OF PRODUCING A LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12047566
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO) DESIGN METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12047603
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
A METHOD OF PRODUCING A LAND GRID ARRAY INTERPOSER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12047622
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
A METHOD OF PRODUCING A LAND GRID ARRAY INTERPOSER UTILIZING METAL-ON-ELASTOMER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
12047664
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
LAND GRID ARRAY INTERPOSER (LGA) UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES THAR IS CONSTITUTED OF A MOLDABLE DIELECTRIC ELASTOMETRIC MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12047694
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
01/07/2010
| | | | |
Title:
|
A METHOD OF OPERATIVELY COMBINING A PLURALITY OF COMPONENTS TO FORM A LAND GRIP ARRAY INTERPOSER (LGA) STRUCTURE UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12048183
|
Filing Dt:
|
03/13/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
PLUGIN HYBRID ELECTRIC VEHICLE WITH V2G OPTIMIZATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12048237
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
APPARATUS AND METHOD FOR IMPLEMENTING WRITE ASSIST FOR STATIC RANDOM ACCESS MEMORY ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12048263
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
12048461
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
ELETROSTATIC DISCHARGE (ESD) DEVICE AND METHOD OF FABRICATING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/2010
|
Application #:
|
12048620
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
12048635
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2009
|
Application #:
|
12048682
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
ELECTRONIC ASSEMBLY HAVING AN ELECTRICAL CONNECTOR ATTACHED TO A PRINTED CIRCUIT BOARD, AND A WIRE PASSING THROUGH A THROUGH-HOLE ON THE PRINTED CIRCUIT BOARD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
12049166
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
SYSTEM AND METHOD OF PROVIDING ERROR DETECTION AND CORRECTION CAPABILITY IN AN INTEGRATED CIRCUIT USING REDUNDANT LOGIC CELLS OF AN EMBEDDED FPGA
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12049258
|
Filing Dt:
|
03/14/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
PATTERNED SILICON-ON-INSULATOR LAYERS AND METHODS FOR FORMING THE SAME
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12049285
|
Filing Dt:
|
03/15/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
Using Performance Monitor to Optimize System Performance
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12049698
|
Filing Dt:
|
03/17/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
TUNGSTEN LINER FOR ALUMINUM-BASED ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12049780
|
Filing Dt:
|
03/17/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
METHOD FOR FABRICATING SELF-ALIGNED NANOSTRUCTURE USING SELF-ASSEMBLY BLOCK COPOLYMERS, AND STRUCTURES FABRICATED THEREFROM
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12049808
|
Filing Dt:
|
03/17/2008
|
Publication #:
|
|
Pub Dt:
|
07/03/2008
| | | | |
Title:
|
METHOD, SYSTEM AND PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING ARBITRARY MAPPING FUNCTIONS FOR CONFIGURATION CONSTRUCTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
12050425
|
Filing Dt:
|
03/18/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
PROVIDING A DYNAMIC SAMPLING PLAN FOR INTEGRATED METROLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
12050589
|
Filing Dt:
|
03/18/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
PHOTORESISTS FOR VISIBLE LIGHT IMAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12050596
|
Filing Dt:
|
03/18/2008
|
Publication #:
|
|
Pub Dt:
|
07/10/2008
| | | | |
Title:
|
METHOD FOR REDUCING OVERLAP CAPACITANCE IN FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12050990
|
Filing Dt:
|
03/19/2008
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR SEMICONDUCTOR ON-CHIP REPAIR SCHEME FOR NEGATIVE BIAS TEMPERATURE INSTABILITY
|
|