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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:036779/0001   Pages: 985
Recorded: 10/05/2015
Attorney Dkt #:3718.266
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
NONE
Issue Dt:
Application #:
12062186
Filing Dt:
04/03/2008
Publication #:
Pub Dt:
08/07/2008
Title:
Techniques for Patterning Features in Semiconductor Devices
2
Patent #:
Issue Dt:
04/05/2011
Application #:
12062262
Filing Dt:
04/03/2008
Publication #:
Pub Dt:
10/08/2009
Title:
METHOD AND STRUCTURE FOR BALLAST RESISTOR
3
Patent #:
Issue Dt:
11/09/2010
Application #:
12062270
Filing Dt:
04/03/2008
Publication #:
Pub Dt:
07/31/2008
Title:
PROCESS FOR SOFTWARE SUPPORT RESOURCE ALLOCATION BASED ON ANALYSIS OF CATEGORIZED FIELD PROBLEMS
4
Patent #:
Issue Dt:
10/12/2010
Application #:
12062310
Filing Dt:
04/03/2008
Publication #:
Pub Dt:
08/07/2008
Title:
TRENCH CAPACITOR
5
Patent #:
Issue Dt:
08/30/2011
Application #:
12062586
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
08/07/2008
Title:
TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
6
Patent #:
Issue Dt:
02/09/2010
Application #:
12062592
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
09/11/2008
Title:
AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS
7
Patent #:
Issue Dt:
02/02/2010
Application #:
12062612
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
11/27/2008
Title:
METAL SPACER IN SINGLE AND DUAL DAMASCENE PROCESSING
8
Patent #:
Issue Dt:
05/22/2012
Application #:
12062618
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
08/07/2008
Title:
DEVICE COMPONENT FORMING METHOD WITH A TRIM STEP PRIOR TO SIDEWALL IMAGE TRANSFER (SIT) PROCESSING
9
Patent #:
Issue Dt:
10/05/2010
Application #:
12062665
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
08/07/2008
Title:
VERSATILE SI-BASED PACKAGING WITH INTEGRATED PASSIVE COMPONENTS FOR MMWAVE APPLICATIONS
10
Patent #:
Issue Dt:
04/06/2010
Application #:
12062749
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
11/20/2008
Title:
LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS
11
Patent #:
Issue Dt:
12/28/2010
Application #:
12062972
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
07/31/2008
Title:
LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS
12
Patent #:
Issue Dt:
08/31/2010
Application #:
12077973
Filing Dt:
03/24/2008
Publication #:
Pub Dt:
07/24/2008
Title:
METHOD OF MAKING DOUBLE-GATED SELF-ALIGNED FINFET HAVING GATES OF DIFFERENT LENGTHS
13
Patent #:
Issue Dt:
06/17/2014
Application #:
12080266
Filing Dt:
04/01/2008
Publication #:
Pub Dt:
12/23/2010
Title:
SILICON BASED OPTICAL VIAS
14
Patent #:
Issue Dt:
05/05/2009
Application #:
12098038
Filing Dt:
04/04/2008
Title:
SYSTEM FOR EXPANDING A WINDOW OF VALID DATA
15
Patent #:
Issue Dt:
09/11/2012
Application #:
12098172
Filing Dt:
04/04/2008
Publication #:
Pub Dt:
08/07/2008
Title:
METHOD AND APPARATUS FOR GENERATING PROFILE OF SOLUTIONS TRADING OFF NUMBER OF ACTIVITIES UTILIZED AND OBJECTIVE VALUE FOR BILINEAR INTEGER OPTIMIZATION MODELS
16
Patent #:
NONE
Issue Dt:
Application #:
12098479
Filing Dt:
04/07/2008
Publication #:
Pub Dt:
08/07/2008
Title:
METHOD AND STRUCTURE FOR INTEGRATING MIM CAPACITORS WITHIN DUAL DAMASCENE PROCESSING TECHNIQUES
17
Patent #:
NONE
Issue Dt:
Application #:
12098715
Filing Dt:
04/07/2008
Publication #:
Pub Dt:
09/04/2008
Title:
DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS
18
Patent #:
Issue Dt:
05/24/2011
Application #:
12098895
Filing Dt:
04/07/2008
Publication #:
Pub Dt:
10/16/2008
Title:
ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTI-LAYER HARDMASK SCHEME
19
Patent #:
NONE
Issue Dt:
Application #:
12099016
Filing Dt:
04/07/2008
Publication #:
Pub Dt:
10/16/2008
Title:
MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
20
Patent #:
Issue Dt:
12/30/2014
Application #:
12099175
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
10/08/2009
Title:
FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE
21
Patent #:
Issue Dt:
02/15/2011
Application #:
12099211
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
08/07/2008
Title:
SUBSTRATE BACKGATE FOR TRIGATE FET
22
Patent #:
Issue Dt:
06/23/2009
Application #:
12099304
Filing Dt:
04/08/2008
Title:
METHOD FOR DETECTING ALPHA PARTICLES IN SOI TECHNOLOGY
23
Patent #:
Issue Dt:
01/25/2011
Application #:
12099307
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
10/08/2009
Title:
DESIGN STRUCTURE FOR ALPHA PARTICLE SENSOR IN SOI TECHNOLOGY AND STRUCTURE THEREOF
24
Patent #:
Issue Dt:
09/28/2010
Application #:
12099316
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
10/08/2009
Title:
DEVICE STRUCTURES WITH A HYPER-ABRUPT P-N JUNCTION, METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT
25
Patent #:
Issue Dt:
06/08/2010
Application #:
12099339
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
10/08/2009
Title:
PIXEL SENSOR WITH REDUCED IMAGE LAG
26
Patent #:
Issue Dt:
12/21/2010
Application #:
12099381
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
09/11/2008
Title:
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
27
Patent #:
Issue Dt:
08/17/2010
Application #:
12099412
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
09/18/2008
Title:
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
28
Patent #:
Issue Dt:
06/21/2011
Application #:
12099423
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
08/07/2008
Title:
DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL
29
Patent #:
Issue Dt:
07/27/2010
Application #:
12099437
Filing Dt:
04/08/2008
Publication #:
Pub Dt:
09/25/2008
Title:
ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF
30
Patent #:
Issue Dt:
10/05/2010
Application #:
12099879
Filing Dt:
04/09/2008
Publication #:
Pub Dt:
10/15/2009
Title:
SOI TRANSISTOR WITH MERGED LATERAL BIPOLAR TRANSISTOR
31
Patent #:
NONE
Issue Dt:
Application #:
12099904
Filing Dt:
04/09/2008
Publication #:
Pub Dt:
10/15/2009
Title:
METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER
32
Patent #:
Issue Dt:
12/08/2009
Application #:
12099996
Filing Dt:
04/09/2008
Publication #:
Pub Dt:
10/15/2009
Title:
STRUCTURE AND METHOD FOR HYBRID TUNGSTEN COPPER METAL CONTACT
33
Patent #:
NONE
Issue Dt:
Application #:
12099998
Filing Dt:
04/09/2008
Publication #:
Pub Dt:
12/04/2008
Title:
Layout Generator for Routing and Designing an LSI
34
Patent #:
Issue Dt:
02/01/2011
Application #:
12100441
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
10/15/2009
Title:
2-T SRAM CELL STRUCTURE AND METHOD
35
Patent #:
Issue Dt:
12/15/2009
Application #:
12100480
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
07/31/2008
Title:
SOCKET AND METHOD FOR COMPENSATING FOR DIFFERING COEFFICIENTS OF THERMAL EXPANSION
36
Patent #:
Issue Dt:
06/28/2011
Application #:
12100481
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
10/15/2009
Title:
ASSESSING RESOURCES REQUIRED TO COMPLETE A VLSI DESIGN
37
Patent #:
Issue Dt:
10/08/2013
Application #:
12100592
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
10/02/2008
Title:
DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR
38
Patent #:
Issue Dt:
02/23/2010
Application #:
12100615
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD AND APPARATUS FOR IMPROVING INTEGRATED CIRCUIT DEVICE PERFORMANCE USING HYBRID CRYSTAL ORIENTATIONS
39
Patent #:
Issue Dt:
03/23/2010
Application #:
12100644
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
08/21/2008
Title:
PRE-EPITAXIAL DISPOSABLE SPACER INTEGRATION SCHEME WITH VERY LOW TEMPERATURE SELECTIVE EPITAXY FOR ENHANCED DEVICE PERFORMANCE
40
Patent #:
Issue Dt:
11/16/2010
Application #:
12100708
Filing Dt:
04/10/2008
Publication #:
Pub Dt:
10/15/2009
Title:
METAL GATE COMPATIBLE FLASH MEMORY GATE STACK
41
Patent #:
Issue Dt:
10/25/2011
Application #:
12101329
Filing Dt:
04/11/2008
Publication #:
Pub Dt:
10/15/2009
Title:
METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS
42
Patent #:
Issue Dt:
10/01/2013
Application #:
12101441
Filing Dt:
04/11/2008
Publication #:
Pub Dt:
10/15/2009
Title:
CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
43
Patent #:
Issue Dt:
10/14/2014
Application #:
12101449
Filing Dt:
04/11/2008
Publication #:
Pub Dt:
10/15/2009
Title:
CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
44
Patent #:
Issue Dt:
04/05/2011
Application #:
12101455
Filing Dt:
04/11/2008
Publication #:
Pub Dt:
10/15/2009
Title:
CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
45
Patent #:
Issue Dt:
02/09/2010
Application #:
12101599
Filing Dt:
04/11/2008
Publication #:
Pub Dt:
08/14/2008
Title:
CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
46
Patent #:
Issue Dt:
07/10/2012
Application #:
12102032
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
10/15/2009
Title:
SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH A BODY-TO-SUBSTRATE CONNECTION FOR ENHANCED ELECTROSTATIC DISCHARGE PROTECTION, AND DESIGN STRUCTURES FOR SUCH SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES
47
Patent #:
Issue Dt:
12/28/2010
Application #:
12102035
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
10/15/2009
Title:
FINAL VIA STRUCTURES FOR BOND PAD-SOLDER BALL INTERCONNECTIONS
48
Patent #:
Issue Dt:
04/13/2010
Application #:
12102051
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
10/15/2009
Title:
RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S) IN RING AND/OR OFFSET CAVITIES
49
Patent #:
Issue Dt:
10/04/2011
Application #:
12102097
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
02/04/2010
Title:
HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS
50
Patent #:
Issue Dt:
08/10/2010
Application #:
12102116
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
09/04/2008
Title:
SPECIFYING A CONFIGURATION FOR A DIGITAL SYSTEM UTILIZING DIAL BIASING WEIGHTS
51
Patent #:
NONE
Issue Dt:
Application #:
12102333
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
10/15/2009
Title:
FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME
52
Patent #:
Issue Dt:
12/14/2010
Application #:
12102510
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
08/14/2008
Title:
PERFORMING TEMPORAL CHECKING
53
Patent #:
NONE
Issue Dt:
Application #:
12102525
Filing Dt:
04/14/2008
Publication #:
Pub Dt:
08/14/2008
Title:
PERFORMING TEMPORAL CHECKING
54
Patent #:
Issue Dt:
10/26/2010
Application #:
12103000
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
TRENCH WIDENING WITHOUT MERGING
55
Patent #:
Issue Dt:
08/09/2011
Application #:
12103038
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
56
Patent #:
Issue Dt:
05/22/2012
Application #:
12103110
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE
57
Patent #:
Issue Dt:
06/09/2009
Application #:
12103129
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD FOR DIVIDING A HIGH-FREQUENCY SIGNAL
58
Patent #:
Issue Dt:
07/20/2010
Application #:
12103212
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHODS FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS
59
Patent #:
Issue Dt:
11/23/2010
Application #:
12103256
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
10/15/2009
Title:
PARTIALLY UNDERFILLED SOLDER GRID ARRAYS
60
Patent #:
Issue Dt:
06/28/2011
Application #:
12103301
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
10/15/2009
Title:
COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS
61
Patent #:
Issue Dt:
05/31/2011
Application #:
12103538
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
SYSTEM AND PROGRAM PRODUCT FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
62
Patent #:
Issue Dt:
07/12/2011
Application #:
12103548
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
63
Patent #:
NONE
Issue Dt:
Application #:
12103804
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
08/14/2008
Title:
SYSTEM AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS
64
Patent #:
Issue Dt:
11/10/2009
Application #:
12104103
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
09/11/2008
Title:
METHOD AND DEVICE INCLUDING REWORKABLE ALPHA PARTICLE BARRIER AND CORROSION BARRIER
65
Patent #:
Issue Dt:
08/10/2010
Application #:
12104132
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
10/22/2009
Title:
REGULATED VOLTAGE BOOST CHARGE PUMP FOR AN INTEGRATED CIRCUIT DEVICE
66
Patent #:
Issue Dt:
08/09/2011
Application #:
12104461
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD
67
Patent #:
Issue Dt:
06/21/2011
Application #:
12104475
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS
68
Patent #:
Issue Dt:
07/19/2011
Application #:
12104513
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS
69
Patent #:
Issue Dt:
04/14/2015
Application #:
12104526
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
09/11/2008
Title:
METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL
70
Patent #:
Issue Dt:
02/23/2010
Application #:
12104570
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
08/21/2008
Title:
SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK
71
Patent #:
Issue Dt:
02/14/2012
Application #:
12104643
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE
72
Patent #:
Issue Dt:
05/17/2011
Application #:
12104683
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S)
73
Patent #:
NONE
Issue Dt:
Application #:
12104852
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD FOR OPTIMIZATION OF LOGIC CIRCUITS FOR ROUTABILITY IMPROVEMENT
74
Patent #:
Issue Dt:
06/08/2010
Application #:
12105034
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
09/11/2008
Title:
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE
75
Patent #:
Issue Dt:
08/31/2010
Application #:
12105037
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
09/11/2008
Title:
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE
76
Patent #:
Issue Dt:
07/19/2011
Application #:
12105217
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION INVOLVING DATA STORAGE DEVICES
77
Patent #:
Issue Dt:
09/20/2011
Application #:
12105311
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
10/22/2009
Title:
TEST METHOD FOR DETERMINING RETICLE TRANSMISSION STABILITY
78
Patent #:
Issue Dt:
05/24/2011
Application #:
12105349
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
10/22/2009
Title:
SYSTEM AND METHODS TO EXTEND THE SERVICE LIFE OF PORTABLE DEVICES
79
Patent #:
Issue Dt:
07/19/2011
Application #:
12105366
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
PROGRAMMING OF LASER FUSE
80
Patent #:
Issue Dt:
09/07/2010
Application #:
12105395
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS
81
Patent #:
NONE
Issue Dt:
Application #:
12105430
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
09/04/2008
Title:
ASYNCHRONOUS HIDDEN MARKOV MODEL METHOD AND SYSTEM
82
Patent #:
Issue Dt:
06/21/2011
Application #:
12105449
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
INTEGRATED CIRCUIT DESIGN STRUCTURE FOR AN ASYCHRONOUS DATA INTERFACE
83
Patent #:
Issue Dt:
04/17/2012
Application #:
12105494
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
84
Patent #:
Issue Dt:
11/23/2010
Application #:
12105600
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
85
Patent #:
Issue Dt:
05/24/2011
Application #:
12105622
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
86
Patent #:
NONE
Issue Dt:
Application #:
12105883
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
04/09/2009
Title:
DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM
87
Patent #:
Issue Dt:
07/13/2010
Application #:
12106018
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/07/2008
Title:
GENERATION OF HARDWARE THERMAL PROFILES FOR A SET OF PROCESSORS
88
Patent #:
Issue Dt:
09/27/2011
Application #:
12106053
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
11/27/2008
Title:
PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE HAVING CLONE LATCH SUPPORT
89
Patent #:
Issue Dt:
02/08/2011
Application #:
12106361
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
08/07/2008
Title:
HDL DESIGN STRUCTURE FOR INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT DESIGN
90
Patent #:
NONE
Issue Dt:
Application #:
12106373
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
09/11/2008
Title:
Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure
91
Patent #:
NONE
Issue Dt:
Application #:
12106396
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
08/21/2008
Title:
STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES
92
Patent #:
Issue Dt:
05/05/2009
Application #:
12106416
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/09/2008
Title:
PROGRAM PRODUCT FOR DEFINING AND RECORDING MINIMUM AND MAXIMUM EVENT COUNTS OF A SIMULATION UTILIZING A HIGH LEVEL LANGUAGE
93
Patent #:
Issue Dt:
11/23/2010
Application #:
12106462
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
12/31/2009
Title:
A METHOD OF OPERATIVELY COMBINING A PLURALITY OF COMPONENTS TO FORM A LAND GRIP ARRAY INTERPOSER (LGA) STRUCTURE UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
94
Patent #:
Issue Dt:
08/09/2011
Application #:
12106476
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/22/2009
Title:
FINFETS SINGLE-SIDED IMPLANT FORMATION
95
Patent #:
Issue Dt:
02/21/2012
Application #:
12106531
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
08/14/2008
Title:
INTEGRATED CIRCUIT TRANSFORMER DEVICES FOR ON-CHIP MILLIMETER-WAVE APPLICATIONS
96
Patent #:
Issue Dt:
02/01/2011
Application #:
12106539
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
07/30/2009
Title:
CROSS POINT SWITCH USING PHASE CHANGE MATERIAL
97
Patent #:
Issue Dt:
03/08/2011
Application #:
12106557
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/22/2009
Title:
METAL-GATE THERMOCOUPLE
98
Patent #:
Issue Dt:
06/16/2015
Application #:
12106586
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/23/2008
Title:
Methods and structures for protecting one area while processing another area on a chip
99
Patent #:
Issue Dt:
02/07/2012
Application #:
12106983
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
09/11/2008
Title:
ELECTRONIC COMPONENT AND TAPE HEAD HAVING A CLOSURE
100
Patent #:
NONE
Issue Dt:
Application #:
12107064
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/22/2009
Title:
ORGANIC SUBSTRATE WITH ASYMMETRIC THICKNESS FOR WARP MITIGATION
Assignors
1
Exec Dt:
09/10/2015
2
Exec Dt:
09/10/2015
Assignee
1
PO BOX 309
UGLAND HOUSE
GRAND CAYMAN, CAYMAN ISLANDS KY1-1104
Correspondence name and address
HESLIN ROTHENBERG FARLEY & MESITI P.C.
5 COLUMBIA CIRCLE
ALBANY, NY 12203

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