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NONE
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12062186
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04/03/2008
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08/07/2008
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Techniques for Patterning Features in Semiconductor Devices
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04/05/2011
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12062262
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04/03/2008
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10/08/2009
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11/09/2010
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12062270
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04/03/2008
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07/31/2008
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10/12/2010
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12062310
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04/03/2008
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08/07/2008
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TRENCH CAPACITOR
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08/30/2011
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12062586
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04/04/2008
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08/07/2008
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TEST YIELD ESTIMATE FOR SEMICONDUCTOR PRODUCTS CREATED FROM A LIBRARY
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02/09/2010
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12062592
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04/04/2008
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09/11/2008
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AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS
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02/02/2010
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12062612
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04/04/2008
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11/27/2008
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METAL SPACER IN SINGLE AND DUAL DAMASCENE PROCESSING
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05/22/2012
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12062618
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04/04/2008
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08/07/2008
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DEVICE COMPONENT FORMING METHOD WITH A TRIM STEP PRIOR TO SIDEWALL IMAGE TRANSFER (SIT) PROCESSING
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10/05/2010
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12062665
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04/04/2008
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08/07/2008
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Title:
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VERSATILE SI-BASED PACKAGING WITH INTEGRATED PASSIVE COMPONENTS FOR MMWAVE APPLICATIONS
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04/06/2010
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12062749
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04/04/2008
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11/20/2008
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LASER PROCESSING METHOD FOR TRENCH-EDGE-DEFECT-FREE SOLID PHASE EPITAXY IN CONFINED GEOMETRICS
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12/28/2010
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12062972
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04/04/2008
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07/31/2008
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LOW THRESHOLD VOLTAGE SEMICONDUCTOR DEVICE WITH DUAL THRESHOLD VOLTAGE CONTROL MEANS
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08/31/2010
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12077973
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03/24/2008
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07/24/2008
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METHOD OF MAKING DOUBLE-GATED SELF-ALIGNED FINFET HAVING GATES OF DIFFERENT LENGTHS
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06/17/2014
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12080266
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04/01/2008
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12/23/2010
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Title:
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SILICON BASED OPTICAL VIAS
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05/05/2009
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12098038
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04/04/2008
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Title:
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SYSTEM FOR EXPANDING A WINDOW OF VALID DATA
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09/11/2012
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12098172
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04/04/2008
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08/07/2008
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Title:
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METHOD AND APPARATUS FOR GENERATING PROFILE OF SOLUTIONS TRADING OFF NUMBER OF ACTIVITIES UTILIZED AND OBJECTIVE VALUE FOR BILINEAR INTEGER OPTIMIZATION MODELS
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NONE
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12098479
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04/07/2008
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08/07/2008
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Title:
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METHOD AND STRUCTURE FOR INTEGRATING MIM CAPACITORS WITHIN DUAL DAMASCENE PROCESSING TECHNIQUES
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NONE
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12098715
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04/07/2008
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Pub Dt:
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09/04/2008
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Title:
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DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS
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05/24/2011
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12098895
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04/07/2008
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Pub Dt:
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10/16/2008
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Title:
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ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTI-LAYER HARDMASK SCHEME
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NONE
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12099016
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04/07/2008
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Pub Dt:
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10/16/2008
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Title:
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MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
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12/30/2014
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12099175
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04/08/2008
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10/08/2009
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE
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02/15/2011
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12099211
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04/08/2008
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08/07/2008
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Title:
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SUBSTRATE BACKGATE FOR TRIGATE FET
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06/23/2009
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12099304
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Filing Dt:
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04/08/2008
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Title:
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METHOD FOR DETECTING ALPHA PARTICLES IN SOI TECHNOLOGY
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01/25/2011
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12099307
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04/08/2008
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Pub Dt:
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10/08/2009
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Title:
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DESIGN STRUCTURE FOR ALPHA PARTICLE SENSOR IN SOI TECHNOLOGY AND STRUCTURE THEREOF
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09/28/2010
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12099316
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04/08/2008
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Pub Dt:
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10/08/2009
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Title:
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DEVICE STRUCTURES WITH A HYPER-ABRUPT P-N JUNCTION, METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION, AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT
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06/08/2010
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12099339
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04/08/2008
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Pub Dt:
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10/08/2009
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Title:
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PIXEL SENSOR WITH REDUCED IMAGE LAG
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12/21/2010
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12099381
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04/08/2008
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Pub Dt:
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09/11/2008
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Title:
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ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
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08/17/2010
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12099412
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04/08/2008
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Publication #:
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Pub Dt:
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09/18/2008
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Title:
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ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
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06/21/2011
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12099423
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04/08/2008
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Pub Dt:
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08/07/2008
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Title:
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DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL
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07/27/2010
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12099437
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04/08/2008
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Pub Dt:
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09/25/2008
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Title:
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ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF
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10/05/2010
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12099879
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04/09/2008
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10/15/2009
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Title:
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SOI TRANSISTOR WITH MERGED LATERAL BIPOLAR TRANSISTOR
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NONE
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12099904
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04/09/2008
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Pub Dt:
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10/15/2009
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Title:
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METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER
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12/08/2009
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12099996
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04/09/2008
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10/15/2009
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Title:
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STRUCTURE AND METHOD FOR HYBRID TUNGSTEN COPPER METAL CONTACT
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NONE
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12099998
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04/09/2008
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12/04/2008
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Title:
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Layout Generator for Routing and Designing an LSI
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02/01/2011
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12100441
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04/10/2008
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10/15/2009
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Title:
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2-T SRAM CELL STRUCTURE AND METHOD
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12/15/2009
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12100480
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04/10/2008
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07/31/2008
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Title:
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SOCKET AND METHOD FOR COMPENSATING FOR DIFFERING COEFFICIENTS OF THERMAL EXPANSION
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06/28/2011
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12100481
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04/10/2008
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10/15/2009
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Title:
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ASSESSING RESOURCES REQUIRED TO COMPLETE A VLSI DESIGN
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10/08/2013
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12100592
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04/10/2008
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Pub Dt:
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10/02/2008
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Title:
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DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR
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02/23/2010
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12100615
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04/10/2008
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Pub Dt:
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08/14/2008
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Title:
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METHOD AND APPARATUS FOR IMPROVING INTEGRATED CIRCUIT DEVICE PERFORMANCE USING HYBRID CRYSTAL ORIENTATIONS
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03/23/2010
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12100644
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04/10/2008
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Pub Dt:
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08/21/2008
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Title:
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PRE-EPITAXIAL DISPOSABLE SPACER INTEGRATION SCHEME WITH VERY LOW TEMPERATURE SELECTIVE EPITAXY FOR ENHANCED DEVICE PERFORMANCE
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11/16/2010
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12100708
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04/10/2008
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10/15/2009
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Title:
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METAL GATE COMPATIBLE FLASH MEMORY GATE STACK
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10/25/2011
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12101329
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04/11/2008
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10/15/2009
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Title:
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METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS
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10/01/2013
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12101441
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04/11/2008
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10/15/2009
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Title:
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CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
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10/14/2014
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12101449
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04/11/2008
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10/15/2009
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Title:
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CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
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04/05/2011
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12101455
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04/11/2008
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Pub Dt:
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10/15/2009
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Title:
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CONTROLLING IMPEDANCE AND THICKNESS VARIATIONS FOR MULTILAYER ELECTRONIC STRUCTURES
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02/09/2010
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12101599
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04/11/2008
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08/14/2008
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Title:
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CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
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07/10/2012
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12102032
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04/14/2008
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Pub Dt:
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10/15/2009
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Title:
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SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES WITH A BODY-TO-SUBSTRATE CONNECTION FOR ENHANCED ELECTROSTATIC DISCHARGE PROTECTION, AND DESIGN STRUCTURES FOR SUCH SEMICONDUCTOR-ON-INSULATOR DEVICE STRUCTURES
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12/28/2010
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12102035
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04/14/2008
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10/15/2009
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Title:
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FINAL VIA STRUCTURES FOR BOND PAD-SOLDER BALL INTERCONNECTIONS
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04/13/2010
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12102051
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04/14/2008
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Pub Dt:
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10/15/2009
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Title:
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RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) PACKAGES WITH INTEGRATED APERTURE-COUPLED PATCH ANTENNA(S) IN RING AND/OR OFFSET CAVITIES
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10/04/2011
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12102097
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04/14/2008
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Pub Dt:
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02/04/2010
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Title:
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HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS
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08/10/2010
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12102116
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04/14/2008
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Pub Dt:
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09/04/2008
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Title:
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SPECIFYING A CONFIGURATION FOR A DIGITAL SYSTEM UTILIZING DIAL BIASING WEIGHTS
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NONE
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12102333
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04/14/2008
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Pub Dt:
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10/15/2009
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Title:
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FINFET DEVICES FROM BULK SEMICONDUCTOR AND METHODS FOR MANUFACTURING THE SAME
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12/14/2010
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12102510
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04/14/2008
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Pub Dt:
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08/14/2008
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Title:
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PERFORMING TEMPORAL CHECKING
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Patent #:
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NONE
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12102525
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Filing Dt:
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04/14/2008
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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PERFORMING TEMPORAL CHECKING
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Patent #:
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10/26/2010
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12103000
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Filing Dt:
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04/15/2008
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Publication #:
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Pub Dt:
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08/14/2008
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Title:
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TRENCH WIDENING WITHOUT MERGING
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08/09/2011
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12103038
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Filing Dt:
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04/15/2008
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Pub Dt:
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08/14/2008
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Title:
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SYSTEM AND METHOD FOR DESIGNING A LOW LEAKAGE MONOTONIC CMOS LOGIC CIRCUIT
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05/22/2012
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12103110
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04/15/2008
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Pub Dt:
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08/14/2008
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Title:
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APPARATUS FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE
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06/09/2009
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12103129
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04/15/2008
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Pub Dt:
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08/14/2008
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Title:
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METHOD FOR DIVIDING A HIGH-FREQUENCY SIGNAL
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Issue Dt:
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07/20/2010
|
Application #:
|
12103212
|
Filing Dt:
|
04/15/2008
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Publication #:
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|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHODS FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12103256
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
PARTIALLY UNDERFILLED SOLDER GRID ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12103301
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
10/15/2009
| | | | |
Title:
|
COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12103538
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SYSTEM AND PROGRAM PRODUCT FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12103548
|
Filing Dt:
|
04/15/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12103804
|
Filing Dt:
|
04/16/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
SYSTEM AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
12104103
|
Filing Dt:
|
04/16/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD AND DEVICE INCLUDING REWORKABLE ALPHA PARTICLE BARRIER AND CORROSION BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
12104132
|
Filing Dt:
|
04/16/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
REGULATED VOLTAGE BOOST CHARGE PUMP FOR AN INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12104461
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12104475
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12104513
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
12104526
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/2010
|
Application #:
|
12104570
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12104643
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12104683
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S)
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12104852
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD FOR OPTIMIZATION OF LOGIC CIRCUITS FOR ROUTABILITY IMPROVEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
12105034
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12105037
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS NI ALLOY SILICIDE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12105217
|
Filing Dt:
|
04/17/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION INVOLVING DATA STORAGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12105311
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
TEST METHOD FOR DETERMINING RETICLE TRANSMISSION STABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12105349
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
SYSTEM AND METHODS TO EXTEND THE SERVICE LIFE OF PORTABLE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12105366
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
PROGRAMMING OF LASER FUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12105395
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
CAPACITOR BELOW THE BURIED OXIDE OF SOI CMOS TECHNOLOGIES FOR PROTECTION AGAINST SOFT ERRORS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12105430
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
09/04/2008
| | | | |
Title:
|
ASYNCHRONOUS HIDDEN MARKOV MODEL METHOD AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12105449
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT DESIGN STRUCTURE FOR AN ASYCHRONOUS DATA INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12105494
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12105600
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2011
|
Application #:
|
12105622
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
METHOD FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12105883
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR CHIP IDENTIFICATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
07/13/2010
|
Application #:
|
12106018
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
GENERATION OF HARDWARE THERMAL PROFILES FOR A SET OF PROCESSORS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12106053
|
Filing Dt:
|
04/18/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE HAVING CLONE LATCH SUPPORT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
12106361
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
08/07/2008
| | | | |
Title:
|
HDL DESIGN STRUCTURE FOR INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT DESIGN
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12106373
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
Method in a Computer-aided Design System for Generating a Functional Design Model of a Test Structure
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12106396
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
08/21/2008
| | | | |
Title:
|
STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2009
|
Application #:
|
12106416
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
Title:
|
PROGRAM PRODUCT FOR DEFINING AND RECORDING MINIMUM AND MAXIMUM EVENT COUNTS OF A SIMULATION UTILIZING A HIGH LEVEL LANGUAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12106462
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
Title:
|
A METHOD OF OPERATIVELY COMBINING A PLURALITY OF COMPONENTS TO FORM A LAND GRIP ARRAY INTERPOSER (LGA) STRUCTURE UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12106476
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
FINFETS SINGLE-SIDED IMPLANT FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12106531
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
08/14/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT TRANSFORMER DEVICES FOR ON-CHIP MILLIMETER-WAVE APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12106539
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
07/30/2009
| | | | |
Title:
|
CROSS POINT SWITCH USING PHASE CHANGE MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12106557
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
METAL-GATE THERMOCOUPLE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
|
Application #:
|
12106586
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
Title:
|
Methods and structures for protecting one area while processing another area on a chip
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12106983
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
09/11/2008
| | | | |
Title:
|
ELECTRONIC COMPONENT AND TAPE HEAD HAVING A CLOSURE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12107064
|
Filing Dt:
|
04/21/2008
|
Publication #:
|
|
Pub Dt:
|
10/22/2009
| | | | |
Title:
|
ORGANIC SUBSTRATE WITH ASYMMETRIC THICKNESS FOR WARP MITIGATION
|
|