|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12137646
|
Filing Dt:
|
06/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
02/05/2009
| | | | |
|
Title:
|
POLYCRYSTALLINE CONDUCTING POLYMERS AND PRECURSORS THEREOF HAVING ADJUSTABLE MORPHOLOGY AND PROPERTIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12137743
|
Filing Dt:
|
06/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
CHEMICAL TRIM OF PHOTORESIST LINES BY MEANS OF A TUNED OVERCOAT MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12137953
|
Filing Dt:
|
06/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
APPARATUS OF CAPACITY LEARNING FOR COMPUTER SYSTEMS AND APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12138099
|
Filing Dt:
|
06/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
WRITE FILTER CACHE METHOD AND APPARATUS FOR PROTECTING THE MICROPROCESSOR CORE FROM SOFT ERRORS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12138214
|
Filing Dt:
|
06/12/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
12138482
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
SOLDER CONNECTOR STRUCTURE AND METHOD
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12138514
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
12138531
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
METHOD OF CREATING CONTOUR STRUCTURES TO HIGHLIGHT INSPECTION REGION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12138532
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
DETECTING X STATE TRANSITIONS AND STORING COMPRESSED DEBUG INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12138536
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
TRENCH CAPACITORS AND MEMORY CELLS USING TRENCH CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12138871
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
STATIC TIMING SLACKS ANALYSIS AND MODIFICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
12139080
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
DEFECT REDUCTION BY OXIDATION OF SILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2010
|
Application #:
|
12139358
|
Filing Dt:
|
06/13/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
APPARATUS FOR ANALYZING POST-LAYOUT TIMING CRITICAL PATHS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12139476
|
Filing Dt:
|
06/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
HIGHLY SPECIALIZED SCENARIOS IN RANDOM TEST GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12139483
|
Filing Dt:
|
06/15/2008
|
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
|
Title:
|
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR AUTOMATED VERIFICATION OF GATING LOGIC USING FORMAL VERIFICATION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12139523
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
PIXEL SENSOR CELL, METHODS AND DESIGN STRUCTURE INCLUDING OPTICALLY TRANSPARENT GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
12139524
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
PIXEL SENSOR CELL, METHODS AND DESIGN STRUCTURE INCLUDING OPTICALLY TRANSPARENT GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
12139564
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
NETWORK BASED ENERGY PREFERENCE SERVICE FOR MANAGING ELECTRIC VEHICLE CHARGING PREFERENCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12139574
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
ELECTRIC VEHICLE CHARGING TRANSACTION INTERFACE FOR MANAGING ELECTRIC VEHICLE CHARGING TRANSACTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12139704
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
INTERCONNECT STRUCTURE FOR ELECTROMIGRATION ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12139716
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/02/2008
| | | | |
|
Title:
|
MULTI-LEVEL INTERCONNECTIONS FOR AN INTEGRATED CIRCUIT CHIP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12139722
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
MULTI-EXPOSURE LITHOGRAPHY EMPLOYING DIFFERENTIALLY SENSITIVE PHOTORESIST LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12139803
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12139928
|
Filing Dt:
|
06/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
SELF-LEARNING OF THE OPTIMAL POWER OR PERFORMANCE OPERATING POINT OF A COMPUTER CHIP BASED ON INSTANTANEOUS FEEDBACK OF PRESENT OPERATING ENVIRONMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12140335
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
DUTY CYCLE CORRECTION CIRCUIT WHOSE OPERATION IS LARGELY INDEPENDENT OF OPERATING VOLTAGE AND PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12140366
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/13/2008
| | | | |
|
Title:
|
INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12140479
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
TEST STRUCTURE FOR DETECTING VIA CONTACT SHORTING IN SHALLOW TRENCH ISOLATION REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
12140489
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
SUPERVISOR PARTITIONING OF CLIENT RESOURCES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12140492
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/17/2009
| | | | |
|
Title:
|
METHODS OF SEPARATING INTEGRATED CIRCUIT CHIPS FABRICATED ON A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12140535
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
|
Title:
|
PHASE LOCKED LOOP APPARATUS WITH ADJUSTABLE PHASE SHIFT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12140561
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR READ/WRITE CONTROL AND BIT SELECTION WITH FALSE READ SUPPRESSION IN AN SRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
12140600
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
METHOD OF CREATING DEFECT FREE HIGH GE CONTENT (> 25%) SIGE-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12140612
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
12140714
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
METHOD FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12140854
|
Filing Dt:
|
06/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
POLYCARBOSILANE BURIED ETCH STOPS IN INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
12141121
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
SERVO SYSTEM FOR A TWO-DIMENSIONAL MICRO-ELECTROMECHANICAL SYSTEM (MEMS)-BASED SCANNER AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12141183
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
Early HSS Rx Data Sampling
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12141276
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12141311
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
WORK FUNCTION ENGINEERING FOR EDRAM MOSFETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12141314
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
CMOS DEVICES HAVING REDUCED THRESHOLD VOLTAGE VARIATIONS AND METHODS OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12141453
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
USER SELECTED GRID FOR LOGICALLY REPRESENTING AN ELECTRONIC CIRCUIT
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12141476
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
METHOD OF FORMING HfSiN METAL FOR n-FET APPLICATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2009
|
Application #:
|
12141556
|
Filing Dt:
|
06/18/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
COUPLING ELEMENT ALIGNMENT USING WAVEGUIDE FIDUCIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12141960
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
APPARATUS FOR PROVIDING ERROR CORRECTION CAPABILITY TO LONGITUDINAL POSITION DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2012
|
Application #:
|
12141962
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
APPARATUS FOR PROVIDING ERROR CORRECTION CAPABILITY TO LONGITUDINAL POSITION DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
12142000
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/03/2014
|
Application #:
|
12142094
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
REDUCING WIRE EROSION DURING DAMASCENE PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12142123
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/09/2008
| | | | |
|
Title:
|
DIGITAL PHASE AND FREQUENCY DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12142239
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
|
12142325
|
Filing Dt:
|
06/19/2008
|
|
Title:
|
SYSTEMS AND METHODS FOR ENUMERATIVE ENCODING AND DECODING OF MAXIMUM-TRANSITION-RUN CODES AND PRML (G,I,M) CODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/19/2010
|
Application #:
|
12142394
|
Filing Dt:
|
06/19/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
NITRIDE-ENCAPSULATED FET (NNCFET)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
12142849
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
SECTIONAL FIELD EFFECT DEVICES AND METHOD OF FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12142870
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12142896
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12142997
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
03/19/2009
| | | | |
|
Title:
|
PLANAR ARRAY CONTACT MEMORY CARDS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12143007
|
Filing Dt:
|
06/20/2008
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|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12143213
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
12143289
|
Filing Dt:
|
06/20/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
COOLING APPARATUS AND METHOD OF FABRICATION THEREOF WITH A COLD PLATE FORMED IN SITU ON A SURFACE TO BE COOLED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12143864
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
APPARATUS FOR IMPLEMENTING DOMINO SRAM LEAKAGE CURRENT REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
12143912
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/2010
|
Application #:
|
12143917
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12143918
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
MULTILAYERED CAP BARRIER IN MICROELECTRONIC INTERCONNECT STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12143940
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2008
| | | | |
|
Title:
|
PISTON RESET APPARATUS FOR A MULTICHIP MODULE AND METHOD FOR RESETTING PISTONS IN THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12144071
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/2010
|
Application #:
|
12144084
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12144089
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12144095
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/2010
|
Application #:
|
12144139
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
METHOD OF FORMING A DUAL GATED FINFET GAIN CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12144229
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/2010
|
Application #:
|
12144250
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12144272
|
Filing Dt:
|
06/23/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12144682
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12144684
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12144686
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12144703
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
DESIGN STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
12144998
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BICMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12145024
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12145025
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/24/2009
| | | | |
|
Title:
|
METHOD FOR OPTIMIZING THE ROUTING OF WAFERS/LOTS BASED ON YIELD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
12145113
|
Filing Dt:
|
06/24/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
CMOS SILICIDE METAL GATE INTEGRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
12145406
|
Filing Dt:
|
06/24/2008
|
|
Title:
|
METHOD FOR DETERMINATION OF EFFICIENT LIGHTING USE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12145502
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
BALANCING POWER PLANE PIN CURRENTS AND IMPROVING STRENGTH IN A PRINTED WIRING BOARD USING COLLINEAR SLOTS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12145616
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
VERTICAL PROFILE FinFET GATE FORMED VIA PLATING UPON A THIN GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/2010
|
Application #:
|
12145622
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
12145715
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
REDUCED POWER CONSUMPTION LIMITED-SWITCH DYNAMIC LOGIC (LSDL) CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2010
|
Application #:
|
12145857
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
VERTICAL P-N JUNCTION DEVICE AND METHOD OF FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12145915
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
|
Title:
|
MASK FORMING AND IMPLANTING METHODS USING IMPLANT STOPPING LAYER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12145922
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/20/2008
| | | | |
|
Title:
|
MASK HAVING IMPLANT STOPPING LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12146128
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
WRITE OPERATIONS FOR PHASE-CHANGE-MATERIAL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
12146310
|
Filing Dt:
|
06/25/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/16/2008
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR THE COMPRESSION OF PROBABILITY TABLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12146500
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
STRUCTURES, FABRICATION METHODS, AND DESIGN STRUCTURES FOR MULTIPLE BIT FLASH MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/2010
|
Application #:
|
12146546
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
METHODS OF FABRICATING A BEOL WIRING STRUCTURE CONTAINING AN ON-CHIP INDUCTOR AND AN ON-CHIP CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/2010
|
Application #:
|
12146554
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
APPARATUS FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12146555
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
BEOL WIRING STRUCTURES THAT INCLUDE AN ON-CHIP INDUCTOR AND AN ON-CHIP CAPACITOR, AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12146560
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
BAND GAP MODULATED OPTICAL SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/30/2011
|
Application #:
|
12146575
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
BAND GAP MODULATED OPTICAL SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
12146576
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
10/23/2008
| | | | |
|
Title:
|
FLIP FERAM CELL AND METHOD TO FORM SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
12146601
|
Filing Dt:
|
06/26/2008
|
|
Title:
|
CIRCULAR GRATING RESONATOR WITH INTEGRATED ELECTRO-OPTICAL MODULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12146728
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
STRUCTURES, FABRICATION METHODS, DESIGN STRUCTURES FOR STRAINED FIN FIELD EFFECT TRANSISTORS (FINFETS)
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12146757
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
PLASTIC LAND GRID ARRAY (PLGA) MODULE AND PRINTED WIRING BOARD (PWB) WITH ENHANCED CONTACT METALLURGY CONSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12146777
|
Filing Dt:
|
06/26/2008
|
|
Publication #:
|
|
Pub Dt:
|
12/31/2009
| | | | |
|
Title:
|
HIGH PERFORMANCE READ BYPASS TEST FOR SRAM CIRCUITS
|
|
