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|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12185759
|
Filing Dt:
|
08/04/2008
|
Publication #:
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|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
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|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12186061
|
Filing Dt:
|
08/05/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
IC HAVING VIABAR INTERCONNECTION AND RELATED METHOD
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|
Patent #:
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|
Issue Dt:
|
10/29/2013
|
Application #:
|
12186075
|
Filing Dt:
|
08/05/2008
|
Publication #:
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|
Pub Dt:
|
11/20/2008
| | | | |
Title:
|
CMOS GATE STRUCTURES FABRICATED BY SELECTIVE OXIDATION
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|
|
Patent #:
|
|
Issue Dt:
|
07/06/2010
|
Application #:
|
12186243
|
Filing Dt:
|
08/05/2008
|
Publication #:
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|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
CRYSTALLINE SILICON SUBSTRATES WITH IMPROVED MINORITY CARRIER LIFETIME INCLUDING A METHOD OF ANNEALING AND REMOVING SIOX PRECIPITATES AND GETTERNING SITES
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|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12186588
|
Filing Dt:
|
08/06/2008
|
Publication #:
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|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
ROBUST JITTER-FREE REMOTE CLOCK OFFSET MEASURING METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12186655
|
Filing Dt:
|
08/06/2008
|
Publication #:
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|
Pub Dt:
|
03/12/2009
| | | | |
Title:
|
DUAL-SIDED CHIP ATTACHED MODULES
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|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12186750
|
Filing Dt:
|
08/06/2008
|
Publication #:
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|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS
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|
Patent #:
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|
Issue Dt:
|
05/17/2011
|
Application #:
|
12186762
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METHOD FOR SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS AND DESIGN STRUCTURE THEREOF
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|
Patent #:
|
|
Issue Dt:
|
08/18/2009
|
Application #:
|
12186764
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
01/29/2009
| | | | |
Title:
|
IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING
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|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12186767
|
Filing Dt:
|
08/06/2008
|
Publication #:
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|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
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|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
12186769
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
01/29/2009
| | | | |
Title:
|
IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING
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|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12186780
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING
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|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12187003
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
ELECTRICAL ANTIFUSE HAVING A MULTI-THICKNESS DIELECTRIC LAYER
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|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12187164
|
Filing Dt:
|
08/06/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
POWER DELIVERY ANALYSIS AND DESIGN
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|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12187415
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE, DESIGN STRUCTURE, AND METHOD HAVING IMPROVED ISOLATION AND HARMONICS
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|
|
Patent #:
|
|
Issue Dt:
|
09/28/2010
|
Application #:
|
12187419
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
INTEGRATED CIRCUIT STRUCTURE, DESIGN STRUCTURE, AND METHOD HAVING IMPROVED ISOLATION AND HARMONICS
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|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12187436
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE
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|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12187442
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12187453
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
Underfill Air Vent for Flipchip BGA
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
12187511
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
MEMORY CONTROLLER FOR REDUCING TIME TO INITIALIZE MAIN MEMORY
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|
|
Patent #:
|
|
Issue Dt:
|
12/07/2010
|
Application #:
|
12187759
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
PROBE FOR SCANNING OVER A SUBSTRATE AND A DATA STORAGE DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2012
|
Application #:
|
12187767
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12187917
|
Filing Dt:
|
08/07/2008
|
Publication #:
|
|
Pub Dt:
|
07/02/2009
| | | | |
Title:
|
METHOD OF FORMING A BOTTLE-SHAPED TRENCH BY ION IMPLANTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2010
|
Application #:
|
12188230
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METHOD OF MAKING THROUGH WAFER VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/2011
|
Application #:
|
12188234
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METAL WIRING STRUCTURE FOR INTEGRATION WITH THROUGH SUBSTRATE VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12188235
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
COMBINATION VIA AND PAD STRUCTURE FOR IMPROVED SOLDER BUMP ELECTROMIGRATION CHARACTERISTICS
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|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12188243
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE
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|
|
Patent #:
|
|
Issue Dt:
|
09/06/2011
|
Application #:
|
12188366
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE
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|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12188381
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE
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|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12188749
|
Filing Dt:
|
08/08/2008
|
Publication #:
|
|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METHODS AND SYSTEMS FOR ON-THE-FLY CHIP VERIFICATION
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|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12189298
|
Filing Dt:
|
08/11/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES
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|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12189344
|
Filing Dt:
|
08/11/2008
|
Publication #:
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|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
PATTERN INDEPENDENT SI:C SELECTIVE EPITAXY
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|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12189388
|
Filing Dt:
|
08/11/2008
|
Publication #:
|
|
Pub Dt:
|
01/08/2009
| | | | |
Title:
|
ROTATIONAL FILL TECHNIQUES FOR INJECTION MOLDING OF SOLDER
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12189639
|
Filing Dt:
|
08/11/2008
|
Publication #:
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|
Pub Dt:
|
02/11/2010
| | | | |
Title:
|
METHOD OF MAKING AN MOSFET HAVING SELF-ALIGNED SILICIDED SCHOTTKY BODY TIE INCLUDING INTENTIONALLY PULL-DOWN OF AN STI DIELECTRIC EXPOSING SIDEWALL OF DIFFUSION REGION.
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|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
12189822
|
Filing Dt:
|
08/12/2008
|
Publication #:
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|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
FILL HEAD FOR INJECTION MOLDING OF SOLDER
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|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12189983
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
NON-VOLATILE PROGRAMMABLE OPTICAL ELEMENT EMPLOYING F-CENTERS
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|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12190028
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH SUPPRESSED CORNER LEAKAGE THROUGH CHANNEL MATERIAL BAND-EDGE MODULATION, DESIGN STRUCTURE AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
12190040
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
DESIGN STRUCTURE, STRUCTURE AND METHOD OF USING ASYMMETRIC JUNCTION ENGINEERED SRAM PASS GATES
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|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12190041
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE
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|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12190067
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
STRUCTURE AND METHOD OF USING ASYMMETRIC JUNCTION ENGINEERED SRAM PASS GATES, AND DESIGN STRUCTURE
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12190109
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
FIELD EFFECT DEVICE HAVING GATE DIELECTRIC PORTION UNDER THE GATE ELECTRODE THINNER THAN THAT UNDER THE GATE SIDEWALL SPACER
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|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12190123
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
METAL-GATE HIGH-K REFERENCE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12190129
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
METAL OXYNITRIDE AS A PFET MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/2010
|
Application #:
|
12190173
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
METHOD OF MAKING A SIDEWALL-PROTECTED METALLIC PILLAR ON A SEMICONDUCTOR SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
12190220
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
CHANGING EFFECTIVE WORK FUNCTION USING ION IMPLANTATION DURING DUAL WORK FUNCTION METAL GATE INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12190242
|
Filing Dt:
|
08/12/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
FUNCTIONAL FLOAT MODE SCREEN TO TEST FOR LEAKAGE DEFECTS ON SRAM BITLINES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12190657
|
Filing Dt:
|
08/13/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
ERASEABLE NONVOLATILE MEMORY WITH SIDEWALL STORAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/2010
|
Application #:
|
12190777
|
Filing Dt:
|
08/13/2008
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
11/19/2013
|
Application #:
|
12191226
|
Filing Dt:
|
08/13/2008
|
Publication #:
|
|
Pub Dt:
|
11/27/2008
| | | | |
Title:
|
DEVICE SELECT SYSTEM FOR MULTI-DEVICE ELECTRONIC SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12191379
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING A STRUCTURE HAVING VIAS AND HIGH DENSITY CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12191385
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING A STRUCTURE HAVING VIAS AND HIGH DENSITY CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12191425
|
Filing Dt:
|
08/14/2008
|
Publication #:
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|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
FINFET WITH LONGITUDINAL STRESS IN A CHANNEL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
|
Application #:
|
12191441
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
03/05/2009
| | | | |
Title:
|
SYSTEM FOR PERFORMING A CO-SIMULATION AND/OR EMULATION OF HARDWARE AND SOFTWARE
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|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12191519
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
ACTIVE INDUCTOR FOR ASIC APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12191522
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
INTERCONNECT STRUCTURES, DESIGN STRUCTURE AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/2010
|
Application #:
|
12191534
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
RELIABILITY OF WIDE INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12191538
|
Filing Dt:
|
08/14/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
VALIDATING MANUFACTURING TEST RULES PERTAINING TO AN ELECTRONIC COMPONENT
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|
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Patent #:
|
|
Issue Dt:
|
04/19/2011
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Application #:
|
12191543
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Filing Dt:
|
08/14/2008
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Publication #:
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Pub Dt:
|
02/18/2010
| | | | |
Title:
|
REDUNDANT BARRIER STRUCTURE FOR INTERCONNECT AND WIRING APPLICATIONS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE
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|
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Patent #:
|
|
Issue Dt:
|
07/12/2011
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Application #:
|
12191633
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Filing Dt:
|
08/14/2008
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Publication #:
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Pub Dt:
|
02/18/2010
| | | | |
Title:
|
METHODS FOR FORMING BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
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Application #:
|
12191635
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Filing Dt:
|
08/14/2008
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Publication #:
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Pub Dt:
|
02/18/2010
| | | | |
Title:
|
SCALABLE REDUCTION IN REGISTERS WITH SAT-BASED RESUBSTITIUTION
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|
Patent #:
|
NONE
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Issue Dt:
|
|
Application #:
|
12191654
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Filing Dt:
|
08/14/2008
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Publication #:
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|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
TRADING PROPENSITY-BASED CLUSTERING OF CIRCUIT ELEMENTS IN A CIRCUIT DESIGN
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|
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Patent #:
|
|
Issue Dt:
|
12/08/2009
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Application #:
|
12191666
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Filing Dt:
|
08/14/2008
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Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
CIRCUITS AND METHODS FOR IMPLEMENTING TRANSFORMER-COUPLED AMPLIFIERS AT MILLIMETER WAVE FREQUENCIES
|
|
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Patent #:
|
|
Issue Dt:
|
05/10/2011
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Application #:
|
12191683
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Filing Dt:
|
08/14/2008
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Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
BACK-END-OF-LINE RESISTIVE SEMICONDUCTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
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Application #:
|
12191687
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Filing Dt:
|
08/14/2008
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Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
SUSPENDED GERMANIUM PHOTODETECTOR FOR SILICON WAVEGUIDE
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|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
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Application #:
|
12192272
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Filing Dt:
|
08/15/2008
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Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
DESIGN STRUCTURE FOR SWITCHING DIGITAL CIRCUIT CLOCK NET DRIVER WITHOUT LOSING CLOCK PULSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12192309
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
DESIGN STRUCTURE FOR IMPROVED LOGIC SIMULATION USING A NEGATIVE UNKNOWN BOOLEAN STATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2014
|
Application #:
|
12192367
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/12/2009
| | | | |
Title:
|
CAPPING COATING FOR 3D INTEGRATION APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12192387
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
ELECTRICALLY PROGRAMMABLE FUSE AND FABRICATION METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12192491
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12192517
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
STRUCTURE, DESIGN STRUCTURE AND METHOD OF MANUFACTURING DUAL METAL GATE VT ROLL-UP STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12192537
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12192554
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
SPLIT-GATE DRAM WITH MUGFET, DESIGN STRUCTURE, AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12192571
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12192573
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12192586
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
METHOD, CIRCUIT, AND DESIGN STRUCTURE FOR CAPTURING DATA ACROSS A PSEUDO-SYNCHRONOUS INTERFACE
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12192636
|
Filing Dt:
|
08/15/2008
|
Publication #:
|
|
Pub Dt:
|
12/04/2008
| | | | |
Title:
|
SYSTEM AND METHOD OF TRANSFER PRINTING AN ORGANIC SEMICONDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/2012
|
Application #:
|
12193058
|
Filing Dt:
|
08/18/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
DESIGN STRUCTURE FOR COUPLE NOISE CHARACTERIZATION USING A SINGLE OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12193059
|
Filing Dt:
|
08/18/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
STRUCTURE FOR COUPLE NOISE CHARACTERIZATION USING A SINGLE OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12193119
|
Filing Dt:
|
08/18/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
IDENTIFICATION OF VOLTAGE REFERENCE ERRORS IN PCB DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
12193339
|
Filing Dt:
|
08/18/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12193392
|
Filing Dt:
|
08/18/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
12193497
|
Filing Dt:
|
08/18/2008
|
Publication #:
|
|
Pub Dt:
|
02/18/2010
| | | | |
Title:
|
METHOD FOR MONITORING THERMAL CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2012
|
Application #:
|
12193825
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
FABRICATING PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
12193834
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
METHODS OF ION MILLING FOR MAGNETIC HEADS AND SYSTEMS FORMED THEREBY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12193837
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
A METHOD FOR VIA STUB ELIMINATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12193842
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
METHOD OF FORMING A SUBSTRATE HAVING A PLURALITY OF INSULATOR LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12194039
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
A FIELD EFFECT TRANSISTOR HAVING A GATE STRUCTURE WITH A FIRST SECTION ABOVE A CENTER PORTION OF THE CHANNEL REGION AND HAVING A FIRST EFFECTIVE WORK FUNCTION AND SECOND SECTIONS ABOVE EDGES OF THE CHANNEL REGION AND HAVING A SECOND EFFECTIVE WORK FUNCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12194065
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12194198
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
3D INTEGRATED CIRCUIT DEVICE FABRICATION USING INTERFACE WAFER AS PERMANENT CARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12194211
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
12/16/2010
| | | | |
Title:
|
METHOD FOR FABRICATING A 3D INTEGRATED CIRCUIT DEVICE HAVING LOWER-COST ACTIVE CIRCUITRY LAYERS STACKED BEFORE HIGHER-COST ACTIVE CIRCUITRY LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12194448
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
ELECTRONIC PACKAGE WITH A THERMAL INTERPOSER AND METHOD OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12194526
|
Filing Dt:
|
08/19/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
NANOSCALE ELECTRODES FOR PHASE CHANGE MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
12194563
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
12/18/2008
| | | | |
Title:
|
METHOD AND STURCTURE FOR SELF-ALIGNED DEVICE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12194564
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2010
|
Application #:
|
12194566
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
HIGH CAPACITANCE DENSITY VERTICAL NATURAL CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/2012
|
Application #:
|
12194570
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
12/11/2008
| | | | |
Title:
|
ON CHIP TIMING ADJUSTMENT IN MULTI-CHANNEL FAST DATA TRANSFER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12194571
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
ADAPTIVE CLOCK AND EQUALIZATION CONTROL SYSTEMS AND METHODS FOR DATA RECEIVERS IN COMMUNICATIONS SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12195117
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
IMPLEMENTING LOCAL EVALUATION OF DOMINO READ SRAM WITH ENHANCED SRAM CELL STABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12195151
|
Filing Dt:
|
08/20/2008
|
Publication #:
|
|
Pub Dt:
|
02/25/2010
| | | | |
Title:
|
IMPLEMENTING LOCAL EVALUATION OF DOMINO READ SRAM WITH ENHANCED SRAM CELL STABILITY WITH MINIMIZED AREA USAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12195456
|
Filing Dt:
|
08/21/2008
|
Publication #:
|
|
Pub Dt:
|
01/01/2009
| | | | |
Title:
|
HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES
|
|