|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12411612
|
Filing Dt:
|
03/26/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
ESD NETWORK CIRCUIT WITH A THROUGH WAFER VIA STRUCTURE AND A METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12411624
|
Filing Dt:
|
03/26/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
12412406
|
Filing Dt:
|
03/27/2009
|
Title:
|
LOW TEMPERATURE ION IMPLANTATION FOR IMPROVED SILICIDE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12413771
|
Filing Dt:
|
03/30/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
CMOS SIGE CHANNEL PFET AND SI CHANNEL NFET DEVICES WITH MINIMAL STI RECESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12413836
|
Filing Dt:
|
03/30/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
STRUCTURE AND METHOD OF FABRICATING FINFET
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12414794
|
Filing Dt:
|
03/31/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
12415266
|
Filing Dt:
|
03/31/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD FOR EXTRACTING INFORMATION FOR A CIRCUIT DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12415348
|
Filing Dt:
|
03/31/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR EVALUATING A MACHINE TOOL OPERATING CHARACTERISTICS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
12415406
|
Filing Dt:
|
03/31/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
CMP METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12416754
|
Filing Dt:
|
04/01/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12416960
|
Filing Dt:
|
04/02/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
TECHNIQUES FOR FAST AREA-EFFICIENT INCREMENTAL PHYSICAL SYNTHESIS
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12417136
|
Filing Dt:
|
04/02/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
POST-ROUTING COUPLING FIXES FOR INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
12417454
|
Filing Dt:
|
04/02/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
METHOD AND APPARATUS FOR PROBING A WAFER
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/2010
|
Application #:
|
12417954
|
Filing Dt:
|
04/03/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
GATE PATTERNING OF NANO-CHANNEL DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12418896
|
Filing Dt:
|
04/06/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
METHOD OF CONSTRUCTING AN APPROXIMATED DYNAMIC HUFFMAN TABLE FOR USE IN DATA COMPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12419377
|
Filing Dt:
|
04/07/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
ON-CHIP LEAKAGE CURRENT MODELING AND MEASUREMENT CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
12419403
|
Filing Dt:
|
04/07/2009
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
METHOD TO MITIGATE RESIST PATTERN CRITICAL DIMENSION VARIATION IN A DOUBLE-EXPOSURE PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12420157
|
Filing Dt:
|
04/08/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12420258
|
Filing Dt:
|
04/08/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2013
|
Application #:
|
12420589
|
Filing Dt:
|
04/08/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A RETENTION BEHAVIOR FOR AT LEAST ONE BLOCK OF A MEMORY DEVICE HAVING FINITE ENDURANCE AND/OR RETENTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2012
|
Application #:
|
12420628
|
Filing Dt:
|
04/08/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANALYZING MONITOR DATA INFORMATION FROM A PLURALITY OF MEMORY DEVICES HAVING FINITE ENDURANCE AND/OR RETENTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12420879
|
Filing Dt:
|
04/09/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
BLENDED MODEL INTERPOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12420910
|
Filing Dt:
|
04/09/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12422420
|
Filing Dt:
|
04/13/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
METHODOLOGY FOR CORRELATED MEMORY FAIL ESTIMATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12422664
|
Filing Dt:
|
04/13/2009
|
Publication #:
|
|
Pub Dt:
|
08/06/2009
| | | | |
Title:
|
APPARATUS AND METHODS FOR PACKAGING INTEGRATED CIRCUIT CHIPS WITH ANTENNAS FORMED FROM PACKAGE LEAD WIRES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2010
|
Application #:
|
12423055
|
Filing Dt:
|
04/14/2009
|
Publication #:
|
|
Pub Dt:
|
09/10/2009
| | | | |
Title:
|
IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12423236
|
Filing Dt:
|
04/14/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
12423242
|
Filing Dt:
|
04/14/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
BOTTLE-SHAPED TRENCH CAPACITOR WITH ENHANCED CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12423254
|
Filing Dt:
|
04/14/2009
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
PROCESS FOR WET SINGULATION USING A DICING SINGULATION STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
12423516
|
Filing Dt:
|
04/14/2009
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
METHOD FOR FABRICATING AN INORGANIC NANOCOMPOSITE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12423835
|
Filing Dt:
|
04/15/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
ON CHIP SLOW-WAVE STRUCTURE, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12424001
|
Filing Dt:
|
04/15/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
METAL WIRING STRUCTURES FOR UNIFORM CURRENT DENSITY IN C4 BALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12424110
|
Filing Dt:
|
04/15/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
CIRCUIT STRUCTURE AND DESIGN STRUCTURE FOR AN OPTIONALLY SWITCHABLE ON-CHIP SLOW WAVE TRANSMISSION LINE BAND-STOP FILTER AND A METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12424833
|
Filing Dt:
|
04/16/2009
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
Title:
|
COUPLING ELEMENT ALIGNMENT USING WAVEGUIDE FIDUCIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2012
|
Application #:
|
12425603
|
Filing Dt:
|
04/17/2009
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
Title:
|
PHYSICAL DESIGN SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12425689
|
Filing Dt:
|
04/17/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
DETERMINING A DIRECTION OF ARRIVAL OF SIGNALS INCIDENT TO A TRIPOLE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12425843
|
Filing Dt:
|
04/17/2009
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
Title:
|
SICOH FILM PREPARATION USING PRECURSORS WITH BUILT-IN POROGEN FUNCTIONALITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12426457
|
Filing Dt:
|
04/20/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
HIGH-K METAL GATE CMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12426467
|
Filing Dt:
|
04/20/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
MOSFET INCLUDING EPITAXIAL HALO REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12426475
|
Filing Dt:
|
04/20/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2013
|
Application #:
|
12426561
|
Filing Dt:
|
04/20/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
VERTICAL INTEGRATED CIRCUIT SWITCHES, DESIGN STRUCTURE AND METHODS OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
12426607
|
Filing Dt:
|
04/20/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
SYSTEM, METHOD AND GRAPHICAL USER INTERFACE FOR A SIMULATION BASED CALCULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12427247
|
Filing Dt:
|
04/21/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
MULTIPLE VT FIELD-EFFECT TRANSISTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/18/2011
|
Application #:
|
12427484
|
Filing Dt:
|
04/21/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
HIGH DENSITY TERNARY CONTENT ADDRESSABLE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2013
|
Application #:
|
12427775
|
Filing Dt:
|
04/22/2009
|
Publication #:
|
|
Pub Dt:
|
11/26/2009
| | | | |
Title:
|
CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12429374
|
Filing Dt:
|
04/24/2009
|
Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
Title:
|
SYNCHRONOUS AND ASYNCHRONOUS CONTINUOUS DATA PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12430300
|
Filing Dt:
|
04/27/2009
|
Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
Title:
|
IMPLEMENTING VERTICAL AIRGAP STRUCTURES BETWEEN CHIP METAL LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
12431259
|
Filing Dt:
|
04/28/2009
|
Publication #:
|
|
Pub Dt:
|
10/28/2010
| | | | |
Title:
|
UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12431289
|
Filing Dt:
|
04/28/2009
|
Publication #:
|
|
Pub Dt:
|
08/13/2009
| | | | |
Title:
|
VIA BOTTOM CONTACT AND METHOD OF MANUFACTURING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/2011
|
Application #:
|
12431827
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
REWORKABLE ELECTRONIC DEVICE ASSEMBLY AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12431887
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
T-CONNECTIONS, METHODOLOGY FOR DESIGNING T-CONNECTIONS, AND COMPACT MODELING OF T-CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12432082
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
SYSTEM AND METHOD IMPLEMENTING SHORT-PULSE PROPAGATION TECHNIQUE ON PRODUCTION-LEVEL BOARDS WITH INCREMENTAL ACCURACY AND PRODUCTIVITY LEVELS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12432243
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
THROUGH SUBSTRATE VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12432293
|
Filing Dt:
|
04/29/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
METHOD OF MANUFACTURING SOLAR CELL WITH DOPING PATTERNS AND CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12432927
|
Filing Dt:
|
04/30/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
12433157
|
Filing Dt:
|
04/30/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12433220
|
Filing Dt:
|
04/30/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
12433669
|
Filing Dt:
|
04/30/2009
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES
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Patent #:
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Issue Dt:
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12/20/2011
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Application #:
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12434233
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Filing Dt:
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05/01/2009
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Publication #:
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Pub Dt:
|
08/27/2009
| | | | |
Title:
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CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINS
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12434321
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Filing Dt:
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05/01/2009
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Publication #:
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Pub Dt:
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11/12/2009
| | | | |
Title:
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LOW PH MIXTURES FOR THE REMOVAL OF HIGH DENSITY IMPLANTED RESIST
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Patent #:
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Issue Dt:
|
02/21/2012
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Application #:
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12436189
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Filing Dt:
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05/06/2009
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Publication #:
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Pub Dt:
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08/27/2009
| | | | |
Title:
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HIGH-Z STRUCTURE AND METHOD FOR CO-ALIGNMENT OF MIXED OPTICAL AND ELECTRON BEAM LITHOGRAPHIC FABRICATION LEVELS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12436236
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Filing Dt:
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05/06/2009
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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INTERACTIVE CHECKER IN A LAYOUT EDITOR
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12436249
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Filing Dt:
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05/06/2009
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Publication #:
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Pub Dt:
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09/02/2010
| | | | |
Title:
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LOW COST SOI SUBSTRATES FOR MONOLITHIC SOLAR CELLS
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|
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Patent #:
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Issue Dt:
|
05/29/2012
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Application #:
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12437242
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Filing Dt:
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05/07/2009
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Publication #:
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Pub Dt:
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11/11/2010
| | | | |
Title:
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STRUCTURE AND METHOD TO FORM EDRAM ON SOI SUBSTRATE
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Patent #:
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Issue Dt:
|
02/21/2012
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Application #:
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12437263
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Filing Dt:
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05/07/2009
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Publication #:
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Pub Dt:
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08/27/2009
| | | | |
Title:
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NEGATIVE COEFFICIENT OF THERMAL EXPANSION PARTICLES
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Patent #:
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Issue Dt:
|
10/19/2010
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Application #:
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12437575
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Filing Dt:
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05/08/2009
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Publication #:
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Pub Dt:
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08/27/2009
| | | | |
Title:
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ON-CHIP ADJUSTMENT OF MIMCAP AND VNCAP CAPACITORS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12462980
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Filing Dt:
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08/11/2009
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Publication #:
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Pub Dt:
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12/10/2009
| | | | |
Title:
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Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer
|
|
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Patent #:
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Issue Dt:
|
05/08/2012
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Application #:
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12464025
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Filing Dt:
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05/11/2009
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Publication #:
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Pub Dt:
|
11/11/2010
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING
|
|
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Patent #:
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Issue Dt:
|
10/11/2011
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Application #:
|
12464206
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Filing Dt:
|
05/12/2009
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Publication #:
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Pub Dt:
|
11/18/2010
| | | | |
Title:
|
ISOLATION WITH OFFSET DEEP WELL IMPLANTS
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|
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Patent #:
|
|
Issue Dt:
|
03/06/2012
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Application #:
|
12465419
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Filing Dt:
|
05/13/2009
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Publication #:
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Pub Dt:
|
09/03/2009
| | | | |
Title:
|
INTEGRATED THERMOELECTRIC COOLING DEVICES AND METHODS FOR FABRICATING SAME
|
|
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Patent #:
|
|
Issue Dt:
|
02/08/2011
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Application #:
|
12465817
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Filing Dt:
|
05/14/2009
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Publication #:
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|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
METHOD AND STRUCTURE FOR REDUCING INDUCED MECHANICAL STRESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
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Application #:
|
12465857
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Filing Dt:
|
05/14/2009
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Publication #:
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|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
HIGH-VOLTAGE SOI MOS DEVICE STRUCTURE AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2013
|
Application #:
|
12467097
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Filing Dt:
|
05/15/2009
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Publication #:
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Pub Dt:
|
11/18/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR DESIGN SIMPLIFICATION THROUGH IMPLICATION-BASED ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12468297
|
Filing Dt:
|
05/19/2009
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Publication #:
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|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
ETCHING OF TUNGSTEN SELECTIVE TO TITANIUM NITRIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/19/2013
|
Application #:
|
12468391
|
Filing Dt:
|
05/19/2009
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Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
Directed self-assembly of block copolymers using segmented prepatterns
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
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Application #:
|
12468478
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Filing Dt:
|
05/19/2009
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/20/2011
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Application #:
|
12469304
|
Filing Dt:
|
05/20/2009
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Publication #:
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|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
ROBUST TOP-DOWN SILICON NANOWIRE STRUCTURE USING A CONFORMAL NITRIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12469710
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Filing Dt:
|
05/21/2009
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Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
IMPLANTATION USING A HARDMASK
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12469980
|
Filing Dt:
|
05/21/2009
|
Publication #:
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Pub Dt:
|
09/10/2009
| | | | |
Title:
|
MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12470001
|
Filing Dt:
|
05/21/2009
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12470128
|
Filing Dt:
|
05/21/2009
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
SINGLE GATE INVERTER NANOWIRE MESH
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12470159
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Filing Dt:
|
05/21/2009
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Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
NANOWIRE MESH FET WITH MULTIPLE THRESHOLD VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12470693
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Filing Dt:
|
05/22/2009
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
DATA CONSISTENCY IN LONG-RUNNING PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12470760
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Filing Dt:
|
05/22/2009
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Publication #:
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|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
METHOD OF FORMING SUB-LITHOGRAPHIC FEATURES USING DIRECTED SELF-ASSEMBLY OF POLYMERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12471656
|
Filing Dt:
|
05/26/2009
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Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
FORMING SEMICONDUCTOR CHIP CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
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Application #:
|
12471872
|
Filing Dt:
|
05/26/2009
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Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
DEVICE INCLUDING HIGH-K METAL GATE FINFET AND RESISTIVE STRUCTURE AND METHOD OF FORMING THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12472704
|
Filing Dt:
|
05/27/2009
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
DIAGNOSTIC METHOD FOR ROOT-CAUSE ANALYSIS OF FET PERFORMANCE VARIATION
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12472943
|
Filing Dt:
|
05/27/2009
|
Publication #:
|
|
Pub Dt:
|
09/17/2009
| | | | |
Title:
|
Techniques for Layer Transfer Processing
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12473324
|
Filing Dt:
|
05/28/2009
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Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS AND AN UNDERLYING FLOATING WELL SECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/20/2015
|
Application #:
|
12473409
|
Filing Dt:
|
05/28/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
IN-LINE STACKING OF TRANSISTORS FOR SOFT ERROR RATE HARDENING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2012
|
Application #:
|
12473435
|
Filing Dt:
|
05/28/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12473627
|
Filing Dt:
|
05/28/2009
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
HIGH PERFORMANCE TAPERED VARACTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12475494
|
Filing Dt:
|
05/30/2009
|
Publication #:
|
|
Pub Dt:
|
01/20/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR DYNAMIC AUTOMATED HINT GENERATION FOR ENHANCED REACHABILITY ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2012
|
Application #:
|
12475661
|
Filing Dt:
|
06/01/2009
|
Publication #:
|
|
Pub Dt:
|
09/24/2009
| | | | |
Title:
|
GUARD RING STRUCTURES FOR HIGH VOLTAGE CMOS/LOW VOLTAGE CMOS TECHNOLOGY USING LDMOS (LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR) DEVICE FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12476297
|
Filing Dt:
|
06/02/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
WEAR REDUCTION METHODS BY USING COMPRESSION/DECOMPRESSION TECHNIQUES WITH FAST RANDOM ACCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
12476676
|
Filing Dt:
|
06/02/2009
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
METHOD TO IMPROVE NUCLEATION OF MATERIALS ON GRAPHENE AND CARBON NANOTUBES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12477361
|
Filing Dt:
|
06/03/2009
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
BROKEN-SPHERES METHODOLOGY FOR IMPROVED FAILURE PROBABILITY ANALYSIS IN MULTI-FAIL REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12477389
|
Filing Dt:
|
06/03/2009
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
COPPER INTERCONNECT STRUCTURE WITH AMORPHOUS TANTALUM IRIDIUM DIFFUSION BARRIER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12477536
|
Filing Dt:
|
06/03/2009
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
12477945
|
Filing Dt:
|
06/04/2009
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
AUTOMATED TUNING IN WIDE RANGE MULTI-BAND VCO WITH INTERNAL RESET CONCEPT
|
|