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Patent #:
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|
Issue Dt:
|
12/27/2011
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Application #:
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12948246
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Filing Dt:
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11/17/2010
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Title:
|
METHOD OF FORMING REPLACEMENT METAL GATE WITH BORDERLESS CONTACT AND STRUCTURE THEREOF
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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12948805
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Filing Dt:
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11/18/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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METHOD OF FABRICATING FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS
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Patent #:
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Issue Dt:
|
08/07/2012
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Application #:
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12949108
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Filing Dt:
|
11/18/2010
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Publication #:
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|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
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Patent #:
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Issue Dt:
|
08/13/2013
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Application #:
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12949148
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Filing Dt:
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11/18/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A CUT-WAY HOLE TO EXPOSE A PORTION OF A HARDMASK LAYER
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Patent #:
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Issue Dt:
|
06/18/2013
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Application #:
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12949158
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Filing Dt:
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11/18/2010
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Publication #:
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Pub Dt:
|
05/19/2011
| | | | |
Title:
|
Method of Forming Metal Interconnect Structures in Ultra Low-K Dielectrics
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Patent #:
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Issue Dt:
|
12/04/2012
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Application #:
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12949328
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Filing Dt:
|
11/18/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION
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Patent #:
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Issue Dt:
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10/29/2013
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Application #:
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12949888
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Filing Dt:
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11/19/2010
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Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
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|
Patent #:
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|
Issue Dt:
|
06/24/2014
|
Application #:
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12949998
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Filing Dt:
|
11/19/2010
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Publication #:
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|
Pub Dt:
|
11/24/2011
| | | | |
Title:
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CIRCUIT MACRO PLACEMENT USING MACRO ASPECT RATIO BASED ON PORTS
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Patent #:
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Issue Dt:
|
10/22/2013
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Application #:
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12950508
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Filing Dt:
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11/19/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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THERMAL SENSOR FOR SEMICONDUCTOR CIRCUITS
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Patent #:
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Issue Dt:
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07/16/2013
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Application #:
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12950635
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Filing Dt:
|
11/19/2010
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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THIN FILM RESISTORS AND METHODS OF MANUFACTURE
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|
Patent #:
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Issue Dt:
|
07/23/2013
|
Application #:
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12951107
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Filing Dt:
|
11/22/2010
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Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
METHOD OF FORMING E-FUSE IN REPLACEMENT METAL GATE MANUFACTURING PROCESS
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Patent #:
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Issue Dt:
|
03/05/2013
|
Application #:
|
12951516
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Filing Dt:
|
11/22/2010
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
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HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED BASE RESISTANCE
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|
Patent #:
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Issue Dt:
|
02/19/2013
|
Application #:
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12951575
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Filing Dt:
|
11/22/2010
|
Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
|
ISOLATION FET FOR INTEGRATED CIRCUIT
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|
Patent #:
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|
Issue Dt:
|
01/21/2014
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Application #:
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12951597
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Filing Dt:
|
11/22/2010
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
FABRICATING PHOTONICS DEVICES FULLY INTEGRATED INTO A CMOS MANUFACTURING PROCESS
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|
Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
12951674
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Filing Dt:
|
11/22/2010
|
Publication #:
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|
Pub Dt:
|
03/24/2011
| | | | |
Title:
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OPTICAL SENSOR INCLUDING STACKED PHOTODIODES
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|
Patent #:
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Issue Dt:
|
07/09/2013
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Application #:
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12952346
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Filing Dt:
|
11/23/2010
|
Publication #:
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|
Pub Dt:
|
05/26/2011
| | | | |
Title:
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DEVICE COMPRISING A CANTILEVER AND SCANNING SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12952372
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Filing Dt:
|
11/23/2010
|
Publication #:
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|
Pub Dt:
|
05/24/2012
| | | | |
Title:
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BORDERLESS CONTACT FOR REPLACEMENT GATE EMPLOYING SELECTIVE DEPOSITION
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|
Patent #:
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|
Issue Dt:
|
07/16/2013
|
Application #:
|
12952465
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Filing Dt:
|
11/23/2010
|
Publication #:
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|
Pub Dt:
|
05/26/2011
| | | | |
Title:
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Method of Manufacturing a Photovoltaic Cell
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|
|
Patent #:
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|
Issue Dt:
|
12/31/2013
|
Application #:
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12953511
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Filing Dt:
|
11/24/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
DETERMINING LITHOGRAPHIC SET POINT USING OPTICAL PROXIMITY CORRECTION VERIFICATION SIMULATION
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
12953654
|
Filing Dt:
|
11/24/2010
|
Publication #:
|
|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
SEMICONDUCTOR CHIP PACKAGES HAVING REDUCED STRESS
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|
|
Patent #:
|
NONE
|
Issue Dt:
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|
Application #:
|
12953727
|
Filing Dt:
|
11/24/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
VARIATION AWARE TESTING OF SMALL RANDOM DELAY DEFECTS
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|
|
Patent #:
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|
Issue Dt:
|
10/30/2012
|
Application #:
|
12954155
|
Filing Dt:
|
11/24/2010
|
Publication #:
|
|
Pub Dt:
|
05/24/2012
| | | | |
Title:
|
VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS
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|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12954946
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
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|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
12955088
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
HIGH-VOLTAGE SEMICONDUCTOR-ON-INSULATOR DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
12955203
|
Filing Dt:
|
11/29/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER
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|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12955224
|
Filing Dt:
|
11/29/2010
|
Title:
|
FORMING AN OXIDE MEMS BEAM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2012
|
Application #:
|
12955883
|
Filing Dt:
|
11/29/2010
|
Title:
|
REMOVABLE AND REPLACEABLE DUAL-SIDED CONNECTOR PIN INTERPOSER
|
|
|
Patent #:
|
|
Issue Dt:
|
04/01/2014
|
Application #:
|
12956343
|
Filing Dt:
|
11/30/2010
|
Publication #:
|
|
Pub Dt:
|
05/31/2012
| | | | |
Title:
|
DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12957420
|
Filing Dt:
|
12/01/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
CIRCUIT DESIGN APPROXIMATION
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|
|
Patent #:
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|
Issue Dt:
|
09/02/2014
|
Application #:
|
12957431
|
Filing Dt:
|
12/01/2010
|
Publication #:
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|
Pub Dt:
|
03/31/2011
| | | | |
Title:
|
METHOD FOR FORMING A CURRENT DISTRIBUTION STRUCTURE
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|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12957881
|
Filing Dt:
|
12/01/2010
|
Publication #:
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|
Pub Dt:
|
03/24/2011
| | | | |
Title:
|
METHOD AND SYSTEM FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUITRY
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|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12958431
|
Filing Dt:
|
12/02/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
METHOD FOR ENABLING MULTIPLE INCOMPATIBLE OR COSTLY TIMING ENVIRONMENTS FOR EFFICIENT TIMING CLOSURE
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|
Patent #:
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|
Issue Dt:
|
04/23/2013
|
Application #:
|
12958607
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Filing Dt:
|
12/02/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
Self-Aligned Contact For Replacement Gate Devices
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|
Patent #:
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|
Issue Dt:
|
07/09/2013
|
Application #:
|
12958608
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Filing Dt:
|
12/02/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
SELF-ALIGNED CONTACT COMBINED WITH A REPLACEMENT METAL GATE/HIGH-K GATE DIELECTRIC
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|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12958637
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Filing Dt:
|
12/02/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
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CHARACTERIZATION OF NONLINEAR CELL MACRO MODEL FOR TIMING ANALYSIS
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|
|
Patent #:
|
|
Issue Dt:
|
02/10/2015
|
Application #:
|
12958979
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Filing Dt:
|
12/02/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
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PARAMETER VARIATION IMPROVEMENT
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|
Patent #:
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|
Issue Dt:
|
01/29/2013
|
Application #:
|
12959029
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Filing Dt:
|
12/02/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
RESOLVING GLOBAL COUPLING TIMING AND SLEW VIOLATIONS FOR BUFFER-DOMINATED DESIGNS
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|
Patent #:
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Issue Dt:
|
10/30/2012
|
Application #:
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12959697
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Filing Dt:
|
12/03/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
UNDERCUT-REPAIR OF BARRIER LAYER METALLURGY FOR SOLDER BUMPS AND METHODS THEREOF
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|
Patent #:
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|
Issue Dt:
|
02/11/2014
|
Application #:
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12959824
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Filing Dt:
|
12/03/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE
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|
Patent #:
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|
Issue Dt:
|
01/29/2013
|
Application #:
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12959883
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Filing Dt:
|
12/03/2010
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Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
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STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH LEAKAGE SUPPRESSION AND LEVEL CONTROL
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|
Patent #:
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|
Issue Dt:
|
07/02/2013
|
Application #:
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12959993
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Filing Dt:
|
12/03/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
PROGRAM DISTURB ERROR LOGGING AND CORRECTION FOR FLASH MEMORY
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|
Patent #:
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|
Issue Dt:
|
06/11/2013
|
Application #:
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12960004
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Filing Dt:
|
12/03/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY
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|
|
Patent #:
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|
Issue Dt:
|
10/30/2012
|
Application #:
|
12960110
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Filing Dt:
|
12/03/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
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OFFSET SOLDER VIAS, METHODS OF MANUFACTURING AND DESIGN STRUCTURES
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|
|
Patent #:
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Issue Dt:
|
04/16/2013
|
Application #:
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12960586
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Filing Dt:
|
12/06/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
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REPLACEMENT GATE DEVICES WITH BARRIER METAL FOR SIMULTANEOUS PROCESSING
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|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12960589
|
Filing Dt:
|
12/06/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
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STRUCTURE AND METHOD FOR Vt TUNING AND SHORT CHANNEL CONTROL WITH HIGH K/METAL GATE MOSFETs
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|
|
Patent #:
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|
Issue Dt:
|
02/19/2013
|
Application #:
|
12960593
|
Filing Dt:
|
12/06/2010
|
Publication #:
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|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
POLY RESISTOR AND METAL GATE FABRICATION AND STRUCTURE
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|
Patent #:
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|
Issue Dt:
|
10/29/2013
|
Application #:
|
12961553
|
Filing Dt:
|
12/07/2010
|
Publication #:
|
|
Pub Dt:
|
06/07/2012
| | | | |
Title:
|
METAL SEMICONDUCTOR ALLOY CONTACT WITH LOW RESISTANCE
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|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12962722
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
THERMALLY CONTROLLED REFRACTORY METAL RESISTOR
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|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
12963054
|
Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
SEMICONDUCTOR DEVICE INCLUDING ASYMMETRIC LIGHTLY DOPED DRAIN (LDD) REGION, RELATED METHOD AND DESIGN STRUCTURE
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|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12963139
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Filing Dt:
|
12/08/2010
|
Publication #:
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|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
SOLDER BUMP CONNECTIONS
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|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12963246
|
Filing Dt:
|
12/08/2010
|
Publication #:
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|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
CREATING SCAN CHAIN DEFINITION FROM HIGH-LEVEL MODEL USING HIGH-LEVEL MODEL SIMULATION
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|
|
Patent #:
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|
Issue Dt:
|
04/09/2013
|
Application #:
|
12963314
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Filing Dt:
|
12/08/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
NARROW-BAND WIDE-RANGE FREQUENCY MODULATION CONTINUOUS WAVE (FMCW) RADAR SYSTEM
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|
|
Patent #:
|
|
Issue Dt:
|
11/20/2012
|
Application #:
|
12963677
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Filing Dt:
|
12/09/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
MULTISTAGE, HYBRID SYNTHESIS PROCESSING FACILITATING INTEGRATED CIRCUIT LAYOUT
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|
Patent #:
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|
Issue Dt:
|
03/12/2013
|
Application #:
|
12963965
|
Filing Dt:
|
12/09/2010
|
Publication #:
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|
Pub Dt:
|
06/14/2012
| | | | |
Title:
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DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY AT POWER-UP
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|
|
Patent #:
|
|
Issue Dt:
|
08/20/2013
|
Application #:
|
12964082
|
Filing Dt:
|
12/09/2010
|
Publication #:
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|
Pub Dt:
|
06/14/2012
| | | | |
Title:
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PSEUDO BUTTED JUNCTION STRUCTURE FOR BACK PLANE CONNECTION
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|
|
Patent #:
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|
Issue Dt:
|
10/15/2013
|
Application #:
|
12964340
|
Filing Dt:
|
12/09/2010
|
Publication #:
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|
Pub Dt:
|
06/14/2012
| | | | |
Title:
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ADDING SCALABILITY AND FAULT TOLERANCE TO GENERIC FINITE STATE MACHINE FRAMEWORKS FOR USE IN AUTOMATED INCIDENT MANAGEMENT OF CLOUD COMPUTING INFRASTRUCTURES
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|
Patent #:
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|
Issue Dt:
|
12/25/2012
|
Application #:
|
12964807
|
Filing Dt:
|
12/10/2010
|
Publication #:
|
|
Pub Dt:
|
06/14/2012
| | | | |
Title:
|
ASYNCHRONOUS DELETION OF A RANGE OF MESSAGES PROCESSED BY A PARALLEL DATABASE REPLICATION APPLY PROCESS
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|
|
Patent #:
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|
Issue Dt:
|
10/04/2011
|
Application #:
|
12964831
|
Filing Dt:
|
12/10/2010
|
Title:
|
TEMPORARY ETCHABLE LINER FOR FORMING AIR GAP
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|
|
Patent #:
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|
Issue Dt:
|
06/25/2013
|
Application #:
|
12966432
|
Filing Dt:
|
12/13/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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NITRIDE ETCH FOR IMPROVED SPACER UNIFORMITY
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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12967114
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
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Title:
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SELF-PROTECTED ELECTROSTATIC DISCHARGE FIELD EFFECT TRANSISTOR (SPESDFET), AN INTEGRATED CIRCUIT INCORPORATING THE SPESDFET AS AN INPUT/OUTPUT (I/O) PAD DRIVER AND ASSOCIATED METHODS OF FORMING THE SPESDFET AND THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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12967268
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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12/22/2011
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Title:
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TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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12967308
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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ELECTRICAL FUSE WITH A CURRENT SHUNT
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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12967323
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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MEASUREMENT OF CMOS DEVICE CHANNEL STRAIN BY X-RAY DIFFRACTION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12967328
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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Oxide Based LED BEOL Integration
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Patent #:
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Issue Dt:
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04/15/2014
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Application #:
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12967329
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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PARTIALLY DEPLETED (PD) SEMICONDUCTOR-ON-INSULATOR (SOI) FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH A GATE-TO-BODY TUNNEL CURRENT REGION FOR THRESHOLD VOLTAGE (VT) LOWERING AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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12967625
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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METHOD OF FABRICATING PHOTOCONDUCTOR-ON-ACTIVE PIXEL DEVICE
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Patent #:
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Issue Dt:
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01/03/2012
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Application #:
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12967633
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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04/14/2011
| | | | |
Title:
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CONTACT METALLURGY STRUCTURE
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Patent #:
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Issue Dt:
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12/16/2014
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Application #:
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12967771
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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DEVICE ISOLATION WITH IMPROVED THERMAL CONDUCTIVITY
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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12968001
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Filing Dt:
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12/14/2010
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Publication #:
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Pub Dt:
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06/14/2012
| | | | |
Title:
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METHODS AND STRUCTURES FOR INCREASED THERMAL DISSIPATION OF THIN FILM RESISTORS
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Patent #:
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Issue Dt:
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02/25/2014
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Application #:
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12968864
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Filing Dt:
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12/15/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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STRESS TESTING OF SILICON-ON-INSULATOR SUBSTRATES USING APPLIED ELECTROSTATIC DISCHARGE
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12969004
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Filing Dt:
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12/15/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY
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Patent #:
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Issue Dt:
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02/11/2014
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Application #:
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12971199
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Filing Dt:
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12/17/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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BURIED OXIDATION FOR ENHANCED MOBILITY
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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12971239
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Filing Dt:
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12/17/2010
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Publication #:
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Pub Dt:
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04/14/2011
| | | | |
Title:
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BALL GRID ARRAY AND CARD SKEW MATCHING OPTIMIZATION
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Patent #:
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Issue Dt:
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09/09/2014
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Application #:
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12971243
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Filing Dt:
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12/17/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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Deposition of Hydrogenated Thin Film
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Patent #:
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Issue Dt:
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09/10/2013
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Application #:
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12971292
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Filing Dt:
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12/17/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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Fluoroalcohol Containing Molecular Photoresist Materials and Processes of Use
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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12972771
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
|
04/14/2011
| | | | |
Title:
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HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12972879
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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12972934
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH NOTIFICATION OF TRANSFORM SIGNATURES
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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12972980
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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12973062
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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04/14/2011
| | | | |
Title:
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COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12973063
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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08/25/2011
| | | | |
Title:
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FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES
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Patent #:
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Issue Dt:
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02/17/2015
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Application #:
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12973147
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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04/01/2014
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Application #:
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12973285
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
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12/29/2011
| | | | |
Title:
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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12973430
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Filing Dt:
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12/20/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
Title:
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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12974451
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Filing Dt:
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12/21/2010
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Publication #:
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Pub Dt:
|
04/21/2011
| | | | |
Title:
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DEEP TRENCH CAPACITOR IN A SOI SUBSTRATE HAVING A LATERALLY PROTRUDING BURIED STRAP
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Patent #:
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Issue Dt:
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08/02/2016
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Application #:
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12974854
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Filing Dt:
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12/21/2010
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Publication #:
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Pub Dt:
|
12/29/2011
| | | | |
Title:
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PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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12975208
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Filing Dt:
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12/21/2010
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Publication #:
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Pub Dt:
|
04/21/2011
| | | | |
Title:
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MAGNETIC HEADS HAVING MAGNETIC FILMS THAT ARE MORE RECESSED THAN INSULATING FILMS, AND SYSTEMS HAVING SUCH HEADS
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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12975327
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Filing Dt:
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12/21/2010
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Publication #:
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Pub Dt:
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06/21/2012
| | | | |
Title:
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INTEGRATED CIRCUIT SYSTEM WITH REDUCED POLYSILICON RESIDUE AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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03/13/2012
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Application #:
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12976445
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Filing Dt:
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12/22/2010
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Publication #:
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Pub Dt:
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04/21/2011
| | | | |
Title:
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EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS
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Patent #:
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Issue Dt:
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10/22/2013
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Application #:
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12977134
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Filing Dt:
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12/23/2010
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Publication #:
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Pub Dt:
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04/21/2011
| | | | |
Title:
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ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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12981017
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Filing Dt:
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12/29/2010
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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CHANNEL MARKING FOR CHIP MARK OVERFLOW AND CALIBRATION ERRORS
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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12982014
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Filing Dt:
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12/30/2010
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Publication #:
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Pub Dt:
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07/21/2011
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Title:
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MATERIALS AND METHODS FOR IMMOBILIZATION OF CATALYSTS ON SURFACES AND FOR SELECTIVE ELECTROLESS METALLIZATION
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12983297
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Filing Dt:
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01/01/2011
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Publication #:
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Pub Dt:
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06/02/2011
| | | | |
Title:
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CHEMICAL TRIM OF PHOTORESIST LINES BY MEANS OF A TUNED OVERCOAT
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Patent #:
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Issue Dt:
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09/24/2013
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Application #:
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12983352
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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SEMICONDUCTOR DEVICE INCLUDING BODY CONNECTED FETS
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Issue Dt:
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06/25/2013
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Application #:
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12983353
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS
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Issue Dt:
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04/16/2013
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Application #:
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12983377
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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04/28/2011
| | | | |
Title:
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METHOD FOR DIRECT HEAT SINK ATTACHMENT
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Issue Dt:
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10/30/2012
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Application #:
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12983439
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED DIELECTRIC PLATES
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Issue Dt:
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09/09/2014
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Application #:
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12983477
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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05/12/2011
| | | | |
Title:
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METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS
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Issue Dt:
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06/17/2014
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Application #:
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12983489
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Filing Dt:
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01/03/2011
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Publication #:
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Pub Dt:
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07/05/2012
| | | | |
Title:
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JUNCTION FIELD EFFECT TRANSISTOR STRUCTURE WITH P-TYPE SILICON GERMANIUM OR SILICON GERMANIUM CARBIDE GATE(S) AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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12983552
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Filing Dt:
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01/03/2011
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Pub Dt:
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04/28/2011
| | | | |
Title:
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SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS
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