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Patent #:
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Issue Dt:
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03/21/2006
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Application #:
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09756415
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Filing Dt:
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01/08/2001
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Publication #:
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Pub Dt:
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07/11/2002
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Title:
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SELF-ALIGNED COLLAR AND STRAP FORMATION FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09758479
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Filing Dt:
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01/11/2001
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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DELAY LOCK LOOP AND UPDATE METHOD WITH LIMITED DRIFT AND IMPROVED POWER SAVINGS
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09794055
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Filing Dt:
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02/28/2001
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Title:
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DRY POLYMER AND OXIDE VEIL REMOVAL FOR POST ETCH CLEANING
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09797245
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Filing Dt:
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03/01/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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SELF-ALIGNED CROSS-POINT MRAM DEVICE WITH ALUMINUM METALLIZATION LAYERS
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09798101
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Filing Dt:
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03/02/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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A METHOD OF MANUFACTURING A METAL CAP LAYER FOR PREVENTING DAMASCENE CONDUCTIVE LINES FROM OXIDATION
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Patent #:
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Issue Dt:
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02/18/2003
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Application #:
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09818010
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Filing Dt:
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03/27/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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NON-ORTHOGONAL MRAM DEVICE
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09819588
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Filing Dt:
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03/28/2001
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Title:
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On-chip circuits for high speed memory testing with a slow memory tester
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09824596
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Filing Dt:
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04/02/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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METAL HARD MASK FOR ILD RIE PROCESSING OF SEMICONDUCTOR MEMORY DEVICES TO PREVENT OXIDATION OF CONDUCTIVE LINES
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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09854760
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Filing Dt:
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05/14/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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DESIGN OF LITHOGRAPHY ALIGNMENT AND OVERLAY MEASUREMENT MARKS ON CMP FINISHED DAMASCENE SURFACE
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Patent #:
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Issue Dt:
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02/11/2003
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Application #:
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09855561
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Filing Dt:
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05/16/2001
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Publication #:
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Pub Dt:
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11/21/2002
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Title:
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APPARATUS AND PROCESS FOR COLLECTING TRACE METALS FROM WAFERS
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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09867518
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Filing Dt:
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05/31/2001
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD FOR REMOVING POLYSILANE FROM A SEMICONDUCTOR WITHOUT STRIPPING
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09871855
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Filing Dt:
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05/31/2001
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Title:
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DELIVERING A FINE DELAY STAGE FOR A DELAY LOCKED LOOP
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Patent #:
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Issue Dt:
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07/15/2003
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Application #:
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09885759
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Filing Dt:
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06/20/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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CURRENT SOURCE AND DRAIN ARRANGEMENT FOR MAGNETORESISTIVE MEMORIES (MRAMS)
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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09888193
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD FOR FORMING A SINGLE WIRING LEVEL FOR TRANSISTORS WITH PLANAR AND VERTICAL GATES ON THE SAME SUBSTRATE
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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09891837
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD AND APPARATUS FOR COLLECTING AND DISPLAYING BIT-FAIL-MAP INFORMATION
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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09893157
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Filing Dt:
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06/27/2001
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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ETCH SELECTIVITY INVERSION FOR ETCHING ALONG CRYSTALLOGRAPHIC DIRECTIONS IN SILICON
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09900626
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Filing Dt:
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07/06/2001
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Title:
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DRAM REFRESH TIMING ADJUSTMENT DEVICE, SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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09900649
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Filing Dt:
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07/06/2001
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Publication #:
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Pub Dt:
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01/09/2003
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Title:
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MEMORY CELL, MEMORY CELL ARRANGEMENT AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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09904799
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD FOR HIGH ASPECT RATIO GAP FILL USING SEQUENTIAL HDP-CVD
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Patent #:
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Issue Dt:
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12/23/2003
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Application #:
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09905357
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Filing Dt:
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07/13/2001
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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HIGH ASPECT RATIO HIGH DENSITY PLASMA (HDP) OXIDE GAPFILL METHOD IN A LINES AND SPACE PATTERN
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09906886
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Filing Dt:
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07/17/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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PROGRAMMABLE TEST SOCKET
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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09918353
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Filing Dt:
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07/30/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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DELIVERING DATA OPTICALLY TO AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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09918933
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Filing Dt:
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07/30/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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RECORDING TEST INFORMATION TO IDENTIFY MEMORY CELL ERRORS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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09920504
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Filing Dt:
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08/01/2001
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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ELECTROSTATIC DAMAGE (ESD) PROTECTED PHOTOMASK
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Patent #:
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Issue Dt:
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02/17/2004
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Application #:
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09923266
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Filing Dt:
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08/03/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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SELF-ALIGNED CONDUCTIVE LINE FOR CROSS-POINT MAGNETIC MEMORY INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09930690
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Filing Dt:
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08/15/2001
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Publication #:
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Pub Dt:
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02/20/2003
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Title:
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PROCESS FLOW FOR SACRIFICIAL COLLAR SCHEME WITH VERTICAL NITRIDE MASK
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Patent #:
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Issue Dt:
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10/01/2002
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Application #:
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09940761
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Filing Dt:
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08/27/2001
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Title:
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PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLY MASK
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Patent #:
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Issue Dt:
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12/16/2003
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Application #:
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09944796
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Filing Dt:
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08/31/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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PAD- REROUTING FOR INTEGRATED CIRCUIT CHIPS
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Patent #:
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Issue Dt:
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06/18/2002
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Application #:
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09945007
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Filing Dt:
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08/31/2001
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Title:
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BURIED STRAP FORMATION WITHOUT TTO DEPOSITION
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09952839
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Filing Dt:
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09/14/2001
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Title:
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METHOD FOR FORMING STRUCTURES ON A WAFER
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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09965086
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Filing Dt:
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09/27/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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MRAM BIT LINE WORD LINE ARCHITECTURE
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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09965093
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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DIRECT, NON-DESTRUCTIVE MEASUREMENT OF RECESS DEPTH IN A WAFER
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Patent #:
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Issue Dt:
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12/27/2005
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Application #:
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09967008
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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MEMORY AND METHOD FOR EMPLOYING A CHECKSUM FOR ADDRESSES OF REPLACED STORAGE ELEMENTS
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Patent #:
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Issue Dt:
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12/03/2002
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Application #:
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09967662
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Filing Dt:
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09/27/2001
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Publication #:
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Pub Dt:
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07/25/2002
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Title:
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SERIAL MRAM DEVICE
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Patent #:
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Issue Dt:
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03/15/2005
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Application #:
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09988183
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Filing Dt:
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11/19/2001
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Publication #:
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Pub Dt:
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05/22/2003
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Title:
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FORMATION OF DUAL WORK FUNCTION GATE ELECTRODE
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10010977
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Filing Dt:
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12/06/2001
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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SYSTEM AND METHOD FOR STORING PARITY INFORMATION IN FUSES
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10032389
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Filing Dt:
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10/26/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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METHOD FOR OBTAINING ELLIPTICAL AND ROUNDED SHAPES USING BEAM SHAPING
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10032876
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Filing Dt:
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10/24/2001
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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GRAPHICAL USER INTERFACE FOR TESTING INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10044136
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Filing Dt:
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01/10/2002
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Publication #:
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Pub Dt:
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07/10/2003
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Title:
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FORMING A STRUCTURE ON A WAFER
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Patent #:
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Issue Dt:
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04/01/2003
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Application #:
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10052201
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Filing Dt:
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01/17/2002
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Title:
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PROCESS FOR IMPLEMENTATION OF A HARDMASK
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10053145
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Filing Dt:
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01/17/2002
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Publication #:
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Pub Dt:
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03/27/2003
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Title:
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SPACER FORMATION IN A DEEP TRENCH MEMORY CELL
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10054452
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Filing Dt:
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11/13/2001
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Publication #:
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Pub Dt:
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05/15/2003
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Title:
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STI LEAKAGE REDUCTION
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10057500
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Filing Dt:
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01/25/2002
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Title:
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GENERATING AN EXECUTABLE FILE
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10074479
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Filing Dt:
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02/11/2002
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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MASK AND METHOD FOR PATTERNING A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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12/02/2003
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Application #:
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10098273
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Filing Dt:
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03/15/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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SEMICONDUCTOR WAFER TESTING SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10122996
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Filing Dt:
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04/12/2002
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Publication #:
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Pub Dt:
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10/16/2003
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Title:
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ETCH PROCESS FOR RECESSING POLYSILICON IN TRENCH STRUCTURES
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Patent #:
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Issue Dt:
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11/11/2003
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10139165
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Filing Dt:
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05/06/2002
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Publication #:
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Pub Dt:
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01/16/2003
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Title:
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METHOD FOR IMPROVING A DOPING PROFILE FOR GAS PHASE DOPING
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02/24/2004
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10156482
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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11/28/2002
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Title:
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SEMICONDUCTOR SUBSTRATE HOLDER FOR CHEMICAL-MECHANICAL POLISHING CONTAINING A MOVABLE PLATE
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Patent #:
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08/24/2004
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10160446
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05/30/2002
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Publication #:
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Pub Dt:
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02/13/2003
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Title:
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PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR MEMORY DEVICE
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Issue Dt:
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06/07/2005
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Application #:
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10163054
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06/05/2002
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Publication #:
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Pub Dt:
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12/05/2002
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Title:
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METHOD FOR CARRYING OUT A RULE-BASED OPTICAL PROXIMITY CORRECTION WITH SIMULTANEOUS SCATTER BAR INSERTION
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11/25/2003
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10166981
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06/11/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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OUTPUT DRIVERS FOR IC
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10167785
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Filing Dt:
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06/12/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD FOR PRODUCING AND/OR RENEWING AN ETCHING MASK
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10178252
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Filing Dt:
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06/24/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD AND SYSTEM FOR BIDIRECTIONAL SIGNAL TRANSMISSION
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10185281
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Filing Dt:
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06/27/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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METHOD FOR PRODUCING A PHASE SHIFT MASK
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10185628
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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INTEGRATED DYNAMIC MEMORY AND METHOD FOR OPERATING IT
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10186113
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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EXPOSURE MASK WITH REPAIRED DUMMY STRUCTURE AND METHOD OF REPAIRING AN EXPOSURE MASK
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10186596
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07/01/2002
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01/23/2003
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Title:
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10/21/2003
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10186650
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07/01/2002
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01/02/2003
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Title:
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METHOD AND INPUT CIRCUIT FOR EVALUATING A DATA SIGNAL AT AN INPUT OF A MEMORY COMPONENT
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08/03/2004
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10186660
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07/01/2002
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05/01/2003
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Title:
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NEGATIVE RESIST PROCESS WITH SIMULTANEOUS DEVELOPMENT AND SILYLATION
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01/13/2004
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10186728
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07/01/2002
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01/02/2003
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Title:
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INTEGRATED CIRCUIT FOR RECEIVING A CLOCK SIGNAL, PARTICULARLY FOR A SEMICONDUCTOR MEMORY CIRCUIT
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02/03/2004
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10191855
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07/10/2002
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01/16/2003
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Title:
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SEMICONDUCTOR MEMORY HAVING A PLURALITY OF MEMORY-CELL ARRAYS
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09/21/2004
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10193730
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07/11/2002
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02/13/2003
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Title:
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LAYERING NITRIDED OXIDE ON A SILICON SUBSTRATE
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03/08/2005
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10195958
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07/16/2002
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03/20/2003
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Title:
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ELECTRONIC INTERFACE STRUCTURES AND METHODS
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01/16/2007
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10196338
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07/16/2002
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02/06/2003
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Title:
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SYSTEM FOR TESTING AN INTEGRATED CIRCUIT USING MULTIPLE TEST MODES
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05/18/2004
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10196566
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07/16/2002
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02/13/2003
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ACTIVATING A CONTROL SIGNAL
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08/09/2005
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10196676
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07/16/2002
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03/13/2003
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Title:
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TRANSMISSION AND RECEPTION INTERFACE AND METHOD OF DATA TRANSMISSION
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09/28/2004
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10196698
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07/16/2002
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01/16/2003
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PROCESS FOR DEPOSITING WSIX LAYERS ON A HIGH TOPOGRAPHY WITH A DEFINED STOICHIOMETRY
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03/30/2004
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10198191
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07/17/2002
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02/20/2003
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Title:
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OUTPUT DRIVER DEVICES
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12/28/2004
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10199193
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07/19/2002
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02/20/2003
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Title:
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METHOD FOR PRODUCING A PHOTOMASK AND CORRESPONDING PHOTOMASK
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05/09/2006
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10199640
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07/19/2002
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05/01/2003
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Title:
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PHOTORESIST BASED ON POLYCONDENSATES AND HAVING AN INCREASED RESOLUTION FOR USE IN 157 NANOMETER LITHOGRAPHY
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08/29/2006
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10200632
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07/22/2002
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02/06/2003
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Title:
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ADJUSTMENT CIRCUIT AND METHOD FOR TUNING OF A CLOCK SIGNAL
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09/21/2004
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10200707
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07/22/2002
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01/23/2003
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METHOD FOR FABRICATING SELF-ALIGNING MASK LAYERS
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04/27/2004
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10202690
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07/24/2002
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01/30/2003
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METHOD FOR ON-CHIP TESTING OF MEMORY CELLS OF AN INTEGRATED MEMORY CIRCUIT
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09/26/2006
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10202914
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07/24/2002
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01/30/2003
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CIRCUIT MODULE WITH HIGH-FREQUENCY INPUT/OUTPUT INTERFACES
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07/04/2006
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10205552
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07/25/2002
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01/30/2003
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PHOTOLITHOGRAPHIC MASK
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08/10/2004
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10206303
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07/26/2002
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01/30/2003
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Title:
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METHOD FOR FABRICATING A METAL CARBIDE LAYER AND METHOD FOR FABRICATING A TRENCH CAPACITOR CONTAINING A METAL CARBIDE
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04/13/2004
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10206305
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07/26/2002
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04/17/2003
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Title:
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METHOD FOR MANUFACTURING AN INTEGRATED MEMORY CIRCUIT AND AN INTEGRATED MEMORY CIRCUIT
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05/02/2006
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10206785
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07/26/2002
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03/20/2003
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Title:
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METHOD FOR TESTING A CIRCUIT UNIT TO BE TESTED AND TEST APPARATUS
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10/19/2004
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10208326
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07/30/2002
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05/22/2003
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Title:
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CHEMICALLY AMPLIFIED PHOTORESIST AND PROCESS FOR STRUCTURING SUBSTITUENTS USING TRANSPARENCY ENHANCEMENT OF RESIST COPOLYMERS FOR 157 NM PHOTOLITHOGRAPHY THROUGH THE USE OF FLUORINATED CINNAMIC ACID DERIVATIVES
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07/06/2004
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10208350
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07/30/2002
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02/13/2003
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TEST APPARATUS FOR TESTING DEVICES UNDER TEST AND METHOD FOR TRANSMITTING A TEST SIGNAL
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05/30/2006
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10208351
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07/30/2002
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06/12/2003
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SILICON-CONTAINING RESIST FOR PHOTOLITHOGRAPHY
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05/30/2006
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10208397
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07/30/2002
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08/07/2003
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USE OF POLYBENZOXAZOLES (PBOS) FOR ADHESION
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11/18/2003
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10208415
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07/29/2002
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02/13/2003
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METHOD FOR DETERMINING THE RELEVANT ION AND PARTICLE FLOWS IN I-PVD PROCESSES
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09/07/2004
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10208422
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07/30/2002
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08/14/2003
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ADHESIVELY BONDED CHIP-AND WAFER STACKS
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04/06/2004
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10208444
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07/29/2002
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01/30/2003
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METHOD FOR DATA COMMUNICATION BETWEEN A PLURALITY OF SEMICONDUCTOR MODULES AND A CONTROLLER MODULE AND SEMICONDUCTOR MODULE CONFIGURED FOR THAT PURPOSE
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04/27/2004
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10208445
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07/29/2002
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02/20/2003
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METHOD AND CIRCUIT CONFIGURATION FOR GENERATING A DATA STROBE SIGNAL FOR VERY FAST SEMICONDUCTOR MEMORY SYSTEMS
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02/15/2005
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10210014
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07/31/2002
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02/06/2003
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VALVE FOR A SLURRY OUTLET OPENING OF A CHEMICAL MECHANICAL POLISHING DEVICE AND CHEMICAL MECHANICAL POLISHING DEVICE HAVING A VALVE
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06/21/2005
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10210015
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07/31/2002
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04/24/2003
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METHOD AND CONFIGURATION FOR THE OUTPUT OF BIT ERROR TABLES FROM SEMICONDUCTOR DEVICES
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06/26/2007
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10210218
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08/01/2002
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02/06/2003
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PROTECTIVE DEVICE FOR SUBASSEMBLIES AND METHOD FOR PRODUCING A PROTECTIVE DEVICE
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06/07/2005
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10210602
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08/01/2002
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02/06/2003
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COVERING ELEMENT FOR SUBASSEMBLIES
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03/16/2004
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10210628
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07/31/2002
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02/06/2003
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FUSE PROGRAMMABLE I/O ORGANIZATION
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04/20/2004
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10210665
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08/01/2002
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02/06/2003
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METHOD AND INTEGRATED CIRCUIT FOR BOOSTING A VOLTAGE
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08/09/2005
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10210666
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08/01/2002
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02/06/2003
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PROTECTIVE DEVICE WITH SPACER FOR SUBASSEMBLIES
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08/29/2006
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10210741
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07/31/2002
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02/06/2003
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MEMORY CIRCUIT WITH AN OPTICAL INPUT
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05/09/2006
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10215228
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08/08/2002
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02/13/2003
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METHOD AND APPARATUS FOR SYNCHRONOUS SIGNAL TRANSMISSION BETWEEN AT LEAST TWO LOGIC OR MEMORY COMPONENTS
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07/27/2004
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10217184
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08/12/2002
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02/13/2003
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TRANSISTOR CONFIGURATION FOR A BANDGAP CIRCUIT
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05/17/2005
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10219828
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08/15/2002
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05/15/2003
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SHARING OF MULTIPLE-ACCESS SIGNAL LINE IN A PRINTED CIRCUIT BOARD
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06/15/2004
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10223649
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08/19/2002
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02/20/2003
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PROCESS FOR PRODUCING CONTACT HOLES ON A METALLIZATION STRUCTURE
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08/31/2004
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10224619
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08/20/2002
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02/20/2003
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WAFER HANDLING DEVICE
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03/28/2006
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10225592
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08/22/2002
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Pub Dt:
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02/27/2003
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Title:
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METHOD FOR TESTING MEMORY UNITS TO BE TESTED AND TEST DEVICE
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