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Patent #:
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Issue Dt:
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02/25/2003
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Application #:
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09439253
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Filing Dt:
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11/12/1999
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Title:
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METHODS AND APPARATUS FOR REORDERING OF THE MEMORY REQUESTS TO ACHIEVE HIGHER AVERAGE UTILIZATION OF THE COMMAND AND DATA BUS
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Patent #:
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Issue Dt:
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04/23/2002
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Application #:
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09439254
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Filing Dt:
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11/12/1999
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Title:
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UNIVERSAL MEMORY CONTROLLER
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09439276
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Filing Dt:
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11/12/1999
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Title:
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METHODS AND APPARATUS FOR DETECTING THE COLLISION OF DATA ON A DATA BUS IN CASE OF OUT-OF-ORDER MEMORY ACCESSES OF DIFFERENT TIMES OF MEMORY ACCESS EXECUTION
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09439715
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Filing Dt:
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11/12/1999
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Title:
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METHOD OF SPEEDING UP ACCESS TO A MEMORY PAGE USING A NUMBER OF M PAGE TAG REGISTERS TO TRACK A STATE OF PHYSICAL PAGES IN A MEMORY DEVICE HAVING N MEMORY BANKS WHERE N IS GREATER THAN M
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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09439867
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Filing Dt:
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11/12/1999
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Title:
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METHODS AND APPARATUS FOR PREDICTION OF THE TIME BETWEEN TWO CONSECUTIVE MEMORY ACCESSES
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Patent #:
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Issue Dt:
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07/01/2003
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Application #:
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09712993
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Filing Dt:
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11/14/2000
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Title:
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APPARATUS FOR DETECTIND DATA COLLISION ON DATA BUS FOR OUT-OF-ORDER MEMORY ACCESSES WITH ACCESS EXECUTION TIME BASED IN PART ON CHARACTERIZATION DATA SPECIFIC TO MEMORY
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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09907894
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Filing Dt:
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07/17/2001
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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SOLDER-FREE PCB ASSEMBLY
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Patent #:
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Issue Dt:
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07/29/2003
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Application #:
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09910771
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Filing Dt:
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07/24/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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METHOD OF PREPARING BURIED LOCOS COLLAR IN TRENCH DRAMS
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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09931125
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Filing Dt:
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08/16/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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PSEUDO FAIL BIT MAP GENERATION FOR RAMS DURING COMPONENT TEST AND BURN-IN IN A MANUFACTURING ENVIRONMENT
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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09939554
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Filing Dt:
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08/28/2001
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Title:
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PROCESS FLOW FOR TWO-STEP COLLAR IN DRAM PREPARATION
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Patent #:
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Issue Dt:
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01/31/2006
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Application #:
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09964205
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Filing Dt:
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09/26/2001
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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MULTI-LEVEL CONDUCTIVE LINES WITH REDUCED PITCH
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Patent #:
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Issue Dt:
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08/06/2002
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Application #:
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09964209
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Filing Dt:
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09/26/2001
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Title:
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MULTI-LEVEL SIGNAL LINES WITH VERTICAL TWISTS
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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09965092
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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LOW TEMPERATURE SIDEWALL OXIDATION OF W/WN/POLY-GATESTACK
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09966332
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Filing Dt:
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09/28/2001
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Title:
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METHOD OF FORMING A SELF-ALIGNED ANTIFUSE LINK
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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09966506
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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OPTICAL MEASUREMENT OF PLANARIZED FEATURES
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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09966644
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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INTEGRATED SPACER FOR GATE/SOURCE/DRAIN ISOLATION IN A VERTICAL ARRAY STRUCTURE
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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09967176
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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METHOD FOR OVERLAY METROLOGY OF LOW CONTRAST FEATURES
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Patent #:
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Issue Dt:
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10/04/2005
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Application #:
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09967225
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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METHOD FOR FORMING INSIDE NITRIDE SPACER FOR DEEP TRENCH DEVICE DRAM CELL
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09967226
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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METHOD FOR FORMING INSIDE NITRIDE SPACER FOR DEEP TRENCH DEVICE DRAM CELL
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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09967299
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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ALIGNMENT SYSTEM AND METHOD USING BRIGHT SPOT AND BOX STRUCTURE
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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09967318
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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PROCESS FOR CHEMICAL MECHANICAL POLISHING
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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09967795
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Filing Dt:
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09/28/2001
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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TUNGSTEN HARD MASK
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09977004
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Filing Dt:
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10/12/2001
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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VERTICAL/HORIZONTAL MIMCAP METHOD
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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09977027
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Filing Dt:
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10/12/2001
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Publication #:
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Pub Dt:
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04/17/2003
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Title:
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PLATE-THROUGH HARD MASK FOR MRAM DEVICES
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Patent #:
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Issue Dt:
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12/21/2004
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Application #:
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10002396
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Filing Dt:
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10/23/2001
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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SIMULTANEOUS BIDIRECTIONAL SIGNAL TRANSMISSION
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10015212
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Filing Dt:
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12/10/2001
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Title:
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METHOD FOR ENABLING ACCESS TO MICRO-SECTIONS OF INTEGRATED CIRCUITS ON A WAFER
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10017036
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Filing Dt:
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12/14/2001
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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SELF-TERMINATING BLOW PROCESS OF ELECTRICAL ANTI-FUSES
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10022654
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Filing Dt:
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12/18/2001
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Publication #:
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Pub Dt:
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06/19/2003
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Title:
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MEMORY CELL WITH TRENCH TRANSISTOR
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10026347
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Filing Dt:
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12/20/2001
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Publication #:
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Pub Dt:
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06/26/2003
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Title:
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METHOD OF FORMING AN ALIGNMENT MARK STRUCTURE USING STANDARD PROCESS STEPS FOR FORMING VERTICAL GATE TRANSISTORS
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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10032040
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Filing Dt:
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12/31/2001
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Publication #:
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Pub Dt:
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07/03/2003
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Title:
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HIGH ASPECT RATIO PBL SIN BARRIER FORMATION
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Patent #:
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Issue Dt:
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05/06/2003
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Application #:
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10032041
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Filing Dt:
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12/31/2001
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Title:
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ROUGH OXIDE HARD MASK FOR DT SURFACE AREA ENHANCEMENT FOR DT DRAM
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10032941
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Filing Dt:
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10/31/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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COMPLIANT RELIEF WAFER LEVEL PACKAGING
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10034625
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Filing Dt:
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12/27/2001
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Publication #:
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Pub Dt:
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07/17/2003
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Title:
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TWISTED BIT-LINE COMPENSATION
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Patent #:
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Issue Dt:
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04/08/2003
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Application #:
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10041779
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Filing Dt:
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10/19/2001
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Publication #:
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Pub Dt:
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04/24/2003
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Title:
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PROCESS FLOW FOR SACRIFICIAL COLLAR WITH POLYSILICON VOID
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10044000
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Filing Dt:
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10/31/2001
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Publication #:
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Pub Dt:
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05/01/2003
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Title:
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TRANSFER WAFER LEVEL PACKAGING
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10050737
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Filing Dt:
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01/16/2002
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Publication #:
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Pub Dt:
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07/17/2003
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Title:
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METHOD FOR MONITORING THE RATE OF ETCHING OF A SEMICONDUCTOR
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10051544
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Filing Dt:
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01/18/2002
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Publication #:
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Pub Dt:
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07/24/2003
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Title:
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SYSTEM AND METHOD FOR BACK-SIDE CONTACT FOR TRENCH SEMICONDUCTOR DEVICE CHARACTERIZATION
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10057065
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Filing Dt:
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01/25/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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METHOD FOR ACHIEVING HIGH SELF-ALIGNING VERTICAL GATE STUDS RELATIVE TO THE SUPPORT ISOLATION LEVEL
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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10062755
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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06/13/2002
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10062942
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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07/31/2003
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Title:
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METHOD OF APPLYING A BOTTOM SURFACE PROTECTIVE COATING TO A WAFER, AND WAFER DICING METHOD
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Patent #:
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Issue Dt:
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08/26/2003
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Application #:
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10065166
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Filing Dt:
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09/24/2002
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Title:
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CONTACT FOR MEMORY CELLS
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10065168
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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SENSING OF MEMORY INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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10/19/2004
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Application #:
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10065920
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Filing Dt:
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11/29/2002
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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METHOD OF RELIABILITY TESTING
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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10066184
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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10066206
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Filing Dt:
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01/31/2002
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10067587
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Filing Dt:
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02/04/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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POLYELECTROLYTE DISPENSING POLISHING PAD, PRODUCTION THEREOF AND METHOD OF POLISHING A SUBSTRATE
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Patent #:
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Issue Dt:
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12/24/2002
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Application #:
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10068913
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Filing Dt:
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02/08/2002
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Title:
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MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CROSS-POINT ARRAY WITH REDUCED PARASITIC EFFECTS
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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10077518
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Filing Dt:
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02/15/2002
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Title:
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DUAL GATE OXIDE PROCESS WITHOUT CRITICAL RESIST AND WITHOUT N2 IMPLANT
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Patent #:
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Issue Dt:
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09/13/2005
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Application #:
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10084194
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Filing Dt:
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02/28/2002
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Publication #:
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Pub Dt:
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12/09/2004
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Title:
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INTEGRATION SCHEME FOR METAL GAP FILL, WITH FIXED ABRASIVE CMP
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Patent #:
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Issue Dt:
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09/30/2003
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Application #:
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10093722
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Filing Dt:
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03/08/2002
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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MEMORY CELL FABRICATION METHOD AND MEMORY CELL CONFIGURATION
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10098840
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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METHOD OF ELIMINATING BACK-END REROUTING IN BALL GRID ARRAY PACKAGING
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10103278
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Filing Dt:
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03/21/2002
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Publication #:
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Pub Dt:
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04/22/2004
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Title:
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INCREASING THE READ SIGNAL IN FERROELECTRIC MEMORIES
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Patent #:
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Issue Dt:
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01/24/2006
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Application #:
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10108359
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Filing Dt:
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03/29/2002
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Publication #:
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Pub Dt:
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10/02/2003
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Title:
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PRODUCING LOW K INTER-LAYER DIELECTRIC FILMS USING SI-CONTAINING RESISTS
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10114484
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Filing Dt:
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04/03/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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ELIMINATION OF RESIST FOOTING ON TERA HARDMASK
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Patent #:
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Issue Dt:
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11/09/2004
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Application #:
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10124950
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Filing Dt:
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04/18/2002
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Publication #:
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Pub Dt:
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10/23/2003
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Title:
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MATERIAL COMBINATIONS FOR TUNNEL JUNCTION CAP LAYER, TUNNEL JUNCTION HARD MASK AND TUNNEL JUNCTION STACK SEED LAYER IN MRAM PROCESSING
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10137142
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Filing Dt:
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05/02/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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METHOD FOR SEMICONDUCTOR YIELD LOSS CALCULATION
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Patent #:
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Issue Dt:
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03/25/2003
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Application #:
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10142537
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Filing Dt:
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05/09/2002
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Title:
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TRANSISTOR AND METHOD OF MANUFACTURING A TRANSISTOR HAVING A SHALLOW JUNCTION FORMATION USING A TWO STEP EPI LAYER
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10144572
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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USE OF AN ON-DIE TEMPERATURE SENSING SCHEME FOR THERMAL PROTECTION OF DRAMS
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10144579
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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USE OF DQ PINS ON A RAM MEMORY CHIP FOR A TEMPERATURE SENSING PROTOCOL
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10144597
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Filing Dt:
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05/13/2002
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Publication #:
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Pub Dt:
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11/13/2003
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Title:
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IMPLEMENTATION OF A TEMPERATURE SENSOR TO CONTROL INTERNAL CHIP VOLTAGES
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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10158982
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Filing Dt:
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05/30/2002
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Title:
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ISOLATING A VERTICAL GATE CONTACT STRUCTURE
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Patent #:
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Issue Dt:
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05/10/2005
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Application #:
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10166837
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
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12/11/2003
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Title:
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AUTO-ADJUSTMENT OF SELF-REFRESH FREQUENCY
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Patent #:
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Issue Dt:
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12/28/2004
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Application #:
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10184127
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Filing Dt:
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06/28/2002
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Publication #:
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Pub Dt:
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01/01/2004
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Title:
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HARDMASK OF AMORPHOUS CARBON-HYDROGEN (A-C:H) LAYERS WITH TUNABLE ETCH RESISTIVITY
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Patent #:
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Issue Dt:
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08/12/2003
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Application #:
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10186043
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Filing Dt:
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06/28/2002
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Title:
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METHOD OF MANUFACTURING CIRCUIT WITH BURIED STRAP INCLUDING A LINER
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Patent #:
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Issue Dt:
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06/17/2003
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Application #:
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10186656
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Filing Dt:
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07/01/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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METHOD AND INSTALLATION FOR FABRICATING ONE-SIDED BURIED STRAPS
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10188532
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Filing Dt:
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07/03/2002
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Publication #:
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Pub Dt:
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01/08/2004
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Title:
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LITHOGRAPHY METHOD FOR PREVENTING LITHOGRAPHIC EXPOSURE OF PERIPHERAL REGION OF SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10196834
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Filing Dt:
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07/17/2002
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Publication #:
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Pub Dt:
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01/23/2003
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Title:
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MEASURING CONFIGURATION AND METHOD FOR MEASURING A CRITICAL DIMENSION OF AT LEAST ONE FEATURE ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10208465
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Filing Dt:
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07/29/2002
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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METHOD FOR CHARACTERIZING THE PLANARIZING PROPERTIES OF AN EXPENDABLE MATERIAL COMBINATION IN A CHEMICAL-MECHANICAL POLISHING PROCESS; SIMULATION TECHNIQUE; AND POLISHING TECHNIQUE
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10209025
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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COOLING HOOD FOR CIRCUIT BOARD
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10210132
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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MASKLESS MIDDLE-OF-LINE LINER DEPOSITION
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10210645
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Filing Dt:
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07/31/2002
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Title:
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TUNABLE ANALOG TO DIGITAL CONVERTER
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10213413
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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PROCESS FOR STRUCTURING A PHOTORESIST LAYER ON A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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02/13/2007
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Application #:
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10216012
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Filing Dt:
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08/09/2002
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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CONTINUOUS SELF-CALIBRATION OF INTERNAL ANALOG SIGNALS
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10218449
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Filing Dt:
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08/13/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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ATOMIC FORCE MICROSCOPY SCANNING METHODS
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10222693
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Filing Dt:
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08/16/2002
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Publication #:
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Pub Dt:
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02/19/2004
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Title:
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LEADLESS SOCKET FOR DECAPPED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10226697
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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SPARE INPUT/OUTPUT BUFFER
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10234864
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Filing Dt:
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09/04/2002
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Publication #:
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Pub Dt:
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03/04/2004
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Title:
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MRAM MTJ STACK TO CONDUCTIVE LINE ALIGNMENT METHOD
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Patent #:
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Issue Dt:
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05/16/2006
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Application #:
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10236448
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Filing Dt:
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09/06/2002
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Publication #:
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Pub Dt:
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03/11/2004
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Title:
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OPTICAL MEASUREMENT SYSTEM AND METHOD
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10242894
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Filing Dt:
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09/12/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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SEMICONDUCTOR WAFER TESTING SYSTEM
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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10243544
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Filing Dt:
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09/12/2002
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Publication #:
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Pub Dt:
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03/18/2004
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Title:
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SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10245622
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Filing Dt:
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09/17/2002
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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METHOD AND APPARATUS FOR REDUCING THE CURRENT CONSUMPTION OF AN ELECTRONIC CIRCUIT
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10248232
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Filing Dt:
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12/30/2002
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Publication #:
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Pub Dt:
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07/01/2004
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Title:
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PATTERN TRANSFER IN DEVICE FABRICATION
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Patent #:
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Issue Dt:
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11/23/2004
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Application #:
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10248233
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Filing Dt:
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12/30/2002
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Publication #:
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Pub Dt:
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07/01/2004
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Title:
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IMPROVED DEEP ISOLATION TRENCHES
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Patent #:
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Issue Dt:
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02/08/2005
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Application #:
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10248801
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Filing Dt:
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02/20/2003
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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TRENCH CAPACITOR WITH BURIED STRAP
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10248861
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Filing Dt:
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02/25/2003
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Publication #:
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Pub Dt:
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08/26/2004
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Title:
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FERROELECTRIC MEMORY INTEGRATED CIRCUIT WITH IMPROVED RELIABILITY
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10248874
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Filing Dt:
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02/26/2003
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Publication #:
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Pub Dt:
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08/28/2003
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Title:
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CONTROL CIRCUIT FOR AN S-DRAM
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Patent #:
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Issue Dt:
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03/29/2005
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Application #:
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10248985
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Filing Dt:
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03/06/2003
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Publication #:
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Pub Dt:
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09/09/2004
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Title:
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NONVOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
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11/16/2004
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Application #:
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10249029
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Filing Dt:
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03/11/2003
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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LATENCY TIME CIRCUIT FOR AN S-DRAM
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Patent #:
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Issue Dt:
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01/25/2005
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Application #:
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10249531
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Filing Dt:
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04/17/2003
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Publication #:
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Pub Dt:
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10/21/2004
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Title:
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LOW SWITCHING FIELD MAGNETIC ELEMENT
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10249532
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Filing Dt:
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04/17/2003
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Title:
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MAGNETIC MEMORY
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10252331
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Filing Dt:
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09/23/2002
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Title:
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DELAY LOCKED LOOP COMPENSATING FOR EFFECTIVE LOADS OF OFF-CHIP DRIVERS AND METHODS FOR LOCKING A DELAY LOOP
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Patent #:
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Issue Dt:
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06/07/2005
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Application #:
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10252995
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Filing Dt:
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09/23/2002
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Publication #:
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Pub Dt:
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04/03/2003
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Title:
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DIGITAL MAGNETIC MEMORY CELL DEVICE
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10254467
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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SYSTEM AND METHOD FOR ENABLING A VENDOR MODE ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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10/20/2009
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Application #:
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10254470
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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FLUORESCENT NAPHTHALENE -1,4,5,8-TETRACARBOXYLIC BISIMIDES WITH AN ELECTRON-DONATING SUBSTITUENT ON THE NUCLEUS
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Patent #:
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Issue Dt:
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01/18/2005
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Application #:
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10255767
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Filing Dt:
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09/25/2002
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Publication #:
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Pub Dt:
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03/25/2004
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Title:
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SYSTEM AND METHOD FOR MONITORING INTERNAL VOLTAGES ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/11/2006
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Application #:
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10256463
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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METHOD OF SELF-REPAIRING DYNAMIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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03/23/2004
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Application #:
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10256539
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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INDICATION OF THE SYSTEM OPERATION FREQUENCY TO A DRAM DURING POWER-UP
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Patent #:
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Issue Dt:
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08/09/2005
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Application #:
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10259100
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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BITLINE EQUALIZATION SYSTEM FOR A DRAM INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10260919
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Filing Dt:
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09/30/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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ON-DIE DETECTION OF THE SYSTEM OPERATION FREQUENCY IN A DRAM TO ADJUST DRAM OPERATIONS
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Patent #:
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Issue Dt:
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03/09/2004
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Application #:
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10266187
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Filing Dt:
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10/07/2002
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Publication #:
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Pub Dt:
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05/01/2003
| | | | |
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Title:
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APPARATUS FOR GENERATING MEMORY-INTERNAL COMMAND SIGNALS FROM A MEMORY OPERATION COMMAND
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