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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	036818/0583			Pages:	14
		Recorded:	10/08/2015
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 250
Page 3 of 3
Pages: 1 2 3

Patent #:	6989707	Issue Dt:	01/24/2006	Application #:	10419596	Filing Dt:	04/21/2003
Publication #:	US20030197545	Pub Dt:	10/23/2003
Title:	SEMICONDUCTOR CIRCUIT AND INITIALIZATION METHOD

Patent #:	7277839	Issue Dt:	10/02/2007	Application #:	10422580	Filing Dt:	04/24/2003
Publication #:	US20030204389	Pub Dt:	10/30/2003
Title:	METHOD FOR NUMERICALLY SIMULATING AN ELECTRICAL CIRCUIT

Patent #:	7018748	Issue Dt:	03/28/2006	Application #:	10425233	Filing Dt:	04/29/2003
Publication #:	US20030203314	Pub Dt:	10/30/2003
Title:	PROCESS FOR PRODUCING HARD MASKS

Patent #:	6822923	Issue Dt:	11/23/2004	Application #:	10425280	Filing Dt:	04/29/2003
Publication #:	US20040008548	Pub Dt:	01/15/2004
Title:	RAM MEMORY CIRCUIT AND METHOD FOR CONTROLLING THE SAME

Patent #:	6867442	Issue Dt:	03/15/2005	Application #:	10425460	Filing Dt:	04/29/2003
Publication #:	US20030227116	Pub Dt:	12/11/2003
Title:	SURFACE-FUNCTIONALIZED INORGANIC SEMICONDUCTOR PARTICLES AS ELECTRICAL SEMICONDUCTORS FOR MICROELECTRONICS APPLICATIONS

Patent #:	6833745	Issue Dt:	12/21/2004	Application #:	10426011	Filing Dt:	04/29/2003
Publication #:	US20040051579	Pub Dt:	03/18/2004
Title:	SIGNAL GENERATOR FOR CHARGE PUMP IN AN INTEGRATED CIRCUIT

Patent #:	6870420	Issue Dt:	03/22/2005	Application #:	10429577	Filing Dt:	05/05/2003
Publication #:	US20030230758	Pub Dt:	12/18/2003
Title:	METHOD OF INCREASING AN INTERNAL OPERATING VOLTAGE FOR AN INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT

Patent #:	7278072	Issue Dt:	10/02/2007	Application #:	10429579	Filing Dt:	05/05/2003
Publication #:	US20030217313	Pub Dt:	11/20/2003
Title:	METHOD AND AUXILIARY DEVICE FOR TESTING A RAM MEMORY CIRCUIT

Patent #:	6868018	Issue Dt:	03/15/2005	Application #:	10431422	Filing Dt:	05/07/2003
Publication #:	US20030210592	Pub Dt:	11/13/2003
Title:	MEMORY CIRCUIT, METHOD FOR MANUFACTURING AND METHOD FOR OPERATING THE SAME

Patent #:	6884676	Issue Dt:	04/26/2005	Application #:	10447065	Filing Dt:	05/28/2003
Publication #:	US20040238868	Pub Dt:	12/02/2004
Title:	VERTICAL 8F2 CELL DRAM WITH ACTIVE AREA SELF-ALIGNED TO BIT LINE

Patent #:	7428671	Issue Dt:	09/23/2008	Application #:	10452482	Filing Dt:	06/02/2003
Publication #:	US20040153922	Pub Dt:	08/05/2004
Title:	MEMORY MODULE WITH TEST STRUCTURE

Patent #:	6981241	Issue Dt:	12/27/2005	Application #:	10455764	Filing Dt:	06/05/2003
Publication #:	US20030229882	Pub Dt:	12/11/2003
Title:	METHOD FOR ELIMINATING PHASE CONFLICT CENTERS IN ALTERNATING PHASE MASKS, AND METHOD FOR PRODUCING ALTERNATING PHASE MASKS

Patent #:	6930540	Issue Dt:	08/16/2005	Application #:	10460714	Filing Dt:	06/12/2003
Publication #:	US20030231049	Pub Dt:	12/18/2003
Title:	INTEGRATED CIRCUIT WITH VOLTAGE DIVIDER AND BUFFERED CAPACITOR

Patent #:	7439186	Issue Dt:	10/21/2008	Application #:	10463565	Filing Dt:	06/16/2003
Publication #:	US20040005778	Pub Dt:	01/08/2004
Title:	METHOD FOR STRUCTURING A SILICON LAYER

Patent #:	7005220	Issue Dt:	02/28/2006	Application #:	10465103	Filing Dt:	06/19/2003
Publication #:	US20040013952	Pub Dt:	01/22/2004
Title:	METHOD FOR STRUCTURING A LITHOGRAPHY MASK

Patent #:	7075814	Issue Dt:	07/11/2006	Application #:	10495301	Filing Dt:	12/15/2004
Publication #:	US20050105355	Pub Dt:	05/19/2005
Title:	METHOD AND APPARATUS FOR HOMOGENEOUSLY MAGNETIZING AN EXCHANGE-COUPLED LAYER SYSTEM OF A DIGITAL MAGNETIC MEMORY CELL DEVICE

Patent #:	7413971	Issue Dt:	08/19/2008	Application #:	10498421	Filing Dt:	01/31/2005
Publication #:	US20050196950	Pub Dt:	09/08/2005
Title:	METHOD OF PRODUCING A LAYERED ARRANGEMENT AND LAYERED ARRANGEMENT

Patent #:	7261829	Issue Dt:	08/28/2007	Application #:	10501464	Filing Dt:	04/08/2005
Publication #:	US20050224451	Pub Dt:	10/13/2005
Title:	METHOD FOR MASKING A RECESS IN A STRUCTURE HAVING A HIGH ASPECT RATIO

Patent #:	7034383	Issue Dt:	04/25/2006	Application #:	10501599	Filing Dt:	12/22/2004
Publication #:	US20050087889	Pub Dt:	04/28/2005
Title:	ELECTRONIC COMPONENT AND PANEL AND METHOD FOR PRODUCING THE SAME

Patent #:	7318307	Issue Dt:	01/15/2008	Application #:	10507935	Filing Dt:	07/18/2005
Publication #:	US20060011508	Pub Dt:	01/19/2006
Title:	METHOD AND DEVICE FOR PACKAGING AND TRANSPORTING ELECTRONIC COMPONENTS

Patent #:	7709827	Issue Dt:	05/04/2010	Application #:	10533550	Filing Dt:	11/17/2005
Publication #:	US20060128088	Pub Dt:	06/15/2006
Title:	VERTICALLY INTEGRATED FIELD-EFFECT TRANSISTOR HAVING A NANOSTRUCTURE THEREIN

Patent #:	6933768	Issue Dt:	08/23/2005	Application #:	10600961	Filing Dt:	06/20/2003
Publication #:	US20050077949	Pub Dt:	04/14/2005
Title:	METHOD FOR INCREASING THE INPUT VOLTAGE OF AN INTEGRATED CIRCUIT WITH A TWO-STAGE CHARGE PUMP, AND INTEGRATED CIRCUIT

Patent #:	6819627	Issue Dt:	11/16/2004	Application #:	10602403	Filing Dt:	06/23/2003
Publication #:	US20040049485	Pub Dt:	03/11/2004
Title:	METHOD FOR STORING DATA, METHOD FOR READING DATA, APPARATUS FOR STORING DATA AND APPARATUS FOR READING DATA

Patent #:	7159156	Issue Dt:	01/02/2007	Application #:	10610186	Filing Dt:	06/30/2003
Publication #:	US20040001375	Pub Dt:	01/01/2004
Title:	MEMORY CHIP WITH TEST LOGIC TAKING INTO CONSIDERATION THE ADDRESS OF A REDUNDANT WORD LINE AND METHOD FOR TESTING A MEMORY CHIP

Patent #:	7034358	Issue Dt:	04/25/2006	Application #:	10615567	Filing Dt:	07/08/2003
Publication #:	US20040005762	Pub Dt:	01/08/2004
Title:	VERTICAL TRANSISTOR, AND A METHOD FOR PRODUCING A VERTICAL TRANSISTOR

Patent #:	7088624	Issue Dt:	08/08/2006	Application #:	10623078	Filing Dt:	07/18/2003
Publication #:	US20050013174	Pub Dt:	01/20/2005
Title:	SYSTEM OF MULTIPLEXED DATA LINES IN A DYNAMIC RANDOM ACCESS MEMORY

Patent #:	7074696	Issue Dt:	07/11/2006	Application #:	10630632	Filing Dt:	07/29/2003
Title:	SEMICONDUCTOR CIRCUIT MODULE AND METHOD FOR FABRICATING SEMICONDUCTOR CIRCUIT MODULES

Patent #:	7292046	Issue Dt:	11/06/2007	Application #:	10654342	Filing Dt:	09/03/2003
Publication #:	US20050046426	Pub Dt:	03/03/2005
Title:	SIMULATED MODULE LOAD

Patent #:	7073969	Issue Dt:	07/11/2006	Application #:	10736775	Filing Dt:	12/17/2003
Publication #:	US20040198047	Pub Dt:	10/07/2004
Title:	METHOD FOR FABRICATING A PHOTOMASK FOR AN INTEGRATED CIRCUIT AND CORRESPONDING PHOTOMASK

Patent #:	6825096	Issue Dt:	11/30/2004	Application #:	10762973	Filing Dt:	01/22/2004
Publication #:	US20040152270	Pub Dt:	08/05/2004
Title:	METHOD OF FORMING AN ALIGNMENT MARK STRUCTURE USING STANDARD PROCESS STEPS FOR FORMING VERTICAL GATE TRANSISTORS

Patent #:	7212019	Issue Dt:	05/01/2007	Application #:	10826954	Filing Dt:	04/15/2004
Publication #:	US20040239921	Pub Dt:	12/02/2004
Title:	PROBE NEEDLE FOR TESTING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SAID PROBE NEEDLE

Patent #:	6998296	Issue Dt:	02/14/2006	Application #:	10868855	Filing Dt:	06/17/2004
Publication #:	US20040262780	Pub Dt:	12/30/2004
Title:	ELECTRONIC COMPONENT AND METHOD FOR ITS PRODUCTION

Patent #:	7229857	Issue Dt:	06/12/2007	Application #:	10890827	Filing Dt:	07/14/2004
Publication #:	US20050064630	Pub Dt:	03/24/2005
Title:	METHOD FOR PRODUCING A PROTECTION FOR CHIP EDGES AND SYSTEM FOR THE PROTECTION OF CHIP EDGES

Patent #:	6924225	Issue Dt:	08/02/2005	Application #:	10893561	Filing Dt:	07/16/2004
Publication #:	US20050079702	Pub Dt:	04/14/2005
Title:	METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTIVE CONTACT

Patent #:	7034336	Issue Dt:	04/25/2006	Application #:	10911994	Filing Dt:	08/05/2004
Publication #:	US20050064659	Pub Dt:	03/24/2005
Title:	CAPACITORLESS 1-TRANSISTOR DRAM CELL AND FABRICATION METHOD

Patent #:	7129155	Issue Dt:	10/31/2006	Application #:	10916742	Filing Dt:	08/12/2004
Publication #:	US20050026407	Pub Dt:	02/03/2005
Title:	PROCESS FOR PRODUCING A PLURALITY OF GATE STACKS WHICH ARE APPROXIMATELY THE SAME HEIGHT AND EQUIDISTANT ON A SEMICONDUCTOR SUBSTRATE

Patent #:	7385243	Issue Dt:	06/10/2008	Application #:	10926838	Filing Dt:	08/25/2004
Publication #:	US20050048720	Pub Dt:	03/03/2005
Title:	FLOATING GATE MEMORY CELL WITH A METALLIC SOURCE/DRAIN AND GATE, AND METHOD FOR MANUFACTURING SUCH A FLOATING GATE MEMORY GATE CELL

Patent #:	7421667	Issue Dt:	09/02/2008	Application #:	10940382	Filing Dt:	09/14/2004
Publication #:	US20050034085	Pub Dt:	02/10/2005
Title:	SYSTEM AND METHOD FOR ENABLING A VENDOR MODE ON AN INTEGRATED CIRCUIT

Patent #:	7049193	Issue Dt:	05/23/2006	Application #:	10960735	Filing Dt:	10/07/2004
Publication #:	US20050062111	Pub Dt:	03/24/2005
Title:	MASKLESS MIDDLE-OF-LINE LINER DEPOSITION

Patent #:	7176131	Issue Dt:	02/13/2007	Application #:	10960994	Filing Dt:	10/12/2004
Publication #:	US20050110162	Pub Dt:	05/26/2005
Title:	ELECTRONIC COMPONENT HAVING AT LEAST ONE SEMICONDUCTOR CHIP AND FLIP-CHIP CONTACTS, AND METHOD FOR PRODUCING THE SAME

Patent #:	7057206	Issue Dt:	06/06/2006	Application #:	10974774	Filing Dt:	10/28/2004
Publication #:	US20050104060	Pub Dt:	05/19/2005
Title:	SILICON PARTICLES AS ADDITIVES FOR IMPROVING CHARGE CARRIER MOBILITY IN ORGANIC SEMICONDUCTORS

Patent #:	7223639	Issue Dt:	05/29/2007	Application #:	10989650	Filing Dt:	11/16/2004
Publication #:	US20050067721	Pub Dt:	03/31/2005
Title:	METHOD OF PRODUCING AN ELECTRONIC COMPONENT AND A PANEL WITH A PLURALITY OF ELECTRONIC COMPONENTS

Patent #:	7163891	Issue Dt:	01/16/2007	Application #:	11003592	Filing Dt:	12/03/2004
Publication #:	US20050130352	Pub Dt:	06/16/2005
Title:	HIGH DENSITY DRAM WITH REDUCED PERIPHERAL DEVICE AREA AND METHOD OF MANUFACTURE

Patent #:	6993455	Issue Dt:	01/31/2006	Application #:	11029573	Filing Dt:	01/05/2005
Publication #:	US20050148195	Pub Dt:	07/07/2005
Title:	METHOD FOR DETERMINING THE CONSTRUCTION OF A MASK FOR THE MICROPATTERNING OF SEMICONDUCTOR SUBSTRATES BY MEANS OF PHOTOLITHOGRAPHY

Patent #:	6952378	Issue Dt:	10/04/2005	Application #:	11042624	Filing Dt:	01/25/2005
Publication #:	US20050122832	Pub Dt:	06/09/2005
Title:	Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations

Patent #:	7157329	Issue Dt:	01/02/2007	Application #:	11053508	Filing Dt:	02/08/2005
Publication #:	US20050158961	Pub Dt:	07/21/2005
Title:	TRENCH CAPACITOR WITH BURIED STRAP

Patent #:	7341904	Issue Dt:	03/11/2008	Application #:	11367731	Filing Dt:	03/03/2006
Publication #:	US20060177980	Pub Dt:	08/10/2006
Title:	CAPACITORLESS 1-TRANSISTOR DRAM CELL AND FABRICATION METHOD

Patent #:	7242208	Issue Dt:	07/10/2007	Application #:	11386512	Filing Dt:	03/22/2006
Publication #:	US20060158209	Pub Dt:	07/20/2006
Title:	SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER

Patent #:	7643956	Issue Dt:	01/05/2010	Application #:	11649047	Filing Dt:	01/03/2007
Publication #:	US20070110145	Pub Dt:	05/17/2007
Title:	CONTINUOUS SELF-CALIBRATION OF INTERNAL ANALOG SIGNALS

Patent #:	7449909	Issue Dt:	11/11/2008	Application #:	11707408	Filing Dt:	02/16/2007
Publication #:	US20070152700	Pub Dt:	07/05/2007
Title:	SYSTEM AND METHOD FOR TESTING ONE OR MORE DIES ON A SEMICONDUCTOR WAFER

Assignor

INFINEON TECHNOLOGIES AG

Exec Dt:

07/08/2015

Assignee

POLARIS INNOVATIONS LIMITED

29 EARLSFORT TERRACE, DUBLIN 2

DUBLIN, IRELAND

Correspondence name and address
	POLARIS INNOVATIONS LIMITED
	303 TERRY FOX DRIVE, SUITE 300
	OTTAWA, K2K 3J1 CANADA

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