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Reel/Frame:	036873/0758			Pages:	13
		Recorded:	10/15/2015
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 220
Page 1 of 3
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Patent #:	6940111	Issue Dt:	09/06/2005	Application #:	10065922	Filing Dt:	11/29/2002
Publication #:	US20040104754	Pub Dt:	06/03/2004
Title:	RADIATION PROTECTION IN INTEGRATED CIRCUITS

Patent #:	7035753	Issue Dt:	04/25/2006	Application #:	10102145	Filing Dt:	03/20/2002
Publication #:	US20030179010	Pub Dt:	09/25/2003
Title:	METHOD AND APPARATUS FOR PLACING AN INTEGRATED CIRCUIT INTO A DEFAULT MODE OF OPERATION

Patent #:	6954873	Issue Dt:	10/11/2005	Application #:	10115504	Filing Dt:	04/02/2002
Publication #:	US20030088801	Pub Dt:	05/08/2003
Title:	IMPLEMENTATION OF WAIT-STATES

Patent #:	6538939	Issue Dt:	03/25/2003	Application #:	10197991	Filing Dt:	07/18/2002
Publication #:	US20030063510	Pub Dt:	04/03/2003
Title:	MEMORY EMPLOYING MULTIPLE ENABLE/DISABLE MODES FOR REDUNDANT ELEMENTS AND TESTING METHOD USING SAME

Patent #:	6847911	Issue Dt:	01/25/2005	Application #:	10210962	Filing Dt:	08/02/2002
Publication #:	US20040024561	Pub Dt:	02/05/2004
Title:	METHOD AND APPARATUS FOR TEMPERATURE THROTTLING THE ACCESS FREQUENCY OF AN INTEGRATED CIRCUIT

Patent #:	6815234	Issue Dt:	11/09/2004	Application #:	10248253	Filing Dt:	12/31/2002
Publication #:	US20040124452	Pub Dt:	07/01/2004
Title:	REDUCING STRESS IN INTEGRATED CIRCUITS

Patent #:	6897501	Issue Dt:	05/24/2005	Application #:	10248897	Filing Dt:	02/28/2003
Publication #:	US20040169211	Pub Dt:	09/02/2004
Title:	AVOIDING SHORTING IN CAPACITORS

Patent #:	7187602	Issue Dt:	03/06/2007	Application #:	10250211	Filing Dt:	06/13/2003
Publication #:	US20030179616	Pub Dt:	09/25/2003
Title:	REDUCING MEMORY FAILURES IN INTEGRATED CIRCUITS

Patent #:	6919147	Issue Dt:	07/19/2005	Application #:	10254405	Filing Dt:	09/25/2002
Publication #:	US20040058252	Pub Dt:	03/25/2004
Title:	PRODUCTION METHOD FOR A HALFTONE PHASE MASK

Patent #:	6711082	Issue Dt:	03/23/2004	Application #:	10299026	Filing Dt:	11/18/2002
Title:	METHOD AND IMPLEMENTATION OF AN ON-CHIP SELF REFRESH FEATURE

Patent #:	6724676	Issue Dt:	04/20/2004	Application #:	10299037	Filing Dt:	11/18/2002
Title:	SOFT ERROR IMPROVEMENT FOR LATCHES

Patent #:	6826099	Issue Dt:	11/30/2004	Application #:	10301529	Filing Dt:	11/20/2002
Publication #:	US20040095819	Pub Dt:	05/20/2004
Title:	2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE AND DISCHARGE OF BL AND /BL

Patent #:	6731554	Issue Dt:	05/04/2004	Application #:	10301546	Filing Dt:	11/20/2002
Publication #:	US20040095820	Pub Dt:	05/20/2004
Title:	2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT

Patent #:	6876590	Issue Dt:	04/05/2005	Application #:	10301548	Filing Dt:	11/20/2002
Publication #:	US20040095821	Pub Dt:	05/20/2004
Title:	2T2C SIGNAL MARGIN TEST MODE USING A DEFINED CHARGE EXCHANGE BETWEEN BL AND/BL

Patent #:	6794282	Issue Dt:	09/21/2004	Application #:	10305063	Filing Dt:	11/27/2002
Publication #:	US20040102001	Pub Dt:	05/27/2004
Title:	THREE LAYER ALUMINUM DEPOSITION PROCESS FOR HIGH ASPECT RATIO CL CONTACTS

Patent #:	6946735	Issue Dt:	09/20/2005	Application #:	10307257	Filing Dt:	11/29/2002
Publication #:	US20040104471	Pub Dt:	06/03/2004
Title:	SIDE-WALL BARRIER STRUCTURE AND METHOD OF FABRICATION

Patent #:	6709947	Issue Dt:	03/23/2004	Application #:	10314548	Filing Dt:	12/06/2002
Title:	METHOD OF AREA ENHANCEMENT IN CAPACITOR PLATES

Patent #:	6774691	Issue Dt:	08/10/2004	Application #:	10337606	Filing Dt:	01/07/2003
Publication #:	US20040130365	Pub Dt:	07/08/2004
Title:	HIGH RESOLUTION INTERLEAVED DELAY CHAIN

Patent #:	6746877	Issue Dt:	06/08/2004	Application #:	10338798	Filing Dt:	01/07/2003
Title:	ENCAPSULATION OF FERROELECTRIC CAPACITORS

Patent #:	6861872	Issue Dt:	03/01/2005	Application #:	10358581	Filing Dt:	02/05/2003
Publication #:	US20040150423	Pub Dt:	08/05/2004
Title:	VOLTAGE DOWN CONVERTER FOR LOW VOLTAGE OPERATION

Patent #:	7145216	Issue Dt:	12/05/2006	Application #:	10361989	Filing Dt:	02/11/2003
Publication #:	US20040156156	Pub Dt:	08/12/2004
Title:	ANTIFUSE PROGRAMMING WITH RELAXED UPPER CURRENT LIMIT

Patent #:	6946889	Issue Dt:	09/20/2005	Application #:	10364716	Filing Dt:	02/11/2003
Publication #:	US20040160253	Pub Dt:	08/19/2004
Title:	SELF ALIGNMENT SYSTEM FOR COMPLEMENT CLOCKS

Patent #:	6947344	Issue Dt:	09/20/2005	Application #:	10376408	Filing Dt:	02/28/2003
Publication #:	US20040170075	Pub Dt:	09/02/2004
Title:	MEMORY DEVICE AND METHOD OF READING DATA FROM A MEMORY CELL

Patent #:	6914844	Issue Dt:	07/05/2005	Application #:	10378472	Filing Dt:	03/03/2003
Publication #:	US20040174762	Pub Dt:	09/09/2004
Title:	DEEP POWER DOWN SWITCH FOR MEMORY DEVICE

Patent #:	6847092	Issue Dt:	01/25/2005	Application #:	10383191	Filing Dt:	03/06/2003
Publication #:	US20040173868	Pub Dt:	09/09/2004
Title:	MICROELECTRONIC CAPACITOR STRUCTURE WITH RADIAL CURRENT FLOW

Patent #:	6825707	Issue Dt:	11/30/2004	Application #:	10384860	Filing Dt:	03/10/2003
Publication #:	US20040178827	Pub Dt:	09/16/2004
Title:	CURRENT MODE LOGIC (CML) CIRCUIT CONCEPT FOR A VARIABLE DELAY ELEMENT

Patent #:	8934597	Issue Dt:	01/13/2015	Application #:	10386974	Filing Dt:	03/12/2003
Publication #:	US20040179640	Pub Dt:	09/16/2004
Title:	Multiple delay locked loop integration system and method

Patent #:	6909642	Issue Dt:	06/21/2005	Application #:	10387435	Filing Dt:	03/14/2003
Publication #:	US20040179417	Pub Dt:	09/16/2004
Title:	SELF TRIMMING VOLTAGE GENERATOR

Patent #:	6819142	Issue Dt:	11/16/2004	Application #:	10387733	Filing Dt:	03/13/2003
Publication #:	US20040178828	Pub Dt:	09/16/2004
Title:	CIRCUIT FOR TRANSFORMING A DIFFERENTIAL MODE SIGNAL INTO A SINGLE ENDED SIGNAL WITH REDUCED STANDBY CURRENT CONSUMPTION

Patent #:	6853229	Issue Dt:	02/08/2005	Application #:	10391850	Filing Dt:	03/19/2003
Publication #:	US20040183580	Pub Dt:	09/23/2004
Title:	CIRCUIT FOR TRANSFORMING A SINGLE ENDED SIGNAL INTO A DIFFERENTIAL MODE SIGNAL

Patent #:	6847225	Issue Dt:	01/25/2005	Application #:	10394779	Filing Dt:	03/21/2003
Publication #:	US20040183565	Pub Dt:	09/23/2004
Title:	CML (CURRENT MODE LOGIC) OCD (OFF CHIP DRIVER) - ODT (ON DIE TERMINATION) CIRCUIT FOR BIDIRECTIONAL DATA TRANSMISSION

Patent #:	6940773	Issue Dt:	09/06/2005	Application #:	10404561	Filing Dt:	04/02/2003
Publication #:	US20040196718	Pub Dt:	10/07/2004
Title:	METHOD AND SYSTEM FOR MANUFACTURING DRAMS WITH REDUCED SELF-REFRESH CURRENT REQUIREMENTS

Patent #:	6813193	Issue Dt:	11/02/2004	Application #:	10406019	Filing Dt:	04/02/2003
Publication #:	US20040196699	Pub Dt:	10/07/2004
Title:	MEMORY DEVICE AND METHOD OF OUTPUTTING DATA FROM A MEMORY DEVICE

Patent #:	6847571	Issue Dt:	01/25/2005	Application #:	10406320	Filing Dt:	04/04/2003
Publication #:	US20040196702	Pub Dt:	10/07/2004
Title:	USE OF REDUNDANT MEMORY CELLS TO MANUFACTURE COST EFFICIENT DRAMS WITH REDUCED SELF REFRESH CURRENT CAPABILITY

Patent #:	6807084	Issue Dt:	10/19/2004	Application #:	10418734	Filing Dt:	04/17/2003
Publication #:	US20040208043	Pub Dt:	10/21/2004
Title:	FERAM MEMORY DEVICE

Patent #:	7137049	Issue Dt:	11/14/2006	Application #:	10425224	Filing Dt:	04/29/2003
Publication #:	US20040221210	Pub Dt:	11/04/2004
Title:	METHOD AND APPARATUS FOR MASKING KNOWN FAILS DURING MEMORY TESTS READOUTS

Patent #:	7016027	Issue Dt:	03/21/2006	Application #:	10431368	Filing Dt:	05/08/2003
Publication #:	US20040223145	Pub Dt:	11/11/2004
Title:	SYSTEM AND METHOD FOR QUANTIFYING ERRORS IN AN ALTERNATING PHASE SHIFT MASK

Patent #:	6881592	Issue Dt:	04/19/2005	Application #:	10453858	Filing Dt:	06/03/2003
Publication #:	US20040072447	Pub Dt:	04/15/2004
Title:	METHOD AND DEVICE FOR MINIMIZING MULTI-LAYER MICROSCOPIC AND MACROSCOPIC ALIGNMENT ERRORS

Patent #:	6838339	Issue Dt:	01/04/2005	Application #:	10456648	Filing Dt:	06/05/2003
Publication #:	US20040248365	Pub Dt:	12/09/2004
Title:	AREA-EFFICIENT STACK CAPACITOR

Patent #:	6674684	Issue Dt:	01/06/2004	Application #:	10460791	Filing Dt:	06/11/2003
Title:	MULTI-BANK CHIP COMPATIBLE WITH A CONTROLLER DESIGNED FOR A LESSER NUMBER OF BANKS AND METHOD OF OPERATING

Patent #:	6807092	Issue Dt:	10/19/2004	Application #:	10461029	Filing Dt:	06/13/2003
Title:	MRAM CELL HAVING FRUSTRATED MAGNETIC RESERVOIRS

Patent #:	6930357	Issue Dt:	08/16/2005	Application #:	10463023	Filing Dt:	06/16/2003
Publication #:	US20040253773	Pub Dt:	12/16/2004
Title:	AN ACTIVE SOI STRUCTURE WITH A BODY CONTACT THROUGH AN INSULATOR

Patent #:	6806096	Issue Dt:	10/19/2004	Application #:	10464226	Filing Dt:	06/18/2003
Title:	INTEGRATION SCHEME FOR AVOIDING PLASMA DAMAGE IN MRAM TECHNOLOGY

Patent #:	6943396	Issue Dt:	09/13/2005	Application #:	10464382	Filing Dt:	06/17/2003
Publication #:	US20040256675	Pub Dt:	12/23/2004
Title:	ELECTRO-STATIC DISCHARGE PROTECTION CIRCUIT AND METHOD FOR MAKING THE SAME

Patent #:	7057253	Issue Dt:	06/06/2006	Application #:	10465144	Filing Dt:	06/19/2003
Publication #:	US20040256688	Pub Dt:	12/23/2004
Title:	COMBINATION OF INTRINSIC AND SHAPE ANISOTROPY FOR REDUCED SWITCHING FIELD FLUCTUATIONS

Patent #:	7265376	Issue Dt:	09/04/2007	Application #:	10533215	Filing Dt:	04/28/2005
Publication #:	US20060011972	Pub Dt:	01/19/2006
Title:	NON-VOLATILE MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCTION OF A NON-VOLATILE MEMORY CELL

Patent #:	6783999	Issue Dt:	08/31/2004	Application #:	10600057	Filing Dt:	06/20/2003
Title:	SUBTRACTIVE STUD FORMATION FOR MRAM MANUFACTURING

Patent #:	6713802	Issue Dt:	03/30/2004	Application #:	10600661	Filing Dt:	06/20/2003
Title:	MAGNETIC TUNNEL JUNCTION PATTERNING USING SIC OR SIN

Patent #:	6849465	Issue Dt:	02/01/2005	Application #:	10600920	Filing Dt:	06/20/2003
Publication #:	US20040259274	Pub Dt:	12/23/2004
Title:	METHOD OF PATTERNING A MAGNETIC MEMORY CELL BOTTOM ELECTRODE BEFORE MAGNETIC STACK DEPOSITION

Patent #:	7221788	Issue Dt:	05/22/2007	Application #:	10611067	Filing Dt:	07/01/2003
Publication #:	US20050002554	Pub Dt:	01/06/2005
Title:	METHOD OF INSPECTING A MASK OR RETICLE FOR DETECTING A DEFECT, AND MASK OR RETICLE INSPECTION SYSTEM

Patent #:	6839267	Issue Dt:	01/04/2005	Application #:	10618333	Filing Dt:	07/11/2003
Publication #:	US20050007804	Pub Dt:	01/13/2005
Title:	STRUCTURE AND METHOD OF MULTIPLEXING BITLINE SIGNALS WITHIN A MEMORY ARRAY

Patent #:	6937531	Issue Dt:	08/30/2005	Application #:	10624031	Filing Dt:	07/21/2003
Publication #:	US20050018497	Pub Dt:	01/27/2005
Title:	MEMORY DEVICE AND METHOD OF STORING FAIL ADDRESSES OF A MEMORY CELL

Patent #:	6975550	Issue Dt:	12/13/2005	Application #:	10625962	Filing Dt:	07/24/2003
Publication #:	US20050018469	Pub Dt:	01/27/2005
Title:	ARRAY TRANSISTOR AMPLIFICATION METHOD AND APPARATUS FOR DYNAMIC RANDOM ACCESS MEMORY

Patent #:	6913990	Issue Dt:	07/05/2005	Application #:	10628149	Filing Dt:	07/28/2003
Publication #:	US20050026341	Pub Dt:	02/03/2005
Title:	METHOD OF FORMING ISOLATION DUMMY FILL STRUCTURES

Patent #:	6928024	Issue Dt:	08/09/2005	Application #:	10639379	Filing Dt:	08/12/2003
Publication #:	US20040076040	Pub Dt:	04/22/2004
Title:	RAM MEMORY CIRCUIT AND METHOD FOR MEMORY OPERATION AT A MULTIPLIED DATA RATE

Patent #:	7062748	Issue Dt:	06/13/2006	Application #:	10648493	Filing Dt:	08/25/2003
Publication #:	US20050050511	Pub Dt:	03/03/2005
Title:	SYSTEM AND METHOD OF CORRECTING MASK RULE VIOLATIONS AFTER OPTICAL PROXIMITY CORRECTION

Patent #:	6977516	Issue Dt:	12/20/2005	Application #:	10651803	Filing Dt:	08/29/2003
Publication #:	US20050099201	Pub Dt:	05/12/2005
Title:	SEMI-CONDUCTOR COMPONENT TESTING SYSTEM WITH A REDUCED NUMBER OF TEST CHANNELS

Patent #:	7170798	Issue Dt:	01/30/2007	Application #:	10652266	Filing Dt:	08/29/2003
Publication #:	US20050050262	Pub Dt:	03/03/2005
Title:	CONTROLLED SUBSTRATE VOLTAGE FOR MEMORY SWITCHES

Patent #:	7211504	Issue Dt:	05/01/2007	Application #:	10652520	Filing Dt:	08/29/2003
Publication #:	US20040087127	Pub Dt:	05/06/2004
Title:	PROCESS AND ARRANGEMENT FOR THE SELECTIVE METALLIZATION OF 3D STRUCTURES

Patent #:	6970395	Issue Dt:	11/29/2005	Application #:	10658130	Filing Dt:	09/08/2003
Publication #:	US20050052943	Pub Dt:	03/10/2005
Title:	MEMORY DEVICE AND METHOD OF READING DATA FROM A MEMORY DEVICE

Patent #:	7231488	Issue Dt:	06/12/2007	Application #:	10663151	Filing Dt:	09/15/2003
Publication #:	US20050060488	Pub Dt:	03/17/2005
Title:	SELF-REFRESH SYSTEM AND METHOD FOR DYNAMIC RANDOM ACCESS MEMORY

Patent #:	7123523	Issue Dt:	10/17/2006	Application #:	10670662	Filing Dt:	09/25/2003
Publication #:	US20040056693	Pub Dt:	03/25/2004
Title:	INTEGRATED CIRCUIT HAVING AN INPUT CIRCUIT

Patent #:	7105400	Issue Dt:	09/12/2006	Application #:	10673262	Filing Dt:	09/30/2003
Publication #:	US20050070031	Pub Dt:	03/31/2005
Title:	MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Patent #:	6947306	Issue Dt:	09/20/2005	Application #:	10674304	Filing Dt:	09/30/2003
Publication #:	US20050078500	Pub Dt:	04/14/2005
Title:	BACKSIDE OF CHIP IMPLEMENTATION OF REDUNDANCY FUSES AND CONTACT PADS

Patent #:	6956782	Issue Dt:	10/18/2005	Application #:	10674905	Filing Dt:	09/30/2003
Publication #:	US20050068826	Pub Dt:	03/31/2005
Title:	SELECTIVE BANK REFRESH

Patent #:	7241701	Issue Dt:	07/10/2007	Application #:	10675049	Filing Dt:	09/30/2003
Publication #:	US20040081754	Pub Dt:	04/29/2004
Title:	METHOD AND FURNACE FOR THE VAPOR PHASE DEPOSITION OF COMPONENTS ONTO SEMICONDUCTOR SUBSTRATES WITH A VARIABLE MAIN FLOW DIRECTION OF THE PROCESS GAS

Patent #:	6958613	Issue Dt:	10/25/2005	Application #:	10675492	Filing Dt:	09/30/2003
Publication #:	US20040080322	Pub Dt:	04/29/2004
Title:	METHOD FOR CALIBRATING SEMICONDUCTOR DEVICES USING A COMMON CALIBRATION REFERENCE AND A CALIBRATION CIRCUIT

Patent #:	7124379	Issue Dt:	10/17/2006	Application #:	10675772	Filing Dt:	09/30/2003
Publication #:	US20040128643	Pub Dt:	07/01/2004
Title:	METHOD FOR COMMUNICATING A MEASURING POSITION OF A STRUCTURAL ELEMENT THAT IS TO BE FORMED ON A MASK

Patent #:	7162663	Issue Dt:	01/09/2007	Application #:	10676588	Filing Dt:	10/01/2003
Publication #:	US20040062102	Pub Dt:	04/01/2004
Title:	TEST SYSTEM AND METHOD FOR TESTING MEMORY CIRCUITS

Patent #:	6933206	Issue Dt:	08/23/2005	Application #:	10683668	Filing Dt:	10/10/2003
Publication #:	US20050079730	Pub Dt:	04/14/2005
Title:	TRENCH ISOLATION EMPLOYING A HIGH ASPECT RATIO TRENCH

Patent #:	7084966	Issue Dt:	08/01/2006	Application #:	10689241	Filing Dt:	10/20/2003
Publication #:	US20050083514	Pub Dt:	04/21/2005
Title:	OPTICAL MEASUREMENT OF DEVICE FEATURES USING LENSLET ARRAY ILLUMINATION

Patent #:	7009417	Issue Dt:	03/07/2006	Application #:	10689419	Filing Dt:	10/20/2003
Publication #:	US20040082121	Pub Dt:	04/29/2004
Title:	SEMICONDUCTOR MODULE AND METHODS FOR FUNCTIONALLY TESTING AND CONFIGURING A SEMICONDUCTOR MODULE

Patent #:	6949269	Issue Dt:	09/27/2005	Application #:	10690002	Filing Dt:	10/21/2003
Publication #:	US20040146655	Pub Dt:	07/29/2004
Title:	METHOD FOR PRODUCING VERTICAL PATTERNED LAYERS MADE OF SILICON DIOXIDE

Patent #:	7109772	Issue Dt:	09/19/2006	Application #:	10695624	Filing Dt:	10/28/2003
Publication #:	US20040135611	Pub Dt:	07/15/2004
Title:	D-TYPE FLIPFLOP

Patent #:	6967133	Issue Dt:	11/22/2005	Application #:	10696159	Filing Dt:	10/29/2003
Publication #:	US20040115874	Pub Dt:	06/17/2004
Title:	METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE

Patent #:	7049871	Issue Dt:	05/23/2006	Application #:	10699135	Filing Dt:	10/31/2003
Publication #:	US20040130370	Pub Dt:	07/08/2004
Title:	D-TYPE FLIP-FLOP WITH A REDUCED NUMBER OF TRANSISTORS

Patent #:	6927484	Issue Dt:	08/09/2005	Application #:	10700871	Filing Dt:	11/04/2003
Publication #:	US20040113256	Pub Dt:	06/17/2004
Title:	STACK ARRANGEMENT OF A MEMORY MODULE

Patent #:	7198979	Issue Dt:	04/03/2007	Application #:	10701742	Filing Dt:	11/04/2003
Publication #:	US20040126910	Pub Dt:	07/01/2004
Title:	METHOD FOR MANUFACTURING A STACK ARRANGEMENT OF A MEMORY MODULE

Patent #:	7157190	Issue Dt:	01/02/2007	Application #:	10703298	Filing Dt:	11/06/2003
Publication #:	US20040146787	Pub Dt:	07/29/2004
Title:	METHOD FOR REPAIRING A PHOTOLITHOGRAPHIC MASK, AND A PHOTOLITHOGRAPHIC MASK

Patent #:	7183131	Issue Dt:	02/27/2007	Application #:	10712767	Filing Dt:	11/12/2003
Publication #:	US20050040847	Pub Dt:	02/24/2005
Title:	PROCESS FOR PRODUCING A NANOELEMENT ARRANGEMENT, AND NANOELEMENT ARRANGEMENT

Patent #:	6940123	Issue Dt:	09/06/2005	Application #:	10713689	Filing Dt:	11/14/2003
Publication #:	US20040099901	Pub Dt:	05/27/2004
Title:	MEMORY CELL ARRAY

Patent #:	7035116	Issue Dt:	04/25/2006	Application #:	10715145	Filing Dt:	11/17/2003
Publication #:	US20040125635	Pub Dt:	07/01/2004
Title:	MEMORY SYSTEM AND MEMORY SUBSYSTEM

Patent #:	7031218	Issue Dt:	04/18/2006	Application #:	10717178	Filing Dt:	11/17/2003
Publication #:	US20040156226	Pub Dt:	08/12/2004
Title:	EXTERNALLY CLOCKED ELECTRICAL FUSE PROGRAMMING WITH ASYNCHRONOUS FUSE SELECTION

Patent #:	7248365	Issue Dt:	07/24/2007	Application #:	10717413	Filing Dt:	11/19/2003
Publication #:	US20040100625	Pub Dt:	05/27/2004
Title:	METHOD FOR ADJUSTING A SUBSTRATE IN AN APPLIANCE FOR CARRYING OUT EXPOSURE

Patent #:	7293190	Issue Dt:	11/06/2007	Application #:	10720437	Filing Dt:	11/24/2003
Publication #:	US20050110523	Pub Dt:	05/26/2005
Title:	NOISY CLOCK TEST METHOD AND APPARATUS

Patent #:	7074649	Issue Dt:	07/11/2006	Application #:	10721745	Filing Dt:	11/26/2003
Publication #:	US20050014309	Pub Dt:	01/20/2005
Title:	METHOD FOR PRODUCING AN INTEGRATED CIRCUIT WITH A REWIRING DEVICE AND CORRESPONDING INTEGRATED CIRCUIT

Patent #:	6916721	Issue Dt:	07/12/2005	Application #:	10722360	Filing Dt:	11/26/2003
Publication #:	US20040197988	Pub Dt:	10/07/2004
Title:	METHOD FOR FABRICATING A TRENCH CAPACITOR WITH AN INSULATION COLLAR

Patent #:	7009869	Issue Dt:	03/07/2006	Application #:	10723289	Filing Dt:	11/25/2003
Publication #:	US20040151020	Pub Dt:	08/05/2004
Title:	DYNAMIC MEMORY CELL

Patent #:	7166393	Issue Dt:	01/23/2007	Application #:	10723631	Filing Dt:	11/26/2003
Publication #:	US20040106051	Pub Dt:	06/03/2004
Title:	REFLECTION MASK FOR PROJECTING A STRUCTURE ONTO A SEMICONDUCTOR WAFER AND METHOD FOR PRODUCING THE MASK

Patent #:	6992475	Issue Dt:	01/31/2006	Application #:	10723905	Filing Dt:	11/26/2003
Publication #:	US20040140818	Pub Dt:	07/22/2004
Title:	CIRCUIT AND METHOD FOR DETERMINING AT LEAST ONE VOLTAGE, CURRENT AND/OR POWER VALUE FOR AN INTEGRATED CIRCUIT

Patent #:	6977427	Issue Dt:	12/20/2005	Application #:	10723906	Filing Dt:	11/26/2003
Publication #:	US20040108585	Pub Dt:	06/10/2004
Title:	ELECTRONIC COMPONENT HAVING STACKED SEMICONDUCTOR CHIPS IN PARALLEL, AND A METHOD FOR PRODUCING THE COMPONENT

Patent #:	6919234	Issue Dt:	07/19/2005	Application #:	10724007	Filing Dt:	11/26/2003
Publication #:	US20050003647	Pub Dt:	01/06/2005
Title:	METHOD FOR PRODUCING AN ANTIFUSE IN A SUBSTRATE AND AN ANTIFUSE STRUCTURE FOR INTEGRATION IN A SUBSTRATE

Patent #:	7170125	Issue Dt:	01/30/2007	Application #:	10724134	Filing Dt:	12/01/2003
Publication #:	US20040152255	Pub Dt:	08/05/2004
Title:	CAPACITOR WITH ELECTRODES MADE OF RUTHENIUM AND METHOD FOR PATTERNING LAYERS MADE OF RUTHENIUM OR RUTHENIUM(IV) OXIDE

Patent #:	7275189	Issue Dt:	09/25/2007	Application #:	10724135	Filing Dt:	12/01/2003
Publication #:	US20040151038	Pub Dt:	08/05/2004
Title:	MEMORY MODULE AND METHOD FOR OPERATING A MEMORY MODULE IN A DATA MEMORY SYSTEM

Patent #:	7199060	Issue Dt:	04/03/2007	Application #:	10724141	Filing Dt:	12/01/2003
Publication #:	US20040152332	Pub Dt:	08/05/2004
Title:	METHOD FOR PATTERNING DIELECTRIC LAYERS ON SEMICONDUCTOR SUBSTRATES

Patent #:	6859406	Issue Dt:	02/22/2005	Application #:	10724906	Filing Dt:	12/01/2003
Publication #:	US20040109343	Pub Dt:	06/10/2004
Title:	DYNAMIC RAM SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE MEMORY

Patent #:	6992345	Issue Dt:	01/31/2006	Application #:	10727595	Filing Dt:	12/05/2003
Publication #:	US20040136227	Pub Dt:	07/15/2004
Title:	INTEGRATED SEMICONDUCTOR MEMORY WITH A SELECTION TRANSISTOR FORMED AT A RIDGE

Patent #:	6913987	Issue Dt:	07/05/2005	Application #:	10728388	Filing Dt:	12/05/2003
Publication #:	US20040115912	Pub Dt:	06/17/2004
Title:	METHOD FOR FABRICATING SELF-ALIGNED CONTACT CONNECTIONS ON BURIED BIT LINES

Patent #:	7057224	Issue Dt:	06/06/2006	Application #:	10731109	Filing Dt:	12/10/2003
Publication #:	US20040135190	Pub Dt:	07/15/2004
Title:	SEMICONDUCTOR MEMORY HAVING AN ARRANGEMENT OF MEMORY CELLS

100

Patent #:	7251772	Issue Dt:	07/31/2007	Application #:	10732402	Filing Dt:	12/11/2003
Publication #:	US20040136249	Pub Dt:	07/15/2004
Title:	CIRCUIT ARRANGEMENT HAVING A NUMBER OF INTEGRATED CIRCUIT COMPONENTS ON A CARRIER SUBSTRATE AND METHOD FOR TESTING A CIRCUIT ARRANGEMENT OF THIS TYPE

Assignor

INFINEON TECHNOLOGIES AG

Exec Dt:

07/08/2015

Assignee

POLARIS INNOVATIONS LIMITED

29 EARLSFORT TERRACE, DUBLIN 2

DUBLIN, IRELAND

Correspondence name and address
	POLARIS INNOVATIONS LIMITED
	303 TERRY FOX DRIVE, SUITE 300
	OTTAWA, K2K 3J1 CANADA

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