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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08514120
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Filing Dt:
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08/11/1995
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Title:
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CURRENT CONTROL CIRCUIT AND METHOD FOR PROGRAMMABLE READ WRITE PREAMPLIFIER
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Patent #:
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Issue Dt:
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09/15/1998
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Application #:
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08650700
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Filing Dt:
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05/20/1996
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Title:
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SYSTEM AND METHOD FOR ENCODING DATA SUCH THAT AFTER PRECODING THE DATA HAS A PRE-SELECTED PARITY STRUCTURE
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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08791687
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Filing Dt:
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01/30/1997
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Title:
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SYSTEM AND METHOD FOR GENERATING MANY ONES CODES WITH HAMMING DISTANCE AFTER PRECODING
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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11280864
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Filing Dt:
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11/17/2005
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Publication #:
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Pub Dt:
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05/17/2007
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Title:
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METHOD FOR MANUFACTURING A RESISTIVELY SWITCHING MEMORY CELL AND MEMORY DEVICE BASED THEREON
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Patent #:
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Issue Dt:
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03/10/2009
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Application #:
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11292948
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Filing Dt:
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12/02/2005
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Publication #:
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Pub Dt:
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06/07/2007
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Title:
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PROCESSING ARRANGEMENT, MEMORY CARD DEVICE AND METHOD FOR OPERATING AND MANUFACTURING A PROCESSING ARRANGEMENT
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Patent #:
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Issue Dt:
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07/01/2008
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Application #:
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11304062
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Filing Dt:
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12/15/2005
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Publication #:
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Pub Dt:
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06/21/2007
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Title:
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SEMICONDUCTOR MEMORY DEVICE WITH CHANNEL REGIONS ALONG SIDEWALLS OF FINS
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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11313650
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Filing Dt:
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12/22/2005
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Publication #:
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Pub Dt:
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06/28/2007
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Title:
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GATE INDUCED DRAIN LEAKAGE CURRENT REDUCTION BY VOLTAGE REGULATION OF MASTER WORDLINE
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11314529
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Filing Dt:
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12/22/2005
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Publication #:
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Pub Dt:
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06/28/2007
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Title:
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WRITE BURST STOP FUNCTION IN LOW POWER DDR SDRAM
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Patent #:
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Issue Dt:
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04/14/2009
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Application #:
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11318331
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Filing Dt:
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12/23/2005
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Publication #:
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Pub Dt:
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07/26/2007
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Title:
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RESISTIVE MEMORY DEVICE AND METHOD FOR WRITING TO A RESISTIVE MEMORY CELL IN A RESISTIVE MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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11320266
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Filing Dt:
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12/28/2005
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Publication #:
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Pub Dt:
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07/19/2007
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Title:
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EDGE PAD ARCHITECTURE FOR SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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11321450
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Filing Dt:
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12/30/2005
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR DEVICE WITH RECESSED CHANNEL AND CORNER GATE DEVICE
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Patent #:
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Issue Dt:
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08/14/2007
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Application #:
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11322252
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Filing Dt:
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01/03/2006
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
Title:
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TEST MODE FOR IPP CURRENT MEASUREMENT FOR WORDLINE DEFECT DETECTION
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11324700
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Filing Dt:
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01/03/2006
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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11326235
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Filing Dt:
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01/05/2006
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Publication #:
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Pub Dt:
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07/05/2007
| | | | |
Title:
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INTEGRATED CIRCUIT MEMORY HAVING A READ CIRCUIT
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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11327054
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Filing Dt:
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01/06/2006
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Publication #:
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Pub Dt:
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07/12/2007
| | | | |
Title:
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MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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11327354
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Filing Dt:
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01/09/2006
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Publication #:
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Pub Dt:
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07/12/2007
| | | | |
Title:
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MEMORY DATA BUS STRUCTURE AND METHOD OF TRANSFERRING INFORMATION WITH PLURAL MEMORY BANKS
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11333037
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Filing Dt:
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01/17/2006
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Publication #:
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Pub Dt:
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07/19/2007
| | | | |
Title:
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TEST PARALLELISM INCREASE BY TESTER CONTROLLABLE SWITCHING OF CHIP SELECT GROUPS
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Patent #:
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Issue Dt:
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02/10/2009
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Application #:
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11337754
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Filing Dt:
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01/23/2006
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Publication #:
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Pub Dt:
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07/26/2007
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Title:
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SYSTEM METHOD FOR PERFORMING A DIRECT MEMORY ACCESS FOR AUTOMATICALLY COPYING INITIALIZATION BOOT CODE IN A NEW MEMORY ARCHITECTURE
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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11339744
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Filing Dt:
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01/25/2006
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Publication #:
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Pub Dt:
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07/26/2007
| | | | |
Title:
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STORAGE CAPACITOR FOR SEMICONDUCTOR MEMORY CELLS AND METHOD OF MANUFACTURING A STORAGE CAPACITOR
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Patent #:
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Issue Dt:
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11/17/2009
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Application #:
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11346905
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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CLOCK AND DATA RECOVERY CIRCUIT HAVING GAIN CONTROL
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Patent #:
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Issue Dt:
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12/02/2008
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Application #:
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11346993
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Filing Dt:
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02/03/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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DATA HANDOVER UNIT FOR TRANSFERRING DATA BETWEEN DIFFERENT CLOCK DOMAINS BY PARALLELLY READING OUT DATA BITS FROM A PLURALITY OF STORAGE ELEMENTS
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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11349631
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Filing Dt:
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02/08/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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SHARED INTERFACE FOR COMPONENTS IN AN EMBEDDED SYSTEM
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11354955
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Filing Dt:
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02/16/2006
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Publication #:
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Pub Dt:
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08/16/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR CALIBRATION OF AN ON-CHIP TEMPERATURE SENSOR WITHIN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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02/19/2008
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Application #:
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11354985
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Filing Dt:
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02/16/2006
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Publication #:
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Pub Dt:
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08/16/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR AN OSCILLATOR WITHIN A MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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11366370
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Filing Dt:
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03/02/2006
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Publication #:
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Pub Dt:
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10/04/2007
| | | | |
Title:
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PHASE CHANGE MEMORY FABRICATED USING SELF-ALIGNED PROCESSING
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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11366706
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Filing Dt:
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03/02/2006
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Publication #:
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Pub Dt:
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10/04/2007
| | | | |
Title:
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PHASE CHANGE MEMORY FABRICATED USING SELF-ALIGNED PROCESSING
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11368266
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Filing Dt:
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03/03/2006
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Publication #:
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Pub Dt:
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09/06/2007
| | | | |
Title:
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METHODS FOR GENERATING A REFERENCE VOLTAGE AND FOR READING A MEMORY CELL AND CIRCUIT CONFIGURATIONS IMPLEMENTING THE METHODS
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Patent #:
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Issue Dt:
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01/06/2009
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Application #:
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11370172
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Filing Dt:
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03/08/2006
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Publication #:
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Pub Dt:
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09/13/2007
| | | | |
Title:
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INTEGRATED SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11371237
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Filing Dt:
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03/09/2006
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Publication #:
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Pub Dt:
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09/13/2007
| | | | |
Title:
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METHOD FOR DETERMINING AN EDGE PROFILE OF A VOLUME OF A PHOTORESIST AFTER A DEVELOPMENT PROCESS
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Patent #:
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Issue Dt:
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04/21/2009
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Application #:
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11374413
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Filing Dt:
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03/13/2006
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Publication #:
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Pub Dt:
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09/13/2007
| | | | |
Title:
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MEMORY CIRCUIT, METHOD FOR OPERATING A MEMORY CIRCUIT, MEMORY DEVICE AND METHOD FOR PRODUCING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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09/09/2008
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Application #:
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11375365
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Filing Dt:
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03/14/2006
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Publication #:
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Pub Dt:
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09/20/2007
| | | | |
Title:
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Integrated Circuit Having A Memory Cell
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Patent #:
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Issue Dt:
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02/16/2010
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Application #:
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11376645
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Filing Dt:
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03/15/2006
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Publication #:
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Pub Dt:
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09/20/2007
| | | | |
Title:
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HARD MASK LAYER STACK AND A METHOD OF PATTERNING
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Patent #:
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Issue Dt:
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01/06/2009
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Application #:
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11378201
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Filing Dt:
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03/17/2006
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Publication #:
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Pub Dt:
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09/20/2007
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Title:
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INTERGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL ELEMENT
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11385340
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Filing Dt:
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03/21/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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PARALLEL READ FOR FRONT END COMPRESSION MODE
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11386048
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Filing Dt:
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03/21/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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MEMORY WITH A TEMPERATURE SENSOR, DYNAMIC MEMORY AND MEMORY WITH A CLOCK UNIT AND METHOD OF SENSING A TEMPERATURE OF A MEMORY
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11386176
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Filing Dt:
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03/22/2006
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Publication #:
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Pub Dt:
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10/18/2007
| | | | |
Title:
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FINDING A DATA PATTERN IN A MEMORY
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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11386360
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Filing Dt:
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03/22/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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MEMORY INCLUDING A WRITE TRAINING BLOCK
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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11386377
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Filing Dt:
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03/22/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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FILTERING BIT POSITION IN A MEMORY
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Patent #:
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Issue Dt:
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07/21/2009
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Application #:
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11386510
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Filing Dt:
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03/22/2006
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Publication #:
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Pub Dt:
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11/08/2007
| | | | |
Title:
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MEMORY INCLUDING AN OUTPUT POINTER CIRCUIT
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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11387879
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Filing Dt:
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03/24/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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REDUCING LEAKAGE CURRENT IN MEMORY DEVICE USING BITLINE ISOLATION
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Patent #:
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Issue Dt:
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04/22/2008
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Application #:
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11388234
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Filing Dt:
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03/23/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11390983
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Filing Dt:
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03/27/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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METHOD FOR FORMING AN INTEGRATED MEMORY DEVICE AND MEMORY DEVICE
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Patent #:
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Issue Dt:
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08/05/2008
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Application #:
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11390997
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Filing Dt:
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03/27/2006
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Publication #:
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Pub Dt:
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09/27/2007
| | | | |
Title:
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CHARGE TRAPPING DEVICE AND METHOD OF PRODUCING THE CHARGE TRAPPING DEVICE
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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11397429
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Filing Dt:
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04/04/2006
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Publication #:
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Pub Dt:
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10/04/2007
| | | | |
Title:
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METHODS OF DDR RECEIVER READ RE-SYNCHRONIZATION
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11400742
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Filing Dt:
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04/07/2006
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Publication #:
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Pub Dt:
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10/25/2007
| | | | |
Title:
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MEMORY HAVING STORAGE LOCATIONS WITHIN A COMMON VOLUME OF PHASE CHANGE MATERIAL
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Patent #:
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Issue Dt:
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07/21/2009
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Application #:
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11402649
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Filing Dt:
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04/12/2006
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Publication #:
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Pub Dt:
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10/18/2007
| | | | |
Title:
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METHOD FOR PROGRAMMING A BLOCK OF MEMORY CELLS, NON-VOLATILE MEMORY DEVICE AND MEMORY CARD DEVICE
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Patent #:
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Issue Dt:
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12/18/2007
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Application #:
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11403453
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Filing Dt:
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04/13/2006
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Publication #:
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Pub Dt:
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10/18/2007
| | | | |
Title:
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DUTY CYCLE CORRECTOR
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Patent #:
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Issue Dt:
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11/25/2014
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Application #:
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11406766
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Filing Dt:
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04/19/2006
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Publication #:
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Pub Dt:
|
10/25/2007
| | | | |
Title:
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INTEGRATED CIRCUIT INCLUDING SIDEWALL SPACER
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Patent #:
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Issue Dt:
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02/24/2009
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Application #:
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11406803
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Filing Dt:
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04/19/2006
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Publication #:
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Pub Dt:
|
10/25/2007
| | | | |
Title:
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CIRCUIT AND A METHOD OF DETERMINING THE RESISTIVE STATE OF A RESISTIVE MEMORY CELL
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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11408647
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Filing Dt:
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04/21/2006
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Publication #:
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Pub Dt:
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10/25/2007
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Title:
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SYSTEM AND METHOD TO SYNCHRONIZE SIGNALS IN INDIVIDUAL INTEGRATED CIRCUIT COMPONENTS
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Patent #:
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Issue Dt:
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09/02/2008
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Application #:
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11410635
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Filing Dt:
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04/25/2006
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Publication #:
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Pub Dt:
|
10/25/2007
| | | | |
Title:
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DATA INVERSION DEVICE AND METHOD
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Patent #:
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Issue Dt:
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06/16/2009
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Application #:
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11411317
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Filing Dt:
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04/26/2006
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Publication #:
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Pub Dt:
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03/01/2007
| | | | |
Title:
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INTEGRATED CIRCUIT HAVING A SWITCH
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Patent #:
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Issue Dt:
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07/22/2008
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Application #:
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11414364
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Filing Dt:
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05/01/2006
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Publication #:
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Pub Dt:
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11/01/2007
| | | | |
Title:
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BITLINE LEAKAGE LIMITING WITH IMPROVED VOLTAGE REGULATION
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11414553
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Filing Dt:
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05/01/2006
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Publication #:
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Pub Dt:
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11/01/2007
| | | | |
Title:
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VERTICAL DEVICE WITH SIDEWALL SPACER, METHODS OF FORMING SIDEWALL SPACERS AND FIELD EFFECT TRANSISTORS, AND PATTERNING METHOD
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Patent #:
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Issue Dt:
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08/19/2008
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Application #:
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11414570
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Filing Dt:
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04/28/2006
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Publication #:
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Pub Dt:
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11/01/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR EARLY WRITE TERMINATION IN A SEMICONDUCUTOR MEMORY
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Patent #:
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Issue Dt:
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12/02/2008
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Application #:
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11436358
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Filing Dt:
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05/18/2006
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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PHASE CHANGE MEMORY HAVING TEMPERATURE BUDGET SENSOR
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Patent #:
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Issue Dt:
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05/11/2010
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Application #:
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11437211
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Filing Dt:
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05/19/2006
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Publication #:
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Pub Dt:
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08/09/2007
| | | | |
Title:
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THERMAL ISOLATION OF PHASE CHANGE MEMORY CELLS
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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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11438700
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Filing Dt:
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05/23/2006
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Publication #:
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Pub Dt:
|
11/29/2007
| | | | |
Title:
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METHOD FOR PRODUCING A DIELECTRIC INTERLAYER AND STORAGE CAPACITOR WITH SUCH A DIELECTRIC INTERLAYER
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Patent #:
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Issue Dt:
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01/01/2008
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Application #:
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11439443
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Filing Dt:
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05/24/2006
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Publication #:
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Pub Dt:
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05/03/2007
| | | | |
Title:
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SEMICONDUCTOR MEMORY MODULE
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Patent #:
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Issue Dt:
|
09/15/2009
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Application #:
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11443432
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Filing Dt:
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05/31/2006
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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MEMORY CELL ARRAY AND METHOD OF FORMING A MEMORY CELL ARRAY
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Patent #:
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Issue Dt:
|
10/07/2008
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Application #:
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11443493
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Filing Dt:
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05/30/2006
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Publication #:
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Pub Dt:
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12/27/2007
| | | | |
Title:
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INTEGRATED MEMORY DEVICE AND METHOD FOR ITS TESTING AND MANUFACTURE
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Patent #:
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Issue Dt:
|
05/20/2008
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Application #:
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11443602
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Filing Dt:
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05/31/2006
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
|
12/01/2009
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Application #:
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11445801
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Filing Dt:
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06/02/2006
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Publication #:
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Pub Dt:
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12/06/2007
| | | | |
Title:
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MEMORY DEVICE, IN PARTICULAR PHASE CHANGE RANDOM ACCESS MEMORY DEVICE WITH TRANSISTOR, AND METHOD FOR FABRICATING A MEMORY DEVICE
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Patent #:
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Issue Dt:
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01/19/2010
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Application #:
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11452417
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Filing Dt:
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06/14/2006
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Publication #:
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Pub Dt:
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11/22/2007
| | | | |
Title:
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PROGRAMMABLE RESISTIVE MEMORY CELL WITH A PROGRAMMABLE RESISTANCE LAYER
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Patent #:
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Issue Dt:
|
11/04/2008
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Application #:
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11453946
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Filing Dt:
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06/15/2006
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Publication #:
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Pub Dt:
|
12/27/2007
| | | | |
Title:
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RANDOM ACCESS MEMORY INCLUDING MULTIPLE STATE MACHINES
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Patent #:
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Issue Dt:
|
11/25/2008
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Application #:
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11455340
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Filing Dt:
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06/19/2006
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Publication #:
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Pub Dt:
|
12/27/2007
| | | | |
Title:
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MEMORY CELL PROGRAMMED USING A TEMPERATURE CONTROLLED SET PULSE
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Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
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11456063
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Filing Dt:
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07/06/2006
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Publication #:
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Pub Dt:
|
01/10/2008
| | | | |
Title:
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METHOD FOR ACCESSING A NON-VOLATILE MEMORY VIA A VOLATILE MEMORY INTERFACE
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Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
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11457133
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Filing Dt:
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07/12/2006
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Publication #:
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Pub Dt:
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01/17/2008
| | | | |
Title:
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APPARATUS AND METHOD FOR CONTROLLING A DRIVER STRENGTH
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Patent #:
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|
Issue Dt:
|
06/21/2011
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Application #:
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11464215
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Filing Dt:
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08/14/2006
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Publication #:
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Pub Dt:
|
04/23/2009
| | | | |
Title:
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MEMORY SYSTEM AND METHOD FOR OPERATING A MEMORY SYSTEM
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Patent #:
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Issue Dt:
|
04/19/2011
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Application #:
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11464784
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Filing Dt:
|
08/15/2006
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Publication #:
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Pub Dt:
|
02/21/2008
| | | | |
Title:
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INTEGRATED CIRCUIT PACKAGE WITH A HEAT DISSIPATION DEVICE
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Patent #:
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Issue Dt:
|
02/08/2011
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Application #:
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11466312
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Filing Dt:
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08/22/2006
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Publication #:
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Pub Dt:
|
02/28/2008
| | | | |
Title:
|
METHOD AND CIRCUIT FOR TRANSMITTING A MEMORY CLOCK SIGNAL
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|
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Patent #:
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|
Issue Dt:
|
04/15/2008
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Application #:
|
11467747
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Filing Dt:
|
08/28/2006
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Publication #:
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Pub Dt:
|
02/28/2008
| | | | |
Title:
|
TRANSISTOR, MEMORY CELL ARRAY AND METHOD FOR FORMING AND OPERATING A MEMORY DEVICE
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Patent #:
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|
Issue Dt:
|
09/02/2008
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Application #:
|
11468465
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Filing Dt:
|
08/30/2006
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Publication #:
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Pub Dt:
|
03/06/2008
| | | | |
Title:
|
MEMORY DEVICE AND METHOD FOR TRANSFORMING BETWEEN NON-POWER-OF-2 LEVELS OF MULTILEVEL MEMORY CELLS AND 2-LEVEL DATA BITS
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|
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Patent #:
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Issue Dt:
|
08/05/2008
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Application #:
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11469365
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Filing Dt:
|
08/31/2006
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Publication #:
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Pub Dt:
|
03/06/2008
| | | | |
Title:
|
METHOD AND DEVICE FOR VERIFYING OUTPUT SIGNALS OF AN INTEGRATED CIRCUIT
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|
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Patent #:
|
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Issue Dt:
|
10/18/2011
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Application #:
|
11473441
|
Filing Dt:
|
06/23/2006
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Publication #:
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Pub Dt:
|
12/27/2007
| | | | |
Title:
|
SPUTTER DEPOSITION METHOD FOR FORMING INTEGRATED CIRCUIT
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Patent #:
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|
Issue Dt:
|
01/13/2009
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Application #:
|
11475720
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Filing Dt:
|
06/27/2006
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Publication #:
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|
Pub Dt:
|
12/27/2007
| | | | |
Title:
|
DIE CONFIGURATIONS AND METHODS OF MANUFACTURE
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|
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Patent #:
|
|
Issue Dt:
|
11/10/2009
|
Application #:
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11477581
|
Filing Dt:
|
06/29/2006
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Publication #:
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|
Pub Dt:
|
01/03/2008
| | | | |
Title:
|
METHOD FOR FORMING A CAPACITOR STRUCTURE
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Patent #:
|
|
Issue Dt:
|
03/16/2010
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Application #:
|
11478313
|
Filing Dt:
|
06/30/2006
|
Publication #:
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Pub Dt:
|
01/03/2008
| | | | |
Title:
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BURIED BITLINE WITH REDUCED RESISTANCE
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Patent #:
|
|
Issue Dt:
|
07/21/2009
|
Application #:
|
11481157
|
Filing Dt:
|
07/05/2006
|
Publication #:
|
|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
MEMORY DEVICE, AND METHOD FOR OPERATING A MEMORY DEVICE
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|
|
Patent #:
|
|
Issue Dt:
|
10/20/2009
|
Application #:
|
11483197
|
Filing Dt:
|
07/07/2006
|
Publication #:
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Pub Dt:
|
02/07/2008
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH STACKED CHIPS AND METHOD FOR MANUFACTURING THEREOF
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Patent #:
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|
Issue Dt:
|
02/16/2010
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Application #:
|
11483873
|
Filing Dt:
|
07/10/2006
|
Publication #:
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Pub Dt:
|
01/10/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT HAVING A PHASE CHANGE MEMORY CELL INCLUDING A NARROW ACTIVE REGION WIDTH
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Patent #:
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|
Issue Dt:
|
09/07/2010
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Application #:
|
11483968
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Filing Dt:
|
07/10/2006
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Publication #:
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|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
METHOD OF MANUFACTURING AT LEAST ONE SEMICONDUCTOR COMPONENT AND MEMORY CELLS
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Patent #:
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Issue Dt:
|
09/09/2008
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Application #:
|
11487472
|
Filing Dt:
|
07/17/2006
|
Publication #:
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Pub Dt:
|
01/17/2008
| | | | |
Title:
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METHOD AND SYSTEM FOR TRIMMING VOLTAGE OR CURRENT REFERENCES
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Patent #:
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Issue Dt:
|
12/22/2009
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Application #:
|
11487875
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Filing Dt:
|
07/17/2006
|
Publication #:
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|
Pub Dt:
|
01/17/2008
| | | | |
Title:
|
RANDOM ACCESS MEMORY THAT SELECTIVELY PROVIDES DATA TO AMPLIFIERS
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Patent #:
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|
Issue Dt:
|
12/27/2011
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Application #:
|
11488422
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Filing Dt:
|
07/18/2006
|
Publication #:
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|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH MEMORY HAVING A STEP-LIKE PROGRAMMING CHARACTERISTIC
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Patent #:
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Issue Dt:
|
06/09/2009
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Application #:
|
11489052
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Filing Dt:
|
07/19/2006
|
Publication #:
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|
Pub Dt:
|
01/10/2008
| | | | |
Title:
|
METHOD FOR MANUFACTURING A CAPACITOR ELECTRODE STRUCTURE
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Patent #:
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Issue Dt:
|
11/18/2008
|
Application #:
|
11490213
|
Filing Dt:
|
07/20/2006
|
Publication #:
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|
Pub Dt:
|
01/24/2008
| | | | |
Title:
|
PHASE CHANGE MEMORY CELL INCLUDING NANOCOMPOSITE INSULATOR
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|
|
Patent #:
|
|
Issue Dt:
|
05/20/2008
|
Application #:
|
11492636
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Filing Dt:
|
07/25/2006
|
Publication #:
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|
Pub Dt:
|
02/07/2008
| | | | |
Title:
|
BOOSTED CLOCK CIRCUIT FOR SEMICONDUCTOR MEMORY
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|
|
Patent #:
|
|
Issue Dt:
|
11/17/2009
|
Application #:
|
11493028
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Filing Dt:
|
07/26/2006
|
Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
Title:
|
METHOD OF FORMING A DOPED PORTION OF A SEMICONDUCTOR AND METHOD OF FORMING A TRANSISTOR
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Patent #:
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Issue Dt:
|
06/08/2010
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Application #:
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11494848
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Filing Dt:
|
07/28/2006
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Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
Title:
|
DATA SAMPLER INCLUDING A FIRST STAGE AND A SECOND STAGE
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|
|
Patent #:
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|
Issue Dt:
|
10/07/2008
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Application #:
|
11495689
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Filing Dt:
|
07/31/2006
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Publication #:
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Pub Dt:
|
01/31/2008
| | | | |
Title:
|
MEMORY SYSTEM
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|
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Patent #:
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Issue Dt:
|
11/01/2011
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Application #:
|
11496724
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Filing Dt:
|
08/01/2006
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Publication #:
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Pub Dt:
|
02/07/2008
| | | | |
Title:
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METHOD FOR PLACING MATERIAL ONTO A TARGET BOARD BY MEANS OF A TRANSFER BOARD
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|
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Patent #:
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Issue Dt:
|
03/09/2010
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Application #:
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11502627
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Filing Dt:
|
08/11/2006
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Publication #:
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Pub Dt:
|
02/14/2008
| | | | |
Title:
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SHIELDED CIRCUIT BOARD AND METHOD FOR SHIELDING A CIRCUIT BOARD
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Patent #:
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Issue Dt:
|
07/13/2010
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Application #:
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11507647
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Filing Dt:
|
08/21/2006
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Publication #:
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Pub Dt:
|
02/21/2008
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
10/04/2011
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Application #:
|
11510512
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Filing Dt:
|
08/25/2006
|
Publication #:
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|
Pub Dt:
|
03/20/2008
| | | | |
Title:
|
MEMORY ELEMENT COMPRISING NON-GRAPHITIC DISORERED CARBON AND
USING REVERSIBLE SWITICHING BETWEEN SP2 AND SP3 HYBIRDIZATION STATES
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|
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Patent #:
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Issue Dt:
|
01/18/2011
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Application #:
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11513502
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Filing Dt:
|
08/31/2006
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Publication #:
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Pub Dt:
|
03/06/2008
| | | | |
Title:
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FILTER SYSTEM FOR LIGHT SOURCE
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|
|
Patent #:
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|
Issue Dt:
|
11/03/2009
|
Application #:
|
11517557
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Filing Dt:
|
09/08/2006
|
Publication #:
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|
Pub Dt:
|
03/13/2008
| | | | |
Title:
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TRANSISTOR, MEMORY CELL ARRAY AND METHOD OF MANUFACTURING A TRANSISTOR
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Patent #:
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Issue Dt:
|
06/07/2011
|
Application #:
|
11517558
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Filing Dt:
|
09/08/2006
|
Publication #:
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Pub Dt:
|
05/29/2008
| | | | |
Title:
|
TRANSISTOR AND MEMORY CELL ARRAY
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|
|
Patent #:
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|
Issue Dt:
|
01/05/2010
|
Application #:
|
11517634
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Filing Dt:
|
09/08/2006
|
Publication #:
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Pub Dt:
|
03/13/2008
| | | | |
Title:
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INTEGRATED MEMORY CELL ARRAY
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|
|
Patent #:
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|
Issue Dt:
|
07/13/2010
|
Application #:
|
11530015
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Filing Dt:
|
09/07/2006
|
Publication #:
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|
Pub Dt:
|
03/13/2008
| | | | |
Title:
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METHOD AND APPARATUS FOR SENDING DATA FROM A MEMORY
|
|