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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037171/0719   Pages: 12
Recorded: 11/30/2015
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 185
Page 1 of 2
Pages: 1 2
1
Patent #:
5790331
Issue Dt:
08/04/1998
Application #:
08514120
Filing Dt:
08/11/1995
Title:
CURRENT CONTROL CIRCUIT AND METHOD FOR PROGRAMMABLE READ WRITE PREAMPLIFIER
2
Patent #:
5809081
Issue Dt:
09/15/1998
Application #:
08650700
Filing Dt:
05/20/1996
Title:
SYSTEM AND METHOD FOR ENCODING DATA SUCH THAT AFTER PRECODING THE DATA HAS A PRE-SELECTED PARITY STRUCTURE
3
Patent #:
6084535
Issue Dt:
07/04/2000
Application #:
08791687
Filing Dt:
01/30/1997
Title:
SYSTEM AND METHOD FOR GENERATING MANY ONES CODES WITH HAMMING DISTANCE AFTER PRECODING
4
Patent #:
7323357
Issue Dt:
01/29/2008
Application #:
11280864
Filing Dt:
11/17/2005
Publication #:
US20070111333
Pub Dt:
05/17/2007
Title:
METHOD FOR MANUFACTURING A RESISTIVELY SWITCHING MEMORY CELL AND MEMORY DEVICE BASED THEREON
5
Patent #:
7502916
Issue Dt:
03/10/2009
Application #:
11292948
Filing Dt:
12/02/2005
Publication #:
US20070130449
Pub Dt:
06/07/2007
Title:
PROCESSING ARRANGEMENT, MEMORY CARD DEVICE AND METHOD FOR OPERATING AND MANUFACTURING A PROCESSING ARRANGEMENT
6
Patent #:
7394128
Issue Dt:
07/01/2008
Application #:
11304062
Filing Dt:
12/15/2005
Publication #:
US20070138516
Pub Dt:
06/21/2007
Title:
SEMICONDUCTOR MEMORY DEVICE WITH CHANNEL REGIONS ALONG SIDEWALLS OF FINS
7
Patent #:
7359271
Issue Dt:
04/15/2008
Application #:
11313650
Filing Dt:
12/22/2005
Publication #:
US20070147153
Pub Dt:
06/28/2007
Title:
GATE INDUCED DRAIN LEAKAGE CURRENT REDUCTION BY VOLTAGE REGULATION OF MASTER WORDLINE
8
Patent #:
7397727
Issue Dt:
07/08/2008
Application #:
11314529
Filing Dt:
12/22/2005
Publication #:
US20070147142
Pub Dt:
06/28/2007
Title:
WRITE BURST STOP FUNCTION IN LOW POWER DDR SDRAM
9
Patent #:
7518902
Issue Dt:
04/14/2009
Application #:
11318331
Filing Dt:
12/23/2005
Publication #:
US20070171697
Pub Dt:
07/26/2007
Title:
RESISTIVE MEMORY DEVICE AND METHOD FOR WRITING TO A RESISTIVE MEMORY CELL IN A RESISTIVE MEMORY DEVICE
10
Patent #:
7405957
Issue Dt:
07/29/2008
Application #:
11320266
Filing Dt:
12/28/2005
Publication #:
US20070165439
Pub Dt:
07/19/2007
Title:
EDGE PAD ARCHITECTURE FOR SEMICONDUCTOR MEMORY
11
Patent #:
7371645
Issue Dt:
05/13/2008
Application #:
11321450
Filing Dt:
12/30/2005
Publication #:
US20070155119
Pub Dt:
07/05/2007
Title:
METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR DEVICE WITH RECESSED CHANNEL AND CORNER GATE DEVICE
12
Patent #:
7257038
Issue Dt:
08/14/2007
Application #:
11322252
Filing Dt:
01/03/2006
Publication #:
US20070153596
Pub Dt:
07/05/2007
Title:
TEST MODE FOR IPP CURRENT MEASUREMENT FOR WORDLINE DEFECT DETECTION
13
Patent #:
7292466
Issue Dt:
11/06/2007
Application #:
11324700
Filing Dt:
01/03/2006
Publication #:
US20070153563
Pub Dt:
07/05/2007
Title:
INTEGRATED CIRCUIT HAVING A RESISTIVE MEMORY
14
Patent #:
7499344
Issue Dt:
03/03/2009
Application #:
11326235
Filing Dt:
01/05/2006
Publication #:
US20070153569
Pub Dt:
07/05/2007
Title:
INTEGRATED CIRCUIT MEMORY HAVING A READ CIRCUIT
15
Patent #:
7378727
Issue Dt:
05/27/2008
Application #:
11327054
Filing Dt:
01/06/2006
Publication #:
US20070158688
Pub Dt:
07/12/2007
Title:
MEMORY DEVICE AND A METHOD OF FORMING A MEMORY DEVICE
16
Patent #:
7359252
Issue Dt:
04/15/2008
Application #:
11327354
Filing Dt:
01/09/2006
Publication #:
US20070162685
Pub Dt:
07/12/2007
Title:
MEMORY DATA BUS STRUCTURE AND METHOD OF TRANSFERRING INFORMATION WITH PLURAL MEMORY BANKS
17
Patent #:
7362632
Issue Dt:
04/22/2008
Application #:
11333037
Filing Dt:
01/17/2006
Publication #:
US20070165469
Pub Dt:
07/19/2007
Title:
TEST PARALLELISM INCREASE BY TESTER CONTROLLABLE SWITCHING OF CHIP SELECT GROUPS
18
Patent #:
7490177
Issue Dt:
02/10/2009
Application #:
11337754
Filing Dt:
01/23/2006
Publication #:
US20070174602
Pub Dt:
07/26/2007
Title:
SYSTEM METHOD FOR PERFORMING A DIRECT MEMORY ACCESS FOR AUTOMATICALLY COPYING INITIALIZATION BOOT CODE IN A NEW MEMORY ARCHITECTURE
19
Patent #:
7449739
Issue Dt:
11/11/2008
Application #:
11339744
Filing Dt:
01/25/2006
Publication #:
US20070170487
Pub Dt:
07/26/2007
Title:
STORAGE CAPACITOR FOR SEMICONDUCTOR MEMORY CELLS AND METHOD OF MANUFACTURING A STORAGE CAPACITOR
20
Patent #:
7620136
Issue Dt:
11/17/2009
Application #:
11346905
Filing Dt:
02/03/2006
Publication #:
US20070183553
Pub Dt:
08/09/2007
Title:
CLOCK AND DATA RECOVERY CIRCUIT HAVING GAIN CONTROL
21
Patent #:
7461186
Issue Dt:
12/02/2008
Application #:
11346993
Filing Dt:
02/03/2006
Publication #:
US20070186124
Pub Dt:
08/09/2007
Title:
DATA HANDOVER UNIT FOR TRANSFERRING DATA BETWEEN DIFFERENT CLOCK DOMAINS BY PARALLELLY READING OUT DATA BITS FROM A PLURALITY OF STORAGE ELEMENTS
22
Patent #:
7451263
Issue Dt:
11/11/2008
Application #:
11349631
Filing Dt:
02/08/2006
Publication #:
US20070186061
Pub Dt:
08/09/2007
Title:
SHARED INTERFACE FOR COMPONENTS IN AN EMBEDDED SYSTEM
23
Patent #:
7383144
Issue Dt:
06/03/2008
Application #:
11354955
Filing Dt:
02/16/2006
Publication #:
US20070189355
Pub Dt:
08/16/2007
Title:
METHOD AND APPARATUS FOR CALIBRATION OF AN ON-CHIP TEMPERATURE SENSOR WITHIN A MEMORY DEVICE
24
Patent #:
7333382
Issue Dt:
02/19/2008
Application #:
11354985
Filing Dt:
02/16/2006
Publication #:
US20070189095
Pub Dt:
08/16/2007
Title:
METHOD AND APPARATUS FOR AN OSCILLATOR WITHIN A MEMORY DEVICE
25
Patent #:
7324365
Issue Dt:
01/29/2008
Application #:
11366370
Filing Dt:
03/02/2006
Publication #:
US20070230237
Pub Dt:
10/04/2007
Title:
PHASE CHANGE MEMORY FABRICATED USING SELF-ALIGNED PROCESSING
26
Patent #:
7495946
Issue Dt:
02/24/2009
Application #:
11366706
Filing Dt:
03/02/2006
Publication #:
US20070230238
Pub Dt:
10/04/2007
Title:
PHASE CHANGE MEMORY FABRICATED USING SELF-ALIGNED PROCESSING
27
Patent #:
7342819
Issue Dt:
03/11/2008
Application #:
11368266
Filing Dt:
03/03/2006
Publication #:
US20070206402
Pub Dt:
09/06/2007
Title:
METHODS FOR GENERATING A REFERENCE VOLTAGE AND FOR READING A MEMORY CELL AND CIRCUIT CONFIGURATIONS IMPLEMENTING THE METHODS
28
Patent #:
7474552
Issue Dt:
01/06/2009
Application #:
11370172
Filing Dt:
03/08/2006
Publication #:
US20070211552
Pub Dt:
09/13/2007
Title:
INTEGRATED SEMICONDUCTOR MEMORY DEVICE
29
Patent #:
7270922
Issue Dt:
09/18/2007
Application #:
11371237
Filing Dt:
03/09/2006
Publication #:
US20070212624
Pub Dt:
09/13/2007
Title:
METHOD FOR DETERMINING AN EDGE PROFILE OF A VOLUME OF A PHOTORESIST AFTER A DEVELOPMENT PROCESS
30
Patent #:
7522444
Issue Dt:
04/21/2009
Application #:
11374413
Filing Dt:
03/13/2006
Publication #:
US20070211514
Pub Dt:
09/13/2007
Title:
MEMORY CIRCUIT, METHOD FOR OPERATING A MEMORY CIRCUIT, MEMORY DEVICE AND METHOD FOR PRODUCING A MEMORY DEVICE
31
Patent #:
7423906
Issue Dt:
09/09/2008
Application #:
11375365
Filing Dt:
03/14/2006
Publication #:
US20070217252
Pub Dt:
09/20/2007
Title:
Integrated Circuit Having A Memory Cell
32
Patent #:
7662721
Issue Dt:
02/16/2010
Application #:
11376645
Filing Dt:
03/15/2006
Publication #:
US20070215986
Pub Dt:
09/20/2007
Title:
HARD MASK LAYER STACK AND A METHOD OF PATTERNING
33
Patent #:
7474555
Issue Dt:
01/06/2009
Application #:
11378201
Filing Dt:
03/17/2006
Publication #:
US20070217318
Pub Dt:
09/20/2007
Title:
INTERGRATED CIRCUIT INCLUDING RESISTIVITY CHANGING MATERIAL ELEMENT
34
Patent #:
7362633
Issue Dt:
04/22/2008
Application #:
11385340
Filing Dt:
03/21/2006
Publication #:
US20070223293
Pub Dt:
09/27/2007
Title:
PARALLEL READ FOR FRONT END COMPRESSION MODE
35
Patent #:
7272063
Issue Dt:
09/18/2007
Application #:
11386048
Filing Dt:
03/21/2006
Publication #:
US20070223299
Pub Dt:
09/27/2007
Title:
MEMORY WITH A TEMPERATURE SENSOR, DYNAMIC MEMORY AND MEMORY WITH A CLOCK UNIT AND METHOD OF SENSING A TEMPERATURE OF A MEMORY
36
Patent #:
7457913
Issue Dt:
11/25/2008
Application #:
11386176
Filing Dt:
03/22/2006
Publication #:
US20070245096
Pub Dt:
10/18/2007
Title:
FINDING A DATA PATTERN IN A MEMORY
37
Patent #:
7415569
Issue Dt:
08/19/2008
Application #:
11386360
Filing Dt:
03/22/2006
Publication #:
US20070226429
Pub Dt:
09/27/2007
Title:
MEMORY INCLUDING A WRITE TRAINING BLOCK
38
Patent #:
7454559
Issue Dt:
11/18/2008
Application #:
11386377
Filing Dt:
03/22/2006
Publication #:
US20070226430
Pub Dt:
09/27/2007
Title:
FILTERING BIT POSITION IN A MEMORY
39
Patent #:
7565466
Issue Dt:
07/21/2009
Application #:
11386510
Filing Dt:
03/22/2006
Publication #:
US20070260781
Pub Dt:
11/08/2007
Title:
MEMORY INCLUDING AN OUTPUT POINTER CIRCUIT
40
Patent #:
7492648
Issue Dt:
02/17/2009
Application #:
11387879
Filing Dt:
03/24/2006
Publication #:
US20070223302
Pub Dt:
09/27/2007
Title:
REDUCING LEAKAGE CURRENT IN MEMORY DEVICE USING BITLINE ISOLATION
41
Patent #:
7361974
Issue Dt:
04/22/2008
Application #:
11388234
Filing Dt:
03/23/2006
Publication #:
US20070224810
Pub Dt:
09/27/2007
Title:
MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE
42
Patent #:
7531867
Issue Dt:
05/12/2009
Application #:
11390983
Filing Dt:
03/27/2006
Publication #:
US20070224759
Pub Dt:
09/27/2007
Title:
METHOD FOR FORMING AN INTEGRATED MEMORY DEVICE AND MEMORY DEVICE
43
Patent #:
7408222
Issue Dt:
08/05/2008
Application #:
11390997
Filing Dt:
03/27/2006
Publication #:
US20070221988
Pub Dt:
09/27/2007
Title:
CHARGE TRAPPING DEVICE AND METHOD OF PRODUCING THE CHARGE TRAPPING DEVICE
44
Patent #:
7379383
Issue Dt:
05/27/2008
Application #:
11397429
Filing Dt:
04/04/2006
Publication #:
US20070230266
Pub Dt:
10/04/2007
Title:
METHODS OF DDR RECEIVER READ RE-SYNCHRONIZATION
45
Patent #:
7345899
Issue Dt:
03/18/2008
Application #:
11400742
Filing Dt:
04/07/2006
Publication #:
US20070247898
Pub Dt:
10/25/2007
Title:
MEMORY HAVING STORAGE LOCATIONS WITHIN A COMMON VOLUME OF PHASE CHANGE MATERIAL
46
Patent #:
7564718
Issue Dt:
07/21/2009
Application #:
11402649
Filing Dt:
04/12/2006
Publication #:
US20070242518
Pub Dt:
10/18/2007
Title:
METHOD FOR PROGRAMMING A BLOCK OF MEMORY CELLS, NON-VOLATILE MEMORY DEVICE AND MEMORY CARD DEVICE
47
Patent #:
7310010
Issue Dt:
12/18/2007
Application #:
11403453
Filing Dt:
04/13/2006
Publication #:
US20070241799
Pub Dt:
10/18/2007
Title:
DUTY CYCLE CORRECTOR
48
Patent #:
8896045
Issue Dt:
11/25/2014
Application #:
11406766
Filing Dt:
04/19/2006
Publication #:
US20070246782
Pub Dt:
10/25/2007
Title:
INTEGRATED CIRCUIT INCLUDING SIDEWALL SPACER
49
Patent #:
7495971
Issue Dt:
02/24/2009
Application #:
11406803
Filing Dt:
04/19/2006
Publication #:
US20070247892
Pub Dt:
10/25/2007
Title:
CIRCUIT AND A METHOD OF DETERMINING THE RESISTIVE STATE OF A RESISTIVE MEMORY CELL
50
Patent #:
7405996
Issue Dt:
07/29/2008
Application #:
11408647
Filing Dt:
04/21/2006
Publication #:
US20070247960
Pub Dt:
10/25/2007
Title:
SYSTEM AND METHOD TO SYNCHRONIZE SIGNALS IN INDIVIDUAL INTEGRATED CIRCUIT COMPONENTS
51
Patent #:
7420862
Issue Dt:
09/02/2008
Application #:
11410635
Filing Dt:
04/25/2006
Publication #:
US20070250657
Pub Dt:
10/25/2007
Title:
DATA INVERSION DEVICE AND METHOD
52
Patent #:
7548448
Issue Dt:
06/16/2009
Application #:
11411317
Filing Dt:
04/26/2006
Publication #:
US20070047160
Pub Dt:
03/01/2007
Title:
INTEGRATED CIRCUIT HAVING A SWITCH
53
Patent #:
7403439
Issue Dt:
07/22/2008
Application #:
11414364
Filing Dt:
05/01/2006
Publication #:
US20070253265
Pub Dt:
11/01/2007
Title:
BITLINE LEAKAGE LIMITING WITH IMPROVED VOLTAGE REGULATION
54
Patent #:
7678679
Issue Dt:
03/16/2010
Application #:
11414553
Filing Dt:
05/01/2006
Publication #:
US20070254442
Pub Dt:
11/01/2007
Title:
VERTICAL DEVICE WITH SIDEWALL SPACER, METHODS OF FORMING SIDEWALL SPACERS AND FIELD EFFECT TRANSISTORS, AND PATTERNING METHOD
55
Patent #:
7414899
Issue Dt:
08/19/2008
Application #:
11414570
Filing Dt:
04/28/2006
Publication #:
US20070253262
Pub Dt:
11/01/2007
Title:
METHOD AND APPARATUS FOR EARLY WRITE TERMINATION IN A SEMICONDUCUTOR MEMORY
56
Patent #:
7460394
Issue Dt:
12/02/2008
Application #:
11436358
Filing Dt:
05/18/2006
Publication #:
US20070280023
Pub Dt:
12/06/2007
Title:
PHASE CHANGE MEMORY HAVING TEMPERATURE BUDGET SENSOR
57
Patent #:
7714315
Issue Dt:
05/11/2010
Application #:
11437211
Filing Dt:
05/19/2006
Publication #:
US20070181932
Pub Dt:
08/09/2007
Title:
THERMAL ISOLATION OF PHASE CHANGE MEMORY CELLS
58
Patent #:
7416952
Issue Dt:
08/26/2008
Application #:
11438700
Filing Dt:
05/23/2006
Publication #:
US20070272965
Pub Dt:
11/29/2007
Title:
METHOD FOR PRODUCING A DIELECTRIC INTERLAYER AND STORAGE CAPACITOR WITH SUCH A DIELECTRIC INTERLAYER
59
Patent #:
7315454
Issue Dt:
01/01/2008
Application #:
11439443
Filing Dt:
05/24/2006
Publication #:
US20070096302
Pub Dt:
05/03/2007
Title:
SEMICONDUCTOR MEMORY MODULE
60
Patent #:
7589019
Issue Dt:
09/15/2009
Application #:
11443432
Filing Dt:
05/31/2006
Publication #:
US20070278546
Pub Dt:
12/06/2007
Title:
MEMORY CELL ARRAY AND METHOD OF FORMING A MEMORY CELL ARRAY
61
Patent #:
7434121
Issue Dt:
10/07/2008
Application #:
11443493
Filing Dt:
05/30/2006
Publication #:
US20070300106
Pub Dt:
12/27/2007
Title:
INTEGRATED MEMORY DEVICE AND METHOD FOR ITS TESTING AND MANUFACTURE
62
Patent #:
7374992
Issue Dt:
05/20/2008
Application #:
11443602
Filing Dt:
05/31/2006
Publication #:
US20070281416
Pub Dt:
12/06/2007
Title:
MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE
63
Patent #:
7626190
Issue Dt:
12/01/2009
Application #:
11445801
Filing Dt:
06/02/2006
Publication #:
US20070278530
Pub Dt:
12/06/2007
Title:
MEMORY DEVICE, IN PARTICULAR PHASE CHANGE RANDOM ACCESS MEMORY DEVICE WITH TRANSISTOR, AND METHOD FOR FABRICATING A MEMORY DEVICE
64
Patent #:
7649242
Issue Dt:
01/19/2010
Application #:
11452417
Filing Dt:
06/14/2006
Publication #:
US20070267667
Pub Dt:
11/22/2007
Title:
PROGRAMMABLE RESISTIVE MEMORY CELL WITH A PROGRAMMABLE RESISTANCE LAYER
65
Patent #:
7447107
Issue Dt:
11/04/2008
Application #:
11453946
Filing Dt:
06/15/2006
Publication #:
US20070297268
Pub Dt:
12/27/2007
Title:
RANDOM ACCESS MEMORY INCLUDING MULTIPLE STATE MACHINES
66
Patent #:
7457146
Issue Dt:
11/25/2008
Application #:
11455340
Filing Dt:
06/19/2006
Publication #:
US20070297221
Pub Dt:
12/27/2007
Title:
MEMORY CELL PROGRAMMED USING A TEMPERATURE CONTROLLED SET PULSE
67
Patent #:
7441070
Issue Dt:
10/21/2008
Application #:
11456063
Filing Dt:
07/06/2006
Publication #:
US20080010418
Pub Dt:
01/10/2008
Title:
METHOD FOR ACCESSING A NON-VOLATILE MEMORY VIA A VOLATILE MEMORY INTERFACE
68
Patent #:
7439761
Issue Dt:
10/21/2008
Application #:
11457133
Filing Dt:
07/12/2006
Publication #:
US20080012598
Pub Dt:
01/17/2008
Title:
APPARATUS AND METHOD FOR CONTROLLING A DRIVER STRENGTH
69
Patent #:
7966469
Issue Dt:
06/21/2011
Application #:
11464215
Filing Dt:
08/14/2006
Publication #:
US20090106504
Pub Dt:
04/23/2009
Title:
MEMORY SYSTEM AND METHOD FOR OPERATING A MEMORY SYSTEM
70
Patent #:
7928590
Issue Dt:
04/19/2011
Application #:
11464784
Filing Dt:
08/15/2006
Publication #:
US20080042261
Pub Dt:
02/21/2008
Title:
INTEGRATED CIRCUIT PACKAGE WITH A HEAT DISSIPATION DEVICE
71
Patent #:
7886122
Issue Dt:
02/08/2011
Application #:
11466312
Filing Dt:
08/22/2006
Publication #:
US20080052481
Pub Dt:
02/28/2008
Title:
METHOD AND CIRCUIT FOR TRANSMITTING A MEMORY CLOCK SIGNAL
72
Patent #:
7359226
Issue Dt:
04/15/2008
Application #:
11467747
Filing Dt:
08/28/2006
Publication #:
US20080049486
Pub Dt:
02/28/2008
Title:
TRANSISTOR, MEMORY CELL ARRAY AND METHOD FOR FORMING AND OPERATING A MEMORY DEVICE
73
Patent #:
7420841
Issue Dt:
09/02/2008
Application #:
11468465
Filing Dt:
08/30/2006
Publication #:
US20080055987
Pub Dt:
03/06/2008
Title:
MEMORY DEVICE AND METHOD FOR TRANSFORMING BETWEEN NON-POWER-OF-2 LEVELS OF MULTILEVEL MEMORY CELLS AND 2-LEVEL DATA BITS
74
Patent #:
7409308
Issue Dt:
08/05/2008
Application #:
11469365
Filing Dt:
08/31/2006
Publication #:
US20080059102
Pub Dt:
03/06/2008
Title:
METHOD AND DEVICE FOR VERIFYING OUTPUT SIGNALS OF AN INTEGRATED CIRCUIT
75
Patent #:
8038850
Issue Dt:
10/18/2011
Application #:
11473441
Filing Dt:
06/23/2006
Publication #:
US20070295597
Pub Dt:
12/27/2007
Title:
SPUTTER DEPOSITION METHOD FOR FORMING INTEGRATED CIRCUIT
76
Patent #:
7476980
Issue Dt:
01/13/2009
Application #:
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Assignor
1
INFINEON TECHNOLOGIES AG
Exec Dt:
07/08/2015
Assignee
1
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE
DUBLIN 2, IRELAND
Correspondence name and address
POLARIS INNOVATIONS LIMITED
303 TERRY FOX DRIVE
SUITE 300
OTTAWA, K2K 3J1 CANADA

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