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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037221/0885   Pages: 8
Recorded: 12/07/2015
Attorney Dkt #:5649-4420
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 57
1
Patent #:
Issue Dt:
12/28/1999
Application #:
08618161
Filing Dt:
03/19/1996
Title:
ETCHING HIGH ASPECT CONTACT HOLES IN SOLID STATE DEVICES
2
Patent #:
Issue Dt:
07/07/1998
Application #:
08642983
Filing Dt:
05/06/1996
Title:
CRACK STOP FORMATION FOR HIGH-PRODUCTIVITY PROCESSES
3
Patent #:
Issue Dt:
07/07/1998
Application #:
08777156
Filing Dt:
12/26/1996
Title:
PAD STACK WITH A POLY SI ETCH STOP FOR TEOS MASK REMOVAL WITH RIE
4
Patent #:
Issue Dt:
08/04/1998
Application #:
08823668
Filing Dt:
03/24/1997
Title:
CRACK STOPS
5
Patent #:
Issue Dt:
07/25/2000
Application #:
09007911
Filing Dt:
01/15/1998
Title:
DUMMY PATTERNS FOR ALUMINUM CHEMICAL POLISHING (CMP)
6
Patent #:
Issue Dt:
01/30/2001
Application #:
09037289
Filing Dt:
03/09/1998
Title:
REDUCED VOLTAGE INPUT/REDUCED VOLTAGE OUTPUT TRI-STATE BUFFERS
7
Patent #:
Issue Dt:
03/22/2005
Application #:
09052688
Filing Dt:
03/31/1998
Title:
DEVICE INTERCONNECTION
8
Patent #:
Issue Dt:
02/15/2000
Application #:
09061538
Filing Dt:
04/16/1998
Title:
CRACK STOPS
9
Patent #:
Issue Dt:
11/09/1999
Application #:
09061565
Filing Dt:
04/16/1998
Title:
REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE
10
Patent #:
Issue Dt:
12/07/1999
Application #:
09078517
Filing Dt:
05/15/1998
Title:
GEOMETRICAL CONTROL OF DEVICE CORNER THRESHOLD
11
Patent #:
Issue Dt:
03/14/2000
Application #:
09105647
Filing Dt:
06/26/1998
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A CONDUCTIVE FUSE AND PROCESS FOR FABRICATION THEREOF
12
Patent #:
Issue Dt:
02/08/2000
Application #:
09120190
Filing Dt:
07/22/1998
Title:
GEOMETRICAL CONTROL OF DEVICE CORNER THRESHOLD
13
Patent #:
Issue Dt:
08/01/2000
Application #:
09130324
Filing Dt:
08/06/1998
Title:
A METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURES INCLUDING A PAIR OF MOSFETS
14
Patent #:
Issue Dt:
12/28/1999
Application #:
09140573
Filing Dt:
08/26/1998
Title:
ELECTRICAL FUSES WITH TIGHT PITCHES AND METHOD OF FABRICATION IN SEMICONDUCTORS
15
Patent #:
Issue Dt:
02/01/2005
Application #:
09204706
Filing Dt:
12/03/1998
Publication #:
Pub Dt:
07/05/2001
Title:
REMOVAL OF POST-RIE POLYMER ON A1/CU METAL LINE
16
Patent #:
Issue Dt:
04/18/2000
Application #:
09218561
Filing Dt:
12/22/1998
Title:
A REPAIRABLE SEMICONDUCTOR MEMORY CIRCUIT HAVING PARALLEL REDUNDANCY REPLACEMENT WHEREIN REDUNDANCY ELEMENTS REPLACE FAILED ELEMENTS
17
Patent #:
Issue Dt:
08/07/2001
Application #:
09218882
Filing Dt:
12/22/1998
Title:
CRACK STOPS
18
Patent #:
Issue Dt:
10/03/2000
Application #:
09225664
Filing Dt:
01/05/1999
Title:
DRIVER CIRCUIT WITH NEGATIVE LOWER POWER RAIL
19
Patent #:
Issue Dt:
07/04/2000
Application #:
09241741
Filing Dt:
12/22/1998
Title:
CRACK STOPS
20
Patent #:
Issue Dt:
07/17/2001
Application #:
09257304
Filing Dt:
02/25/1999
Title:
DYNAMIC LOGIC CIRCUIT
21
Patent #:
Issue Dt:
07/11/2000
Application #:
09265252
Filing Dt:
03/09/1999
Title:
CURRENT SOURCE
22
Patent #:
Issue Dt:
04/10/2001
Application #:
09265253
Filing Dt:
03/09/1999
Title:
CAPACITIVE COUPLED DRIVER CIRCUIT
23
Patent #:
Issue Dt:
06/27/2000
Application #:
09333539
Filing Dt:
06/15/1999
Title:
HIERARCHICAL PREFETCH FOR SEMICONDUCTOR MEMORIES
24
Patent #:
Issue Dt:
12/23/2003
Application #:
09377588
Filing Dt:
08/19/1999
Title:
SYNCHRONIZED DATA CAPTURING CIRCUITS USING REDUCED VOLTAGE LEVELS AND METHODS THEREFOR
25
Patent #:
Issue Dt:
05/25/2004
Application #:
09408248
Filing Dt:
09/29/1999
Title:
SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
26
Patent #:
Issue Dt:
03/04/2003
Application #:
09425329
Filing Dt:
10/22/1999
Title:
PREFETCH ARCHITECTURES FOR DATA AND TIME SIGNALS IN AN INTEGRATED CIRCUIT AND METHODS THEREFOR
27
Patent #:
Issue Dt:
05/15/2001
Application #:
09442890
Filing Dt:
11/18/1999
Title:
OPTIMIZED DECOUPLING CAPACITOR USING LITHOGRAPHIC DUMMY FILLER
28
Patent #:
Issue Dt:
05/22/2001
Application #:
09458878
Filing Dt:
12/10/1999
Title:
HIGH PERFORMANCE CMOS WORD-LINE DRIVER
29
Patent #:
Issue Dt:
08/14/2001
Application #:
09519104
Filing Dt:
03/06/2000
Title:
Receiver with switched current feedback for controlled hysteresis
30
Patent #:
Issue Dt:
02/27/2001
Application #:
09536185
Filing Dt:
03/24/2000
Title:
Cbr refresh control for the redundancy array
31
Patent #:
Issue Dt:
03/05/2002
Application #:
09562220
Filing Dt:
04/28/2000
Title:
Optimized decoupling capacitor using lithographic dummy filler
32
Patent #:
Issue Dt:
03/19/2002
Application #:
09596097
Filing Dt:
06/16/2000
Title:
Orientation independent oxidation of silicon
33
Patent #:
Issue Dt:
10/08/2002
Application #:
09597121
Filing Dt:
06/20/2000
Title:
POWER CONTROLLED INPUT RECEIVER
34
Patent #:
Issue Dt:
05/28/2002
Application #:
09597401
Filing Dt:
06/21/2000
Title:
DESIGN LAYOUT FOR A DENSE MEMORY CELL STRUCTURE
35
Patent #:
Issue Dt:
08/12/2003
Application #:
09597442
Filing Dt:
06/20/2000
Title:
SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS
36
Patent #:
Issue Dt:
10/21/2003
Application #:
09662424
Filing Dt:
09/14/2000
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATION INCLUDING FORMING ALUMINUM COLUMNS
37
Patent #:
Issue Dt:
07/30/2002
Application #:
09676864
Filing Dt:
09/29/2000
Title:
BUFFERS WITH REDUCED VOLTAGE INPUT/OUTPUT SIGNALS
38
Patent #:
Issue Dt:
12/10/2002
Application #:
09717970
Filing Dt:
11/21/2000
Title:
METHOD FOR ELIMINATING CRACK DAMAGE INDUCED BY DELAMINATING GATE CONDUCTOR INTERFACES IN INTEGRATED CIRCUITS
39
Patent #:
Issue Dt:
12/17/2002
Application #:
09772377
Filing Dt:
01/30/2001
Publication #:
Pub Dt:
08/01/2002
Title:
MULTI-LEVEL FUSE STRUCTURE
40
Patent #:
Issue Dt:
03/11/2003
Application #:
09928209
Filing Dt:
08/10/2001
Publication #:
Pub Dt:
02/13/2003
Title:
METHOD FOR LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF LOW-K FILMS USING SELECTED CYCLOSILOXANE AND OZONE GASES FOR SEMICONDUCTOR APPLICATIONS
41
Patent #:
Issue Dt:
01/20/2004
Application #:
09964208
Filing Dt:
09/26/2001
Publication #:
Pub Dt:
03/27/2003
Title:
UNIT-ARCHITECTURE WITH IMPLEMENTED LIMITED BANK-COLUMN-SELECT REPAIRABILITY
42
Patent #:
Issue Dt:
12/02/2003
Application #:
09965919
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/10/2003
Title:
GATE PROCESSING METHOD WITH REDUCED GATE OXIDE CORNER AND EDGE THINNING
43
Patent #:
Issue Dt:
11/18/2003
Application #:
09994340
Filing Dt:
11/26/2001
Publication #:
Pub Dt:
05/29/2003
Title:
PROCESS FOR FORMING A DAMASCENE STRUCTURE
44
Patent #:
Issue Dt:
05/27/2003
Application #:
10034626
Filing Dt:
12/27/2001
Title:
TWISTED BIT-LINE COMPENSATION FOR DRAM HAVING REDUNDANCY
45
Patent #:
Issue Dt:
06/10/2003
Application #:
10075152
Filing Dt:
02/14/2002
Title:
RTCVD PROCESS AND REACTOR FOR IMPROVED CONFORMALITY AND STEP-COVERAGE
46
Patent #:
Issue Dt:
02/10/2004
Application #:
10114195
Filing Dt:
04/02/2002
Publication #:
Pub Dt:
10/02/2003
Title:
REPEATER WITH REDUCED POWER CONSUMPTION
47
Patent #:
Issue Dt:
05/25/2004
Application #:
10206875
Filing Dt:
07/29/2002
Publication #:
Pub Dt:
01/29/2004
Title:
METHOD TO ENHANCE EPI-REGROWTH IN AMORPHOUS POLY CB CONTACTS
48
Patent #:
Issue Dt:
03/15/2005
Application #:
10338517
Filing Dt:
01/08/2003
Publication #:
Pub Dt:
07/22/2004
Title:
REDUCED HOT CARRIER INDUCED PARASITIC SIDEWALL DEVICE ACTIVATION IN ISOLATED BURIED CHANNEL DEVICES BY CONDUCTIVE BURIED CHANNEL DEPTH OPTIMIZATION
49
Patent #:
Issue Dt:
09/18/2007
Application #:
10408339
Filing Dt:
04/07/2003
Publication #:
Pub Dt:
10/07/2004
Title:
ADHESION LAYER FOR PT ON SIO2
50
Patent #:
Issue Dt:
04/19/2005
Application #:
10447018
Filing Dt:
05/28/2003
Publication #:
Pub Dt:
12/02/2004
Title:
METHODS AND APPARATUS FOR PROVIDING AN ANTIFUSE FUNCTION
51
Patent #:
Issue Dt:
08/23/2005
Application #:
10605604
Filing Dt:
10/13/2003
Publication #:
Pub Dt:
04/14/2005
Title:
METHOD FOR IMPROVED ALIGNMENT OF MAGNETIC TUNNEL JUNCTION ELEMENTS
52
Patent #:
Issue Dt:
06/02/2009
Application #:
11601304
Filing Dt:
11/17/2006
Publication #:
Pub Dt:
05/22/2008
Title:
PHASE CHANGE MEMORY CELL HAVING A SIDEWALL CONTACT
53
Patent #:
Issue Dt:
04/28/2009
Application #:
11668992
Filing Dt:
01/30/2007
Publication #:
Pub Dt:
07/31/2008
Title:
PHASE CHANGE MEMORY CELL DESIGN WITH ADJUSTED SEAM LOCATION
54
Patent #:
Issue Dt:
01/04/2011
Application #:
11843044
Filing Dt:
08/22/2007
Publication #:
Pub Dt:
02/26/2009
Title:
INTEGRATED CIRCUIT INCLUDING SILICIDE REGION TO INHIBIT PARASITIC CURRENTS
55
Patent #:
Issue Dt:
02/28/2012
Application #:
12198383
Filing Dt:
08/26/2008
Publication #:
Pub Dt:
03/04/2010
Title:
CONCENTRIC PHASE CHANGE MEMORY ELEMENT
56
Patent #:
Issue Dt:
08/18/2015
Application #:
13364727
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/31/2012
Title:
CONCENTRIC PHASE CHANGE MEMORY ELEMENT
57
Patent #:
Issue Dt:
08/18/2015
Application #:
13364727
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/31/2012
Title:
CONCENTRIC PHASE CHANGE MEMORY ELEMENT
Assignor
1
Exec Dt:
09/30/2015
Assignee
1
129, SAMSUNG-RO
YEONGTONG-GU, GYEONGGI-DO
SUWON-SI, KOREA, REPUBLIC OF 443-742
Correspondence name and address
MYERS BIGEL SIBLEY & SAJOVEC, P.A.
4140 PARKLAKE AVENUE
SUITE 600
RALEIGH, NC 27612

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