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Reel/Frame:037315/0700   Pages: 8
Recorded: 12/17/2015
Attorney Dkt #:3483.000
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 21
1
Patent #:
Issue Dt:
05/02/2000
Application #:
09061515
Filing Dt:
04/16/1998
Title:
ELIMINATION OF POLY CAP FOR EASY POLY1 CONTACT FOR NAND PRODUCT
2
Patent #:
Issue Dt:
11/06/2001
Application #:
09531582
Filing Dt:
03/21/2000
Title:
Elimination of poly cap for easy poly 1 contact for nand product
3
Patent #:
Issue Dt:
01/04/2011
Application #:
11049855
Filing Dt:
02/04/2005
Title:
NON-VOLATILE MEMORY DEVICE WITH IMPROVED ERASE SPEED
4
Patent #:
Issue Dt:
09/20/2011
Application #:
11091519
Filing Dt:
03/29/2005
Title:
ULTRAVIOLET RADIATION BLOCKING INTERLAYER DIELECTRIC
5
Patent #:
Issue Dt:
04/19/2011
Application #:
11091524
Filing Dt:
03/29/2005
Title:
FILM STACKS TO PREVENT UV-INDUCED DEVICE DAMAGE
6
Patent #:
Issue Dt:
08/17/2010
Application #:
11110165
Filing Dt:
04/20/2005
Title:
ORDERED POROSITY TO DIRECT MEMORY ELEMENT FORMATION
7
Patent #:
Issue Dt:
03/16/2010
Application #:
11128389
Filing Dt:
05/13/2005
Title:
SYSTEM AND METHOD FOR IMPROVING OXIDE-NITRIDE-OXIDE (ONO) COUPLING IN A SEMICONDUCTOR DEVICE
8
Patent #:
Issue Dt:
08/31/2010
Application #:
11136569
Filing Dt:
05/25/2005
Title:
BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME
9
Patent #:
Issue Dt:
07/26/2011
Application #:
11186969
Filing Dt:
07/22/2005
Title:
SYSTEM AND METHOD FOR IMPROVING RELIABILITY IN A SEMICONDUCTOR DEVICE
10
Patent #:
Issue Dt:
08/09/2011
Application #:
11286173
Filing Dt:
11/22/2005
Title:
INTEGRATED CIRCUIT CONTACT SYSTEM
11
Patent #:
Issue Dt:
10/18/2011
Application #:
11388976
Filing Dt:
03/27/2006
Title:
METHOD OF FORMING A CONTACT IN A SEMICONDUCTOR DEVICE WITH ENGINEERED PLASMA TREATMENT PROFILE OF BARRIER METAL LAYER
12
Patent #:
Issue Dt:
02/08/2011
Application #:
11408086
Filing Dt:
04/21/2006
Title:
GAP-FILLING WITH UNIFORM PROPERTIES
13
Patent #:
Issue Dt:
06/08/2010
Application #:
11410695
Filing Dt:
04/24/2006
Title:
METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES
14
Patent #:
Issue Dt:
04/13/2010
Application #:
11412365
Filing Dt:
04/26/2006
Title:
METHODS FOR FABRICATING FLASH MEMORY DEVICES
15
Patent #:
Issue Dt:
01/10/2012
Application #:
11521219
Filing Dt:
09/14/2006
Title:
METAL-INSULATOR-METAL-INSULATOR-METAL (MIMIM) MEMORY DEVICE
16
Patent #:
Issue Dt:
07/05/2011
Application #:
12688477
Filing Dt:
01/15/2010
Publication #:
Pub Dt:
05/13/2010
Title:
MEMORY DEVICE ETCH METHODS
17
Patent #:
Issue Dt:
01/11/2011
Application #:
12765646
Filing Dt:
04/22/2010
Publication #:
Pub Dt:
08/12/2010
Title:
METHODS FOR FABRICATING DUAL BIT FLASH MEMORY DEVICES
18
Patent #:
Issue Dt:
07/05/2011
Application #:
12887182
Filing Dt:
09/21/2010
Publication #:
Pub Dt:
01/13/2011
Title:
PLANARIZATION METHOD USING HYBRID OXIDE AND POLYSILICON CMP
19
Patent #:
Issue Dt:
12/03/2013
Application #:
12910331
Filing Dt:
10/22/2010
Publication #:
Pub Dt:
02/17/2011
Title:
SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE
20
Patent #:
Issue Dt:
12/02/2014
Application #:
13044313
Filing Dt:
03/09/2011
Publication #:
Pub Dt:
06/30/2011
Title:
METHOD FOR FORMING NARROW STRUCTURES IN A SEMICONDUCTOR DEVICE
21
Patent #:
Issue Dt:
02/17/2015
Application #:
13357252
Filing Dt:
01/24/2012
Publication #:
Pub Dt:
05/17/2012
Title:
MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD OF FABRICATING SAME
Assignor
1
Exec Dt:
12/17/2015
Assignees
1
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
2
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
3
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
4
915 DEGUIGNE DRIVE
SUNNYVALE, CALIFORNIA 94088
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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