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Total properties:
33
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Patent #:
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Issue Dt:
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01/24/1995
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Application #:
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08041924
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Filing Dt:
|
04/02/1993
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Title:
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ANTIFUSE CIRCUIT STRUCTURE FOR USE IN A FIELD PROGRAMMABLE GATE ARRAY AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
|
07/30/1996
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Application #:
|
08319170
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Filing Dt:
|
10/06/1994
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Title:
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METAL TO METAL ANTIFUSE
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|
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Patent #:
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|
Issue Dt:
|
04/14/1998
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Application #:
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08332007
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Filing Dt:
|
10/31/1994
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Title:
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VOLTAGE REGULATOR WITH HIGH GAIN CASCODE CURRENT MIRROR
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Patent #:
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|
Issue Dt:
|
12/24/1996
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Application #:
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08369760
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Filing Dt:
|
01/06/1995
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Title:
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TWO-TRANSISTOR ZERO-POWER ELECTRICALLY-ALTERABLE NON-VOLATILE LATCH
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Patent #:
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Issue Dt:
|
04/29/1997
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Application #:
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08371685
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Filing Dt:
|
01/12/1995
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Title:
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TWO-TRANSISTOR ELECTRICALLY-ALTERABLE SWITCH EMPLOYING HOT ELECTRON INJECTION AND FOWLER NORDHEIM TUNNELING
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Patent #:
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Issue Dt:
|
11/19/1996
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Application #:
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08374494
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Filing Dt:
|
01/18/1995
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Title:
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SINGLE-TRANSISTER ELECTRICALLY-ALTERABLE SWITCH EMPLOYING FOWLER NORDHEIM TUNNELING FOR PROGRAM AND ERASE
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Patent #:
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Issue Dt:
|
01/07/1997
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Application #:
|
08423518
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Filing Dt:
|
04/14/1995
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Title:
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ANTIFUSE WITH IMPROVED ANTIFUSE MATERIAL
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|
|
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Patent #:
|
|
Issue Dt:
|
04/29/1997
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Application #:
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08444243
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Filing Dt:
|
05/18/1995
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Title:
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FLEXIBLE FPGA INPUT/OUTPUT ARCHITECTURE
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|
|
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Patent #:
|
|
Issue Dt:
|
11/16/1999
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Application #:
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08472050
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Filing Dt:
|
06/06/1995
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|
Title:
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REDUCED LEAKAGE ANTIFUSE STRUCTURE
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|
|
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Patent #:
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|
Issue Dt:
|
04/28/1998
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Application #:
|
08603597
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Filing Dt:
|
02/16/1996
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Title:
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FLEXIBLE, HIGH-PERFORMANCE STATIC RAM ARCHITECTURE FOR FIELD-PROGRAMMABLE GATE ARRAYS
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|
|
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Patent #:
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|
Issue Dt:
|
09/08/1998
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Application #:
|
08657971
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Filing Dt:
|
06/04/1996
|
|
Title:
|
FABRICATION PROCESS FOR RAISED TUNGSTEN PLUG ANTIFUSE
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/04/1998
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Application #:
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08745096
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Filing Dt:
|
11/07/1996
|
|
Title:
|
ANTIFUSE WITH IMPROVED ANTIFUSE MATERIAL
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|
|
|
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Patent #:
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|
Issue Dt:
|
07/06/1999
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Application #:
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08772241
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Filing Dt:
|
12/23/1996
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|
Title:
|
RAISED TUNGSTEN PLUG ANTIFUSE AND FABRICATION PROCESSES
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|
|
|
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Patent #:
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|
Issue Dt:
|
09/28/1999
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Application #:
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08792482
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Filing Dt:
|
01/31/1997
|
|
Title:
|
FIELD PROGRAMMABLE GATE ARRAY WITH MASK PROGRAMMED INPUT AND OUTPUT BUFFERS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
10/13/1998
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Application #:
|
08792902
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Filing Dt:
|
01/31/1997
|
|
Title:
|
FIELD PROGRAMMABLE GATE ARRAY WITH MASK PROGRAMMED ANALOG FUNCTION CIRCUITS
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/10/1999
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Application #:
|
08794096
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Filing Dt:
|
02/03/1997
|
|
Title:
|
LOGIC FUNCTION MODULE FOR FIELD PROGRAMMABLE ARRAY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/01/1999
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Application #:
|
08797202
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Filing Dt:
|
02/11/1997
|
|
Title:
|
ANTIFUSE PROGRAMMED PROM CELL
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|
|
|
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Patent #:
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|
Issue Dt:
|
11/21/2000
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Application #:
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08807455
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Filing Dt:
|
02/28/1997
|
|
Title:
|
ENHANCED FIELD PROGRAMMABLE GATE ARRAY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/05/1999
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Application #:
|
08895723
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Filing Dt:
|
07/17/1997
|
|
Title:
|
IMPROVED METAL-TO-METAL VIA-TYPE ANTIFUSE
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
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08999970
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Filing Dt:
|
09/01/1995
|
|
Title:
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METHOD OF MAKING A METAL TO METAL ANTIFUSE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
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Application #:
|
09039891
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Filing Dt:
|
03/16/1998
|
|
Title:
|
EMBEDDED STATIC RANDOM ACCESS MEMORY FOR FIELD PROGRAMMABLE GATE ARRAY
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
09039923
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Filing Dt:
|
03/16/1998
|
|
Title:
|
SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09039924
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Filing Dt:
|
03/16/1998
|
|
Title:
|
CYCLIC REDUNDANCY CHECKING OF A FIELD PROGRAMMABLE GATE ARRAY HAVING AN SRAM MEMORY ARCHITECTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
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Application #:
|
09062298
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Filing Dt:
|
04/17/1998
|
|
Title:
|
RAISED TUNGSTEN PLUG ANTIFUSE AND FABRICATION PROCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
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Application #:
|
09069054
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Filing Dt:
|
04/28/1998
|
|
Title:
|
DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09153828
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Filing Dt:
|
09/15/1998
|
|
Title:
|
HIGH DENSITY ANTIFUSE BASED PARTITIONED FPGA ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09518973
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Filing Dt:
|
03/06/2000
|
|
Title:
|
Block connector splitting in logic block of a field programmable gate array
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2004
|
Application #:
|
09519311
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Filing Dt:
|
03/06/2000
|
|
Title:
|
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/24/2005
|
Application #:
|
10288778
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Filing Dt:
|
11/05/2002
|
|
Publication #:
|
|
Pub Dt:
|
06/26/2003
| | | | |
|
Title:
|
BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
10411627
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Filing Dt:
|
04/11/2003
|
|
Publication #:
|
|
Pub Dt:
|
10/30/2003
| | | | |
|
Title:
|
HIGH DENSITY ANTIFUSE BASED PARTITIONED FPGA ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10722636
|
Filing Dt:
|
11/25/2003
|
|
Title:
|
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2009
|
Application #:
|
11561695
|
Filing Dt:
|
11/20/2006
|
|
Title:
|
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2011
|
Application #:
|
12337201
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Filing Dt:
|
12/17/2008
|
|
Publication #:
|
|
Pub Dt:
|
04/09/2009
| | | | |
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Title:
|
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
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