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Reel/Frame:037393/0572   Pages: 7
Recorded: 12/28/2015
Attorney Dkt #:ACTEL #4
Conveyance: CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Total properties: 146
Page 1 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
01/14/1997
Application #:
08418972
Filing Dt:
04/07/1995
Title:
LOGIC CELL AND ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY
2
Patent #:
Issue Dt:
06/17/1997
Application #:
08506828
Filing Dt:
07/25/1995
Title:
PROGRAMMABLE NON-VOLATILE BIDIRECTIONAL SWITCH FOR PROGRAMMABLE LOGIC
3
Patent #:
Issue Dt:
05/27/1997
Application #:
08508914
Filing Dt:
07/28/1995
Title:
NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH FN TUNNELING AND PROGRAMMING METHOD THEREOF
4
Patent #:
Issue Dt:
06/02/1998
Application #:
08703683
Filing Dt:
08/27/1996
Title:
FLOATING GATE FPGA CELL WITH SELECT DEVICE ON DRAIN
5
Patent #:
Issue Dt:
06/30/1998
Application #:
08704853
Filing Dt:
08/27/1996
Title:
FLOATING GATE FGPA CELL WITH SEPARATED SELECT DEVICE
6
Patent #:
Issue Dt:
04/13/1999
Application #:
08708074
Filing Dt:
08/09/1996
Title:
FLOATING GATE FPGA CELL WITH COUNTER-DOPED SELECT DEVICE
7
Patent #:
Issue Dt:
11/17/1998
Application #:
08829374
Filing Dt:
03/31/1997
Title:
NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH FN TUNNELING IN SENSE
8
Patent #:
Issue Dt:
06/26/2001
Application #:
09138838
Filing Dt:
08/24/1998
Title:
NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH FN TUNNELING DEVICE FOR PROGRAMMING AND ERASE
9
Patent #:
Issue Dt:
10/24/2000
Application #:
09205678
Filing Dt:
12/04/1998
Title:
NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH PROGRAMMABLE BURIED SOURCE/DRAIN IN SENSE TRANSISTOR
10
Patent #:
Issue Dt:
06/06/2000
Application #:
09205876
Filing Dt:
12/04/1998
Title:
NONVOLATILE REPROGRAMMABLE INTERCONNECT CELL WITH PROGRAMMABLE BURIED BITLINE
11
Patent #:
Issue Dt:
09/26/2000
Application #:
09311975
Filing Dt:
05/14/1999
Title:
METHOD FOR ERASING NONVOLATILE MEMORY CELLS IN A FIELD PROGRAMMABLE GATE ARRAY
12
Patent #:
Issue Dt:
03/07/2006
Application #:
10021744
Filing Dt:
12/05/2001
Publication #:
Pub Dt:
06/13/2002
Title:
FLOOR PLAN FOR SCALABLE MULTIPLE LEVEL TAB ORIENTED INTERCONNECT ARCHITECTURE
13
Patent #:
Issue Dt:
08/24/2004
Application #:
10412975
Filing Dt:
04/11/2003
Publication #:
Pub Dt:
10/23/2003
Title:
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
14
Patent #:
Issue Dt:
12/02/2008
Application #:
10784903
Filing Dt:
02/20/2004
Title:
REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
15
Patent #:
Issue Dt:
12/13/2005
Application #:
10811422
Filing Dt:
03/25/2004
Publication #:
Pub Dt:
09/16/2004
Title:
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
16
Patent #:
Issue Dt:
08/14/2007
Application #:
10850568
Filing Dt:
05/19/2004
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
17
Patent #:
Issue Dt:
04/01/2008
Application #:
10857472
Filing Dt:
05/28/2004
Title:
INTEGRATED CIRCUIT DEVICE HAVING STATE-SAVING AND INITIALIZATION FEATURE
18
Patent #:
Issue Dt:
10/31/2006
Application #:
10877043
Filing Dt:
06/25/2004
Title:
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
19
Patent #:
Issue Dt:
04/18/2006
Application #:
10877045
Filing Dt:
06/25/2004
Title:
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
20
Patent #:
Issue Dt:
09/05/2006
Application #:
10898149
Filing Dt:
07/22/2004
Title:
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
21
Patent #:
Issue Dt:
09/05/2006
Application #:
10903473
Filing Dt:
07/29/2004
Title:
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
22
Patent #:
Issue Dt:
12/02/2008
Application #:
10955929
Filing Dt:
09/29/2004
Publication #:
Pub Dt:
04/06/2006
Title:
FACE-TO-FACE BONDED I/O CIRCUIT DIE AND FUNCTIONAL LOGIC CIRCUIT DIE SYSTEM
23
Patent #:
Issue Dt:
08/29/2006
Application #:
10959404
Filing Dt:
10/05/2004
Title:
SRAM CELL CONTROLLED BY NON-VOLATILE MEMORY CELL
24
Patent #:
Issue Dt:
11/21/2006
Application #:
11016699
Filing Dt:
12/17/2004
Title:
INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS
25
Patent #:
Issue Dt:
10/10/2006
Application #:
11021092
Filing Dt:
12/22/2004
Title:
POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT
26
Patent #:
Issue Dt:
09/26/2006
Application #:
11021472
Filing Dt:
12/23/2004
Publication #:
Pub Dt:
06/29/2006
Title:
NON-VOLATILE MEMORY CONFIGURATION SCHEME FOR VOLATILE-MEMORY-BASED PROGRAMMABLE CIRCUITS IN AN FPGA
27
Patent #:
Issue Dt:
10/03/2006
Application #:
11022331
Filing Dt:
12/21/2004
Publication #:
Pub Dt:
06/22/2006
Title:
VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT
28
Patent #:
Issue Dt:
10/31/2006
Application #:
11026336
Filing Dt:
12/29/2004
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
29
Patent #:
Issue Dt:
11/04/2008
Application #:
11027788
Filing Dt:
12/29/2004
Publication #:
Pub Dt:
06/29/2006
Title:
ESD PROTECTION STRUCTURE FOR I/O PAD SUBJECT TO BOTH POSITIVE AND NEGATIVE VOLTAGES
30
Patent #:
Issue Dt:
09/11/2007
Application #:
11027789
Filing Dt:
12/29/2004
Title:
SYSTEM FOR SIGNAL ROUTING LINE AGGREGATION IN A FIELD-PROGRAMMABLE GATE ARRAY
31
Patent #:
Issue Dt:
05/01/2007
Application #:
11028471
Filing Dt:
12/31/2004
Title:
FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK
32
Patent #:
Issue Dt:
05/06/2008
Application #:
11152018
Filing Dt:
06/13/2005
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
33
Patent #:
Issue Dt:
08/03/2010
Application #:
11152019
Filing Dt:
06/13/2005
Title:
ISOLATED-NITRIDE-REGION NON-VOLATILE MEMORY CELL AND FABRICATION METHOD
34
Patent #:
Issue Dt:
10/23/2007
Application #:
11155005
Filing Dt:
06/15/2005
Publication #:
Pub Dt:
12/21/2006
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
35
Patent #:
Issue Dt:
04/15/2008
Application #:
11171488
Filing Dt:
06/29/2005
Title:
ARCHITECTURE FOR FACE-TO-FACE BONDING BETWEEN SUBSTRATE AND MULTIPLE DAUGHTER CHIPS
36
Patent #:
Issue Dt:
01/09/2007
Application #:
11171489
Filing Dt:
06/29/2005
Title:
METHOD FOR ERASING PROGRAMMABLE INTERCONNECT CELLS FOR FIELD PROGRAMMABLE GATE ARRAYS USING REVERSE BIAS VOLTAGE
37
Patent #:
Issue Dt:
12/09/2008
Application #:
11185426
Filing Dt:
07/19/2005
Title:
APPARATUS AND METHOD FOR REDUCING LEAKAGE OF UNUSED BUFFERS IN AN INTEGRATED CIRCUIT
38
Patent #:
Issue Dt:
08/25/2009
Application #:
11185427
Filing Dt:
07/19/2005
Title:
METHOD FOR SECURE DELIVERY OF CONFIGURATION DATA FOR A PROGRAMMABLE LOGIC DEVICE
39
Patent #:
Issue Dt:
07/01/2008
Application #:
11195002
Filing Dt:
08/01/2005
Title:
REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
40
Patent #:
Issue Dt:
06/03/2008
Application #:
11219597
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
09/14/2006
Title:
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE
41
Patent #:
Issue Dt:
07/17/2007
Application #:
11233396
Filing Dt:
09/21/2005
Publication #:
Pub Dt:
03/22/2007
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL FOR PROGRAMMABLE LOGIC ARRAY
42
Patent #:
Issue Dt:
11/27/2007
Application #:
11251074
Filing Dt:
10/13/2005
Title:
VOLATILE DATA STORAGE IN A NON-VOLATILE MEMORY CELL ARRAY
43
Patent #:
Issue Dt:
04/22/2008
Application #:
11279046
Filing Dt:
04/07/2006
Publication #:
Pub Dt:
08/17/2006
Title:
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
44
Patent #:
Issue Dt:
03/11/2008
Application #:
11281253
Filing Dt:
11/16/2005
Publication #:
Pub Dt:
05/17/2007
Title:
BIT LINE PRE-SETTLEMENT CIRCUIT AND METHOD FOR FLASH MEMORY SENSING SCHEME
45
Patent #:
Issue Dt:
05/26/2009
Application #:
11303865
Filing Dt:
12/16/2005
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
46
Patent #:
Issue Dt:
04/22/2008
Application #:
11319751
Filing Dt:
12/27/2005
Title:
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
47
Patent #:
Issue Dt:
04/05/2011
Application #:
11336396
Filing Dt:
01/20/2006
Title:
FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NON-VOLATILE USER MEMORY AND METHOD FOR PROGRAMMING
48
Patent #:
Issue Dt:
11/20/2007
Application #:
11427717
Filing Dt:
06/29/2006
Title:
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
49
Patent #:
Issue Dt:
06/10/2008
Application #:
11460055
Filing Dt:
07/26/2006
Publication #:
Pub Dt:
11/16/2006
Title:
NON-VOLATILE MEMORY ARCHITECTURE FOR PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
50
Patent #:
Issue Dt:
11/10/2009
Application #:
11463846
Filing Dt:
08/10/2006
Title:
FLASH-BASED FPGA WITH SECURE REPROGRAMMING
51
Patent #:
Issue Dt:
10/09/2007
Application #:
11465530
Filing Dt:
08/18/2006
Title:
MIXED-SIGNAL SYSTEM-ON-A-CHIP ANALOG SIGNAL DIRECT INTERCONNECTION THROUGH PROGRAMMABLE LOGIC CONTROL
52
Patent #:
Issue Dt:
08/19/2008
Application #:
11465899
Filing Dt:
08/21/2006
Publication #:
Pub Dt:
12/14/2006
Title:
NON-VOLATILE MEMORY CONFIGURATION SCHEME FOR VOLATILE-MEMORY-BASED PROGRAMMABLE CIRCUITS IN AN FPGA
53
Patent #:
Issue Dt:
03/22/2011
Application #:
11467279
Filing Dt:
08/25/2006
Publication #:
Pub Dt:
12/21/2006
Title:
POWER-UP AND POWER-DOWN CIRCUIT FOR SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT
54
Patent #:
Issue Dt:
10/21/2008
Application #:
11467475
Filing Dt:
08/25/2006
Publication #:
Pub Dt:
12/21/2006
Title:
VOLTAGE-AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT
55
Patent #:
Issue Dt:
08/18/2009
Application #:
11502324
Filing Dt:
08/09/2006
Publication #:
Pub Dt:
12/14/2006
Title:
DISAGGREGATED STAR PLATFORM MANAGEMENT BUS ARCHITECTURE SYSTEM
56
Patent #:
Issue Dt:
09/09/2008
Application #:
11551857
Filing Dt:
10/23/2006
Publication #:
Pub Dt:
03/01/2007
Title:
SYSTEM-ON-A-CHIP INTEGRATED CIRCUIT INCLUDING DUAL-FUNCTION ANALOG AND DIGITAL INPUTS
57
Patent #:
Issue Dt:
01/22/2008
Application #:
11551973
Filing Dt:
10/23/2006
Publication #:
Pub Dt:
03/01/2007
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
58
Patent #:
Issue Dt:
08/19/2008
Application #:
11562049
Filing Dt:
11/21/2006
Title:
INTEGRATED MULTI-FUNCTION ANALOG CIRCUIT INCLUDING VOLTAGE, CURRENT, AND TEMPERATURE MONITOR AND GATE-DRIVER CIRCUIT BLOCKS
59
Patent #:
Issue Dt:
09/22/2009
Application #:
11567625
Filing Dt:
12/06/2006
Publication #:
Pub Dt:
04/26/2007
Title:
METHOD FOR ERASING PROGRAMMABLE INTERCONNECT CELLS FOR FIELD PROGRAMMABLE GATE ARRAYS USING REVERSE BIAS VOLTAGE
60
Patent #:
Issue Dt:
07/15/2008
Application #:
11612771
Filing Dt:
12/19/2006
Title:
MIXED SIGNAL SYSTEM-ON-A-CHIP INTEGRATED SIMULTANEOUS MULTIPLE SAMPLE/HOLD CIRCUITS AND EMBEDDED ANALOG COMPARATORS
61
Patent #:
Issue Dt:
07/01/2008
Application #:
11692717
Filing Dt:
03/28/2007
Publication #:
Pub Dt:
07/19/2007
Title:
FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK
62
Patent #:
Issue Dt:
05/18/2010
Application #:
11695992
Filing Dt:
04/03/2007
Publication #:
Pub Dt:
08/09/2007
Title:
INTEGRATED CIRCUIT WAFER WITH INTER-DIE METAL INTERCONNECT LINES TRAVERSING SCRIBE-LINE BOUNDARIES
63
Patent #:
Issue Dt:
08/05/2008
Application #:
11740458
Filing Dt:
04/26/2007
Publication #:
Pub Dt:
08/16/2007
Title:
SRAM CELL CONTROLLED BY FLASH MEMORY CELL
64
Patent #:
Issue Dt:
12/15/2009
Application #:
11745134
Filing Dt:
05/07/2007
Publication #:
Pub Dt:
09/06/2007
Title:
SYSTEM FOR SIGNAL ROUTING LINE AGGREGATION IN A FIELD-PROGRAMMABLE GATE ARRAY
65
Patent #:
Issue Dt:
03/11/2008
Application #:
11750650
Filing Dt:
05/18/2007
Publication #:
Pub Dt:
09/20/2007
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
66
Patent #:
Issue Dt:
09/15/2009
Application #:
11762451
Filing Dt:
06/13/2007
Publication #:
Pub Dt:
10/04/2007
Title:
NON-VOLATILE PROGRAMMABLE MEMORY CELL FOR PROGRAMMABLE LOGIC ARRAY
67
Patent #:
Issue Dt:
07/15/2008
Application #:
11769169
Filing Dt:
06/27/2007
Publication #:
Pub Dt:
12/06/2007
Title:
CIRCUIT AND METHOD FOR SUPPLYING PROGRAMMING POTENTIAL AT VOLTAGES LARGER THAN BVDSS OF PROGRAMMING TRANSISTORS
68
Patent #:
Issue Dt:
11/04/2008
Application #:
11774676
Filing Dt:
07/09/2007
Publication #:
Pub Dt:
11/01/2007
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
69
Patent #:
Issue Dt:
05/03/2011
Application #:
11829335
Filing Dt:
07/27/2007
Publication #:
Pub Dt:
01/29/2009
Title:
ERROR-DETECTING AND CORRECTING FPGA ARCHITECTURE
70
Patent #:
Issue Dt:
05/12/2009
Application #:
11833833
Filing Dt:
08/03/2007
Publication #:
Pub Dt:
02/14/2008
Title:
ADDRESS TRANSITION DETECTOR FOR FAST FLASH MEMORY DEVICE
71
Patent #:
Issue Dt:
08/05/2008
Application #:
11855974
Filing Dt:
09/14/2007
Title:
FPGA ARCHITECTURE HAVING TWO-LEVEL CLUSTER INPUT INTERCONNECT SCHEME WITHOUT BANDWIDTH LIMITATION
72
Patent #:
Issue Dt:
02/17/2009
Application #:
11858322
Filing Dt:
09/20/2007
Publication #:
Pub Dt:
01/10/2008
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
73
Patent #:
Issue Dt:
02/24/2009
Application #:
11858330
Filing Dt:
09/20/2007
Publication #:
Pub Dt:
01/10/2008
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
74
Patent #:
Issue Dt:
05/26/2009
Application #:
11858341
Filing Dt:
09/20/2007
Publication #:
Pub Dt:
01/10/2008
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
75
Patent #:
Issue Dt:
06/30/2009
Application #:
11859073
Filing Dt:
09/21/2007
Title:
NONVOLATILE MEMORY INTEGRATED CIRCUIT HAVING ASSEMBLY BUFFER AND BIT-LINE DRIVER, AND METHOD OF OPERATION THEREOF
76
Patent #:
Issue Dt:
08/11/2009
Application #:
11861504
Filing Dt:
09/26/2007
Title:
VOLATILE DATA STORAGE IN A NON-VOLATILE MEMORY CELL ARRAY
77
Patent #:
Issue Dt:
09/30/2008
Application #:
11868694
Filing Dt:
10/08/2007
Publication #:
Pub Dt:
01/31/2008
Title:
NON-VOLATILE MEMORY CELLS IN A FIELD PROGRAMMABLE GATE ARRAY
78
Patent #:
Issue Dt:
03/10/2009
Application #:
11871741
Filing Dt:
10/12/2007
Publication #:
Pub Dt:
02/07/2008
Title:
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
79
Patent #:
Issue Dt:
05/26/2009
Application #:
11927237
Filing Dt:
10/29/2007
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
80
Patent #:
Issue Dt:
01/06/2009
Application #:
11927265
Filing Dt:
10/29/2007
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
81
Patent #:
Issue Dt:
08/11/2009
Application #:
11927282
Filing Dt:
10/29/2007
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
82
Patent #:
Issue Dt:
11/10/2009
Application #:
11928428
Filing Dt:
10/30/2007
Title:
PROGRAMMABLE LOGIC DEVICE ADAPTED TO ENTER A LOW-POWER MODE
83
Patent #:
Issue Dt:
02/08/2011
Application #:
11928445
Filing Dt:
10/30/2007
Title:
PROGRAMMABLE LOGIC DEVICE ADAPTED TO ENTER A LOW-POWER MODE
84
Patent #:
Issue Dt:
10/28/2008
Application #:
11929287
Filing Dt:
10/30/2007
Title:
NON-VOLATILE LOOK-UP TABLE FOR AN FPGA
85
Patent #:
Issue Dt:
09/02/2008
Application #:
11932661
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
04/24/2008
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
86
Patent #:
Issue Dt:
02/17/2009
Application #:
11932710
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
02/28/2008
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
87
Patent #:
Issue Dt:
02/17/2009
Application #:
11932778
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
03/13/2008
Title:
PROGRAMMABLE SYSTEM ON A CHIP FOR POWER-SUPPLY VOLTAGE AND CURRENT MONITORING AND CONTROL
88
Patent #:
Issue Dt:
08/25/2009
Application #:
11932807
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
12/18/2008
Title:
CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
89
Patent #:
Issue Dt:
04/21/2009
Application #:
11932901
Filing Dt:
10/31/2007
Publication #:
Pub Dt:
02/28/2008
Title:
INTEGRATED CIRCUIT INCLUDING PROGRAMMABLE LOGIC AND EXTERNAL-DEVICE CHIP-ENABLE OVERRIDE CONTROL
90
Patent #:
Issue Dt:
04/21/2009
Application #:
11961134
Filing Dt:
12/20/2007
Title:
NON-VOLATILE MEMORY WITH SOURCE-SIDE COLUMN SELECT
91
Patent #:
Issue Dt:
04/13/2010
Application #:
11961203
Filing Dt:
12/20/2007
Title:
NON-VOLATILE MEMORY ARRAY HAVING DRAIN-SIDE SEGMENTATION FOR AN FPGA DEVICE
92
Patent #:
Issue Dt:
03/10/2009
Application #:
11962615
Filing Dt:
12/21/2007
Publication #:
Pub Dt:
04/24/2008
Title:
NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT
93
Patent #:
Issue Dt:
02/16/2010
Application #:
11962922
Filing Dt:
12/21/2007
Title:
FLEXIBLE CARRY SCHEME FOR FIELD PROGRAMMABLE GATE ARRAYS
94
Patent #:
Issue Dt:
11/10/2009
Application #:
12022064
Filing Dt:
01/29/2008
Title:
RECONFIGURABLE DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER AND CUSTOMIZED DIGITAL FILTERS WITH EMBEDDED FLASH FPGA AND FLASH MEMORY
95
Patent #:
Issue Dt:
08/14/2012
Application #:
12022721
Filing Dt:
01/30/2008
Title:
FAST CARRY LOOKAHEAD CIRCUITS
96
Patent #:
Issue Dt:
06/16/2009
Application #:
12022921
Filing Dt:
01/30/2008
Title:
ISOLATION SCHEME FOR STATIC AND DYNAMIC FPGA PARTIAL PROGRAMMING
97
Patent #:
Issue Dt:
03/23/2010
Application #:
12023299
Filing Dt:
01/31/2008
Title:
PROGRAMMABLE LOGIC DEVICE WITH A MICROCONTROLLER-BASED CONTROL SYSTEM
98
Patent #:
Issue Dt:
11/24/2009
Application #:
12024867
Filing Dt:
02/01/2008
Publication #:
Pub Dt:
06/12/2008
Title:
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY AND NON-VOLATILE MEMORY-BASED PROGRAMMABLE LOGIC DEVICE
99
Patent #:
Issue Dt:
07/14/2009
Application #:
12028615
Filing Dt:
02/08/2008
Publication #:
Pub Dt:
05/29/2008
Title:
INTEGRATED CIRCUIT DEVICE HAVING STATE-SAVING AND INITIALIZATION FEATURE
100
Patent #:
Issue Dt:
12/15/2009
Application #:
12028692
Filing Dt:
02/08/2008
Title:
HIGH-VOLTAGE DUAL-POLARITY I/O P-WELL PUMP ESD PROTECTION CIRCUIT
Assignor
1
Exec Dt:
08/23/2012
Assignee
1
3870 NORTH STREET
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
MICROSEMI CORPORATION
3870 NORTH FIRST STREET
ATT: JANET DRAKES - RECORDS MANAGER
SAN JOSE, CA 95134

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