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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037451/0611   Pages: 37
Recorded: 01/06/2016
Conveyance: MERGER (SEE DOCUMENT FOR DETAILS).
Total properties: 35
1
Patent #:
6014038
Issue Dt:
01/11/2000
Application #:
08821475
Filing Dt:
03/21/1997
Title:
FUNCTION BLOCK ARCHITECTURE FOR GATE ARRAY
2
Patent #:
6242767
Issue Dt:
06/05/2001
Application #:
08966946
Filing Dt:
11/10/1997
Title:
ASIC ROUTING ARCHITECTURE
3
Patent #:
6223313
Issue Dt:
04/24/2001
Application #:
08985790
Filing Dt:
12/05/1997
Title:
METHOD AND APPARATUS FOR CONTROLLING AND OBSERVING DATA IN A LOGIC BLOCK-BASED ASIC
4
Patent #:
6133582
Issue Dt:
10/17/2000
Application #:
09079016
Filing Dt:
05/14/1998
Title:
METHODS AND APPARATUSES FOR BINNING PARTIALLY COMPLETED INTEGRATED CIRCUITS BASED UPON TEST RESULTS
5
Patent #:
6498361
Issue Dt:
12/24/2002
Application #:
09140087
Filing Dt:
08/26/1998
Title:
DESIGN INFORMATION MEMORY FOR CONFIGURABLE INTEGRATED CIRCUITS
6
Patent #:
6770949
Issue Dt:
08/03/2004
Application #:
09144489
Filing Dt:
08/31/1998
Title:
ONE-MASK CUSTOMIZABLE PHASE-LOCKED LOOP
7
Patent #:
6399400
Issue Dt:
06/04/2002
Application #:
09272470
Filing Dt:
03/19/1999
Title:
METHODS AND APPARATUSES FOR BINNING PARTIALLY COMPLETED INTEGRATED CIRCUITS BASED UPON TEST RESULTS
8
Patent #:
6690194
Issue Dt:
02/10/2004
Application #:
09414697
Filing Dt:
10/07/1999
Title:
FUNCTION BLOCK ARCHITECTURE FOR GATE ARRAY
9
Patent #:
6694491
Issue Dt:
02/17/2004
Application #:
09512783
Filing Dt:
02/25/2000
Title:
PROGRAMMABLE LOGIC ARRAY EMBEDDED IN MASK-PROGRAMMED ASIC
10
Patent #:
6613611
Issue Dt:
09/02/2003
Application #:
09747129
Filing Dt:
12/22/2000
Title:
ASIC ROUTING ARCHITECTURE WITH VARIABLE NUMBER OF CUSTOM MASKS
11
Patent #:
7055125
Issue Dt:
05/30/2006
Application #:
09827015
Filing Dt:
04/05/2001
Publication #:
US20020059555
Pub Dt:
05/16/2002
Title:
DEPOPULATED PROGRAMMABLE LOGIC ARRAY
12
Patent #:
6769109
Issue Dt:
07/27/2004
Application #:
09877170
Filing Dt:
06/08/2001
Publication #:
US20020010903
Pub Dt:
01/24/2002
Title:
PROGRAMMABLE LOGIC ARRAY EMBEDDED IN MASK-PROGRAMMED ASIC
13
Patent #:
6696856
Issue Dt:
02/24/2004
Application #:
10020469
Filing Dt:
10/30/2001
Title:
FUNCTION BLOCK ARCHITECTURE WITH VARIABLE DRIVE STRENGTHS
14
Patent #:
6885043
Issue Dt:
04/26/2005
Application #:
10051237
Filing Dt:
01/18/2002
Publication #:
US20030155587
Pub Dt:
08/21/2003
Title:
ASIC ROUTING ARCHITECTURE
15
Patent #:
6611932
Issue Dt:
08/26/2003
Application #:
10056686
Filing Dt:
01/24/2002
Publication #:
US20020073369
Pub Dt:
06/13/2002
Title:
METHOD AND APPARATUS FOR CONTROLLING AND OBSERVING DATA IN A LOGIC BLOCK-BASED ASIC
16
Patent #:
6861867
Issue Dt:
03/01/2005
Application #:
10093767
Filing Dt:
03/07/2002
Publication #:
US20030169070
Pub Dt:
09/11/2003
Title:
METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF LOGIC CIRCUITS WITH MULTIPLE CLOCK DOMAINS
17
Patent #:
6680626
Issue Dt:
01/20/2004
Application #:
10161931
Filing Dt:
06/05/2002
Publication #:
US20030227299
Pub Dt:
12/11/2003
Title:
HIGH SPEED DIFFERENTIAL RECEIVER
18
Patent #:
7770144
Issue Dt:
08/03/2010
Application #:
10447465
Filing Dt:
05/28/2003
Publication #:
US20040243966
Pub Dt:
12/02/2004
Title:
MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC
19
Patent #:
7102237
Issue Dt:
09/05/2006
Application #:
10447466
Filing Dt:
05/28/2003
Title:
ASIC CUSTOMIZATION WITH PREDEFINED VIA MASK
20
Patent #:
6804812
Issue Dt:
10/12/2004
Application #:
10458892
Filing Dt:
06/10/2003
Publication #:
US20030212979
Pub Dt:
11/13/2003
Title:
DEPOPULATED PROGRAMMABLE LOGIC ARRAY
21
Patent #:
6954917
Issue Dt:
10/11/2005
Application #:
10460343
Filing Dt:
06/11/2003
Publication #:
US20030214324
Pub Dt:
11/20/2003
Title:
FUNCTION BLOCK ARCHITECTURE FOR GATE ARRAY AND METHOD FOR FORMING AN ASIC
22
Patent #:
7043713
Issue Dt:
05/09/2006
Application #:
10640171
Filing Dt:
08/12/2003
Publication #:
US20040049759
Pub Dt:
03/11/2004
Title:
IMPLEMENTING PROGRAMMABLE LOGIC ARRAY EMBEDDED IN MASK - PROGRAMMED ASIC
23
Patent #:
7648912
Issue Dt:
01/19/2010
Application #:
11277253
Filing Dt:
03/23/2006
Title:
ASIC CUSTOMIZATION WITH PREDEFINED VIA MASK
24
Patent #:
7461365
Issue Dt:
12/02/2008
Application #:
11456219
Filing Dt:
07/10/2006
Title:
INCREASED EFFECTIVE FLIP-FLOP DENSITY IN A STRUCTURED ASIC
25
Patent #:
7653884
Issue Dt:
01/26/2010
Application #:
11684522
Filing Dt:
03/09/2007
Publication #:
US20070150846
Pub Dt:
06/28/2007
Title:
METHODS AND SYSTEMS FOR PLACEMENT
26
Patent #:
7669160
Issue Dt:
02/23/2010
Application #:
11744758
Filing Dt:
05/04/2007
Publication #:
US20070204252
Pub Dt:
08/30/2007
Title:
METHODS AND SYSTEMS FOR PLACEMENT
27
Patent #:
7840927
Issue Dt:
11/23/2010
Application #:
11953048
Filing Dt:
12/08/2007
Title:
MUTABLE CELLS FOR USE IN INTEGRATED CIRCUITS
28
Patent #:
7814451
Issue Dt:
10/12/2010
Application #:
11967179
Filing Dt:
12/29/2007
Publication #:
US20080216040
Pub Dt:
09/04/2008
Title:
INCREMENTAL RELATIVE SLACK TIMING FORCE MODEL
29
Patent #:
7752588
Issue Dt:
07/06/2010
Application #:
11967180
Filing Dt:
12/29/2007
Publication #:
US20080216038
Pub Dt:
09/04/2008
Title:
TIMING DRIVEN FORCE DIRECTED PLACEMENT FLOW
30
Patent #:
7921392
Issue Dt:
04/05/2011
Application #:
11967184
Filing Dt:
12/29/2007
Publication #:
US20080216039
Pub Dt:
09/04/2008
Title:
NODE SPREADING VIA ARTIFICIAL DENSITY ENHANCEMENT TO REDUCE ROUTING CONGESTION
31
Patent #:
7921393
Issue Dt:
04/05/2011
Application #:
11967185
Filing Dt:
12/29/2007
Publication #:
US20080216025
Pub Dt:
09/04/2008
Title:
TUNNELING AS A BOUNDARY CONGESTION RELIEF MECHANISM
32
Patent #:
8332793
Issue Dt:
12/11/2012
Application #:
12301456
Filing Dt:
11/18/2008
Publication #:
US20090254874
Pub Dt:
10/08/2009
Title:
METHODS AND SYSTEMS FOR PLACEMENT AND ROUTING
33
Patent #:
8122413
Issue Dt:
02/21/2012
Application #:
12303938
Filing Dt:
12/08/2008
Publication #:
US20100169856
Pub Dt:
07/01/2010
Title:
TRANSPARENT TEST METHOD AND SCAN FLIP-FLOP
34
Patent #:
8176458
Issue Dt:
05/08/2012
Application #:
12325629
Filing Dt:
12/01/2008
Publication #:
US20090293035
Pub Dt:
11/26/2009
Title:
INCREASED EFFECTIVE FLIP-FLOP DENSITY IN A STRUCTURED ASIC
35
Patent #:
8504950
Issue Dt:
08/06/2013
Application #:
12842670
Filing Dt:
07/23/2010
Publication #:
US20100299648
Pub Dt:
11/25/2010
Title:
MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC
Assignor
1
OTRSOTECH, LIMITED LIABILITY COMPANY
Exec Dt:
08/26/2015
Assignee
1
CALLAHAN CELLULAR L.L.C.
2711 CENTERVILLE RD
SUITE 400
WILMINGTON, DELAWARE 19808
Correspondence name and address
SCHWABE, WILLIAMSON, & WYATT, PC
700 WASHINGTON ST.
SUITE 701
VANCOUVER, WA 98660

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