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Reel/Frame:037486/0517   Pages: 404
Recorded: 01/12/2016
Attorney Dkt #:F160353
Conveyance: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS
Total properties: 6067
Page 29 of 61
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
1
Patent #:
Issue Dt:
02/26/2008
Application #:
11300710
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
06/14/2007
Title:
ESD PROTECTION FOR PASSIVE INTEGRATED DEVICES
2
Patent #:
Issue Dt:
03/23/2010
Application #:
11302007
Filing Dt:
12/09/2005
Publication #:
Pub Dt:
06/14/2007
Title:
ELECTRONIC APPARATUS INTERCONNECT ROUTING AND INTERCONNECT ROUTING METHOD FOR MINIMIZING PARASITIC RESISTANCE
3
Patent #:
Issue Dt:
06/22/2010
Application #:
11302769
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
06/14/2007
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING DUMMY FEATURES
4
Patent #:
Issue Dt:
10/30/2007
Application #:
11302770
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
06/14/2007
Title:
SOI ACTIVE LAYER WITH DIFFERENT SURFACE ORIENTATION
5
Patent #:
Issue Dt:
11/24/2009
Application #:
11302937
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
06/14/2007
Title:
FLOATING GATE NON-VOLATILE MEMORY AND METHOD THEREOF
6
Patent #:
Issue Dt:
12/15/2009
Application #:
11303234
Filing Dt:
12/16/2005
Publication #:
Pub Dt:
06/21/2007
Title:
METHOD FOR DETERMINING TEMPERATURE PROFILE IN SEMICONDUCTOR MANUFACTURING TEST
7
Patent #:
Issue Dt:
05/27/2008
Application #:
11304196
Filing Dt:
12/14/2005
Publication #:
Pub Dt:
06/14/2007
Title:
SUPERJUNCTION POWER MOSFET
8
Patent #:
Issue Dt:
06/28/2011
Application #:
11311587
Filing Dt:
12/16/2005
Publication #:
Pub Dt:
07/12/2007
Title:
TRANSISTOR WITH IMMERSED CONTACTS AND METHODS OF FORMING THEREOF
9
Patent #:
Issue Dt:
12/25/2007
Application #:
11314203
Filing Dt:
12/20/2005
Publication #:
Pub Dt:
06/21/2007
Title:
QUIET POWER UP AND POWER DOWN OF A DIGITAL AUDIO AMPLIFIER
10
Patent #:
Issue Dt:
05/20/2008
Application #:
11315733
Filing Dt:
12/22/2005
Publication #:
Pub Dt:
07/06/2006
Title:
VOICE SIGNAL PROCESSOR
11
Patent #:
Issue Dt:
09/02/2008
Application #:
11323294
Filing Dt:
12/30/2005
Publication #:
Pub Dt:
07/05/2007
Title:
FREQUENCY MODULATED OUTPUT CLOCK FROM A DIGITAL PHASE LOCKED LOOP
12
Patent #:
Issue Dt:
09/21/2010
Application #:
11324425
Filing Dt:
01/03/2006
Publication #:
Pub Dt:
07/05/2007
Title:
ELECTRICAL SENSOR FOR REAL-TIME FEEDBACK CONTROL OF PLASMA NITRIDATION
13
Patent #:
Issue Dt:
03/18/2008
Application #:
11324510
Filing Dt:
01/03/2006
Publication #:
Pub Dt:
07/05/2007
Title:
METHOD OF FORMING DEVICE HAVING A RAISED EXTENSION REGION
14
Patent #:
Issue Dt:
08/28/2007
Application #:
11324830
Filing Dt:
01/03/2006
Publication #:
Pub Dt:
07/05/2007
Title:
FLOWMETER AND METHOD FOR THE MAKING THEREOF
15
Patent #:
Issue Dt:
04/06/2010
Application #:
11325066
Filing Dt:
01/04/2006
Publication #:
Pub Dt:
07/05/2007
Title:
SYSTEM AND METHOD FOR FAST MOTION ESTIMATION
16
Patent #:
Issue Dt:
05/19/2009
Application #:
11326524
Filing Dt:
01/04/2006
Publication #:
Pub Dt:
07/05/2007
Title:
THIN-FILM CAPACITOR WITH A FIELD MODIFICATION LAYER AND METHODS FOR FORMING THE SAME
17
Patent #:
Issue Dt:
10/07/2008
Application #:
11327686
Filing Dt:
01/06/2006
Publication #:
Pub Dt:
07/12/2007
Title:
ELECTRONIC DEVICE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE
18
Patent #:
Issue Dt:
05/25/2010
Application #:
11328594
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
ELECTRONIC DEVICE INCLUDING A FIN-TYPE TRANSISTOR STRUCTURE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE
19
Patent #:
Issue Dt:
10/07/2008
Application #:
11328645
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
METHODS OF TESTING ELECTRONIC DEVICES
20
Patent #:
Issue Dt:
05/04/2010
Application #:
11328668
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
PROCESS FOR FORMING AN ELECTRONIC DEVICE INCLUDING A FIN-TYPE STRUCTURE
21
Patent #:
Issue Dt:
07/27/2010
Application #:
11328693
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
DUAL PLASMA TREATMENT BARRIER FILM TO REDUCE LOW-K DAMAGE
22
Patent #:
Issue Dt:
07/13/2010
Application #:
11328779
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
INTEGRATED CIRCUIT USING FINFETS AND HAVING A STATIC RANDOM ACCESS MEMORY (SRAM)
23
Patent #:
Issue Dt:
09/01/2009
Application #:
11329752
Filing Dt:
01/10/2006
Publication #:
Pub Dt:
07/12/2007
Title:
AMPLIFIER WITH IMPROVED NOISE PERFORMANCE AND EXTENDED GAIN CONTROL RANGE
24
Patent #:
Issue Dt:
12/04/2007
Application #:
11331763
Filing Dt:
01/13/2006
Publication #:
Pub Dt:
07/19/2007
Title:
ALD GATE ELECTRODE
25
Patent #:
Issue Dt:
08/25/2009
Application #:
11331786
Filing Dt:
01/13/2006
Publication #:
Pub Dt:
07/19/2007
Title:
METHOD FOR REMOVING METAL FOOT DURING HIGH-K DIELECTRIC/METAL GATE ETCHING
26
Patent #:
Issue Dt:
10/12/2010
Application #:
11331958
Filing Dt:
01/13/2006
Publication #:
Pub Dt:
07/19/2007
Title:
METHOD TO CONTROL THE GATE SIDEWALL PROFILE BY GRADED MATERIAL COMPOSITION
27
Patent #:
Issue Dt:
02/26/2008
Application #:
11333844
Filing Dt:
01/18/2006
Publication #:
Pub Dt:
07/19/2007
Title:
CHARGE-FREE LAYER BY LAYER ETCHING OF DIELECTRICS
28
Patent #:
Issue Dt:
11/04/2008
Application #:
11336368
Filing Dt:
01/20/2006
Publication #:
Pub Dt:
07/26/2007
Title:
METHOD OF PACKAGING A SEMICONDUCTOR DIE AND PACKAGE THEREOF
29
Patent #:
Issue Dt:
06/09/2009
Application #:
11337036
Filing Dt:
01/19/2006
Publication #:
Pub Dt:
07/19/2007
Title:
DUAL METAL SILICIDE SCHEME USING A DUAL SPACER PROCESS
30
Patent #:
Issue Dt:
08/19/2008
Application #:
11337355
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
07/26/2007
Title:
ELECTRONIC DEVICE INCLUDING A STATIC-RANDOM-ACCESS MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE
31
Patent #:
Issue Dt:
02/26/2008
Application #:
11337775
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
07/26/2007
Title:
ELECTRONIC DEVICE AND METHOD FOR OPERATING A MEMORY CIRCUIT
32
Patent #:
Issue Dt:
12/13/2011
Application #:
11337783
Filing Dt:
01/23/2006
Publication #:
Pub Dt:
07/26/2007
Title:
MEMORY AND METHOD FOR SENSING DATA IN A MEMORY USING COMPLEMENTARY SENSING SCHEME
33
Patent #:
Issue Dt:
10/19/2010
Application #:
11338252
Filing Dt:
01/24/2006
Publication #:
Pub Dt:
07/26/2007
Title:
SYSTEM AND METHOD FOR CONTROL LOGIC CODE REORDERING BASED ON STOCHASTIC EXECUTION TIME INFORMATION
34
Patent #:
Issue Dt:
12/25/2007
Application #:
11339101
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
07/26/2007
Title:
METHOD FOR PRODUCING TWO GATES CONTROLLING THE SAME CHANNEL
35
Patent #:
Issue Dt:
08/25/2009
Application #:
11339132
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
07/26/2007
Title:
SEMICONDUCTOR INTERCONNECT HAVING ADJACENT RESERVOIR FOR BONDING AND METHOD FOR FORMATION
36
Patent #:
Issue Dt:
01/29/2008
Application #:
11339133
Filing Dt:
01/25/2006
Publication #:
Pub Dt:
07/26/2007
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH DECREASED UNDERCUTTING OF SEMICONDUCTOR MATERIAL
37
Patent #:
Issue Dt:
03/31/2009
Application #:
11339953
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
07/26/2007
Title:
SPACER T-GATE STRUCTURE FOR COSI2 EXTENDIBILITY
38
Patent #:
Issue Dt:
11/24/2009
Application #:
11340049
Filing Dt:
01/26/2006
Publication #:
Pub Dt:
07/26/2007
Title:
EPI T-GATE STRUCTURE FOR COSI2 EXTENDIBILITY
39
Patent #:
Issue Dt:
09/09/2008
Application #:
11341302
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
METHOD FOR FORMING MULTI-LAYER BUMPS ON A SUBSTRATE
40
Patent #:
Issue Dt:
10/07/2008
Application #:
11341303
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
METHOD OF PACKAGING SEMICONDUCTOR DIE WITHOUT LEAD FRAME OR SUBSTRATE
41
Patent #:
Issue Dt:
06/24/2008
Application #:
11341809
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
METHOD FOR MULTIPLE STEP PROGRAMMING A MEMORY CELL
42
Patent #:
Issue Dt:
01/08/2008
Application #:
11341813
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
MEMORY CELL USING A DIELECTRIC HAVING NON-UNIFORM THICKNESS
43
Patent #:
Issue Dt:
07/21/2009
Application #:
11341973
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
DOUBLE-GATED NON-VOLATILE MEMORY AND METHODS FOR FORMING THEREOF
44
Patent #:
Issue Dt:
10/07/2008
Application #:
11342025
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
SEMICONDUCTOR DEVICE COMPRISING A TRANSISTOR HAVING A COUNTER-DOPED CHANNEL REGION AND METHOD FOR FORMING THE SAME
45
Patent #:
Issue Dt:
03/30/2010
Application #:
11342102
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
METHOD OF FORMING A SEMICONDUCTOR ISOLATION TRENCH
46
Patent #:
Issue Dt:
06/09/2009
Application #:
11342155
Filing Dt:
01/27/2006
Publication #:
Pub Dt:
08/02/2007
Title:
SPLIT GATE MEMORY CELL IN A FINFET
47
Patent #:
Issue Dt:
08/26/2008
Application #:
11342747
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
08/02/2007
Title:
SYSTEM AND METHOD FOR REDUCING THE POWER CONSUMPTION OF CLOCK SYSTEMS
48
Patent #:
Issue Dt:
08/16/2011
Application #:
11343454
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/02/2007
Title:
DISTRIBUTED RESOURCE ACCESS PROTECTION
49
Patent #:
Issue Dt:
03/31/2009
Application #:
11343623
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
08/02/2007
Title:
MOS DEVICE WITH MULTI-LAYER GATE STACK
50
Patent #:
Issue Dt:
04/20/2010
Application #:
11343624
Filing Dt:
01/30/2006
Publication #:
Pub Dt:
08/02/2007
Title:
MOS DEVICE WITH NANO-CRYSTAL GATE STRUCTURE
51
Patent #:
NONE
Issue Dt:
Application #:
11343781
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/16/2007
Title:
Detecting reflections in a communication channel
52
Patent #:
Issue Dt:
10/21/2008
Application #:
11344511
Filing Dt:
01/31/2006
Publication #:
Pub Dt:
08/02/2007
Title:
TEMPERATURE COMPENSATION DEVICE AND METHOD THEREOF
53
Patent #:
Issue Dt:
01/04/2011
Application #:
11347103
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
08/09/2007
Title:
SELECTIVE TRANSACTION REQUEST PROCESSING AT AN INTERCONNECT DURING A LOCKOUT
54
Patent #:
Issue Dt:
05/06/2008
Application #:
11347461
Filing Dt:
02/03/2006
Publication #:
Pub Dt:
08/09/2007
Title:
GROUND SHIELDS FOR SEMICONDUCTORS
55
Patent #:
Issue Dt:
05/19/2009
Application #:
11348021
Filing Dt:
02/06/2006
Publication #:
Pub Dt:
08/09/2007
Title:
RECESSED POLY EXTENSION T-GATE
56
Patent #:
Issue Dt:
11/04/2008
Application #:
11349595
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
08/09/2007
Title:
METHOD OF FORMING A CMOS DEVICE WITH STRESSOR SOURCE/DRAIN REGIONS
57
Patent #:
Issue Dt:
06/03/2008
Application #:
11349608
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
08/09/2007
Title:
EDGE SEAL FOR IMPROVING INTEGRATED CIRCUIT NOISE ISOLATION
58
Patent #:
Issue Dt:
03/16/2010
Application #:
11349874
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
08/09/2007
Title:
ADAPTIVE VARIABLE LENGTH PULSE SYNCHRONIZER
59
Patent #:
Issue Dt:
11/04/2008
Application #:
11349875
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
08/09/2007
Title:
METHOD FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) BODY-CONTACTED DEVICE WITH A PORTION OF DRAIN REGION REMOVED
60
Patent #:
Issue Dt:
10/24/2006
Application #:
11350305
Filing Dt:
02/08/2006
Publication #:
Pub Dt:
06/15/2006
Title:
TRANSISTOR WITH REDUCED GATE-TO-SOURCE CAPACITANCE AND METHOD THEREFOR
61
Patent #:
Issue Dt:
10/23/2007
Application #:
11351518
Filing Dt:
02/10/2006
Publication #:
Pub Dt:
08/16/2007
Title:
METHOD TO SELECTIVELY FORM REGIONS HAVING DIFFERING PROPERTIES AND STRUCTURE
62
Patent #:
Issue Dt:
05/27/2008
Application #:
11354472
Filing Dt:
02/14/2006
Publication #:
Pub Dt:
08/16/2007
Title:
METHODS AND APPARATUS FOR A HIGH-FREQUENCY OUTPUT MATCH CIRCUIT
63
Patent #:
Issue Dt:
10/28/2008
Application #:
11355681
Filing Dt:
02/16/2006
Publication #:
Pub Dt:
11/08/2007
Title:
METHOD AND APPARATUS FOR TESTING A DATA PROCESSING SYSTEM
64
Patent #:
Issue Dt:
08/07/2007
Application #:
11355682
Filing Dt:
02/16/2006
Publication #:
Pub Dt:
12/21/2006
Title:
FUSE CIRCUIT AND ELECTRONIC CIRCUIT
65
Patent #:
Issue Dt:
04/22/2008
Application #:
11355822
Filing Dt:
02/16/2006
Publication #:
Pub Dt:
08/16/2007
Title:
METHOD FOR MAKING AN INTEGRATED CIRCUIT HAVING AN EMBEDDED NON-VOLATILE MEMORY
66
Patent #:
Issue Dt:
03/18/2008
Application #:
11356229
Filing Dt:
02/16/2006
Publication #:
Pub Dt:
08/30/2007
Title:
EMBEDDED SUBSTRATE INTERCONNECT FOR UNDERSIDE CONTACT TO SOURCE AND DRAIN REGIONS
67
Patent #:
Issue Dt:
11/10/2009
Application #:
11359329
Filing Dt:
02/21/2006
Publication #:
Pub Dt:
09/20/2007
Title:
ERROR CORRECTION DEVICE AND METHOD THEREOF
68
Patent #:
Issue Dt:
10/27/2009
Application #:
11360285
Filing Dt:
02/23/2006
Publication #:
Pub Dt:
08/23/2007
Title:
NOISE ISOLATION BETWEEN CIRCUIT BLOCKS IN AN INTEGRATED CIRCUIT CHIP
69
Patent #:
Issue Dt:
02/02/2010
Application #:
11360336
Filing Dt:
02/23/2006
Publication #:
Pub Dt:
08/23/2007
Title:
CAP LAYER FOR AN ALUMINUM COPPER BOND PAD
70
Patent #:
Issue Dt:
08/03/2010
Application #:
11360724
Filing Dt:
02/23/2006
Publication #:
Pub Dt:
08/23/2007
Title:
ELECTRONIC DEVICE AND METHOD
71
Patent #:
Issue Dt:
07/21/2009
Application #:
11360897
Filing Dt:
02/22/2006
Publication #:
Pub Dt:
08/23/2007
Title:
METHOD FOR IMPROVING SELF-ALIGNED SILICIDE EXTENDIBILITY WITH SPACER RECESS USING AN AGGREGATED SPACER RECESS ETCH (ASRE) INTEGRATION
72
Patent #:
Issue Dt:
12/22/2009
Application #:
11360925
Filing Dt:
02/23/2006
Publication #:
Pub Dt:
08/23/2007
Title:
METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING
73
Patent #:
Issue Dt:
05/26/2009
Application #:
11361171
Filing Dt:
02/24/2006
Publication #:
Pub Dt:
08/30/2007
Title:
SEMICONDUCTOR PROCESS INTEGRATING SOURCE/DRAIN STRESSORS AND INTERLEVEL DIELECTRIC LAYER STRESSORS
74
Patent #:
Issue Dt:
03/31/2009
Application #:
11361624
Filing Dt:
02/24/2006
Publication #:
Pub Dt:
08/30/2007
Title:
METHOD AND APPARATUS FOR A STEPPED-DRIFT MOSFET
75
Patent #:
Issue Dt:
02/23/2010
Application #:
11361625
Filing Dt:
02/24/2006
Publication #:
Pub Dt:
08/30/2007
Title:
LOW VOLTAGE OUTPUT BUFFER AND METHOD FOR BUFFERING DIGITAL OUTPUT DATA
76
Patent #:
Issue Dt:
04/12/2011
Application #:
11361948
Filing Dt:
02/24/2006
Publication #:
Pub Dt:
08/30/2007
Title:
FLEXIBLE MACROBLOCK ORDERING WITH REDUCED DATA TRAFFIC AND POWER CONSUMPTION
77
Patent #:
Issue Dt:
10/23/2007
Application #:
11362694
Filing Dt:
02/27/2006
Publication #:
Pub Dt:
08/30/2007
Title:
BIT LINE PRECHARGE IN EMBEDDED MEMORY
78
Patent #:
Issue Dt:
07/07/2009
Application #:
11363791
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
PIEZOELECTRIC MEMS SWITCHES AND METHODS OF MAKING
79
Patent #:
Issue Dt:
10/21/2008
Application #:
11363901
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
11/23/2006
Title:
STRUCTURE AND METHOD FOR RESURF LDMOSFET WITH A CURRENT DIVERTER
80
Patent #:
Issue Dt:
11/27/2007
Application #:
11364047
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
MULTI-ROW LEAD FRAME
81
Patent #:
Issue Dt:
10/21/2008
Application #:
11364104
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
INTEGRATED CIRCUIT WITH FUNCTIONAL STATE CONFIGURABLE MEMORY AND METHOD OF CONFIGURING FUNCTIONAL STATES OF THE INTEGRATED CIRCUIT MEMORY
82
Patent #:
Issue Dt:
08/03/2010
Application #:
11364128
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
METHOD FOR FORMING A DEPOSITED OXIDE LAYER
83
Patent #:
Issue Dt:
12/29/2009
Application #:
11364129
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
NON-VOLATILE MEMORY HAVING A MULTIPLE BLOCK ERASE MODE AND METHOD THEREFOR
84
Patent #:
Issue Dt:
10/09/2007
Application #:
11364792
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
METHOD OF TESTING FOR POWER AND GROUND CONTINUITY OF A SEMICONDUCTOR DEVICE
85
Patent #:
Issue Dt:
10/26/2010
Application #:
11364985
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
METHOD FOR SEPARATELY OPTIMIZING SPACER WIDTH FOR TWO TRANSISTOR GROUPS USING A RECESS SPACER ETCH (RSE) INTEGRATION
86
Patent #:
Issue Dt:
03/08/2011
Application #:
11365059
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
METHOD FOR SEPARATELY OPTIMIZING SPACER WIDTH FOR TWO OR MORE TRANSISTOR CLASSES USING A RECESS SPACER INTEGRATION
87
Patent #:
Issue Dt:
11/18/2008
Application #:
11365119
Filing Dt:
02/28/2006
Publication #:
Pub Dt:
08/30/2007
Title:
CAPACITOR ATTACHMENT METHOD
88
Patent #:
Issue Dt:
10/21/2008
Application #:
11366279
Filing Dt:
03/02/2006
Publication #:
Pub Dt:
09/06/2007
Title:
METAL GATE WITH ZIRCONIUM
89
Patent #:
Issue Dt:
01/27/2009
Application #:
11366286
Filing Dt:
03/02/2006
Publication #:
Pub Dt:
09/20/2007
Title:
APPARATUS AND METHOD FOR ADJUSTING AN OPERATING PARAMETER OF AN INTEGRATED CIRCUIT
90
Patent #:
Issue Dt:
08/19/2008
Application #:
11366928
Filing Dt:
03/01/2006
Publication #:
Pub Dt:
09/06/2007
Title:
METHODS AND APPARATUS FOR THERMAL ISOLATION IN VERTICALLY-INTEGRATED SEMICONDUCTOR DEVICES
91
Patent #:
Issue Dt:
04/07/2009
Application #:
11368720
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
07/26/2007
Title:
COMPOSITE INTEGRATED DEVICE AND METHODS FOR FORMING THEREOF
92
Patent #:
Issue Dt:
07/09/2013
Application #:
11368729
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
11/15/2007
Title:
ENHANCED TONE DETECTOR INCLUDING ADAPTIVE MULTI-BANDPASS FILTER FOR TONE DETECTION AND ENHANCEMENT
93
Patent #:
Issue Dt:
03/02/2010
Application #:
11369513
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
09/06/2007
Title:
TREATMENT FOR REDUCTION OF LINE EDGE ROUGHNESS
94
Patent #:
Issue Dt:
05/10/2011
Application #:
11369648
Filing Dt:
03/07/2006
Publication #:
Pub Dt:
09/13/2007
Title:
ELECTRONIC DEVICE TESTING SYSTEM
95
Patent #:
Issue Dt:
12/29/2009
Application #:
11369737
Filing Dt:
03/07/2006
Publication #:
Pub Dt:
09/13/2007
Title:
ALLOCATING PROCESSING RESOURCES FOR MULTIPLE INSTANCES OF A SOFTWARE COMPONENT
96
Patent #:
Issue Dt:
05/19/2009
Application #:
11370283
Filing Dt:
03/08/2006
Publication #:
Pub Dt:
09/13/2007
Title:
CHARGE STORAGE STRUCTURE FORMATION IN TRANSISTOR WITH VERTICAL CHANNEL REGION
97
Patent #:
Issue Dt:
09/02/2008
Application #:
11370381
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
01/25/2007
Title:
CLOCK GENERATION CIRCUIT
98
Patent #:
Issue Dt:
02/24/2009
Application #:
11370387
Filing Dt:
03/06/2006
Publication #:
Pub Dt:
09/06/2007
Title:
METHOD FOR FORMING REINFORCED INTERCONNECTS ON A SUBSTRATE
99
Patent #:
Issue Dt:
05/11/2010
Application #:
11371142
Filing Dt:
03/08/2006
Publication #:
Pub Dt:
09/13/2007
Title:
DYNAMIC TIMING ADJUSTMENT IN A CIRCUIT DEVICE
100
Patent #:
Issue Dt:
10/30/2007
Application #:
11372495
Filing Dt:
03/10/2006
Publication #:
Pub Dt:
09/13/2007
Title:
SEMICONDUCTOR STORAGE DEVICE
Assignor
1
Exec Dt:
12/07/2015
Assignee
1
1300 THAMES STREET, 4TH FLOOR
BALTIMORE, MARYLAND 21231
Correspondence name and address
DARLENA BARI STARK
1025 VERMONT AVE NW, SUITE 1130
NATIONAL CORPORATE RESEARCH, LTD.
WASHINGTON, DC 20005

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