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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:037486/0517   Pages: 404
Recorded: 01/12/2016
Attorney Dkt #:F160353
Conveyance: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS
Total properties: 6067
Page 38 of 61
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
1
Patent #:
7589658
Issue Dt:
09/15/2009
Application #:
12026205
Filing Dt:
02/05/2008
Publication #:
US20090195428
Pub Dt:
08/06/2009
Title:
ANALOG-TO-DIGITAL CONVERTER WITH VARIABLE GAIN AND METHOD THEREOF
2
Patent #:
7777330
Issue Dt:
08/17/2010
Application #:
12026325
Filing Dt:
02/05/2008
Publication #:
US20090196086
Pub Dt:
08/06/2009
Title:
HIGH BANDWIDTH CACHE-TO-PROCESSING UNIT COMMUNICATION IN A MULTIPLE PROCESSOR/CACHE SYSTEM
3
Patent #:
7612613
Issue Dt:
11/03/2009
Application #:
12026394
Filing Dt:
02/05/2008
Publication #:
US20090195318
Pub Dt:
08/06/2009
Title:
SELF REGULATING BIASING CIRCUIT
4
Patent #:
7978793
Issue Dt:
07/12/2011
Application #:
12026556
Filing Dt:
02/06/2008
Publication #:
US20090196380
Pub Dt:
08/06/2009
Title:
METHOD FOR GENERATING SOFT DECISION SIGNAL FROM HARD DECISION SIGNAL IN A RECEIVER SYSTEM
5
Patent #:
7962805
Issue Dt:
06/14/2011
Application #:
12026595
Filing Dt:
02/06/2008
Title:
SYSTEM AND METHOD FOR PREVENTING A RACE CONDITION
6
Patent #:
7978757
Issue Dt:
07/12/2011
Application #:
12028018
Filing Dt:
02/08/2008
Title:
CONFIGURABLE RECEIVER AND A METHOD FOR CONFIGURING A RECEIVER
7
Patent #:
8073078
Issue Dt:
12/06/2011
Application #:
12028623
Filing Dt:
02/08/2008
Publication #:
US20090202022
Pub Dt:
08/13/2009
Title:
SPLIT CHANNEL RECEIVER WITH VERY LOW SECOND ORDER INTERMODULATION
8
Patent #:
7843033
Issue Dt:
11/30/2010
Application #:
12028650
Filing Dt:
02/08/2008
Publication #:
US20090200647
Pub Dt:
08/13/2009
Title:
SHIELDED INTEGRATED CIRCUIT PAD STRUCTURE
9
Patent #:
8010074
Issue Dt:
08/30/2011
Application #:
12028720
Filing Dt:
02/08/2008
Publication #:
US20090203347
Pub Dt:
08/13/2009
Title:
MIXER CIRCUITS FOR SECOND ORDER INTERCEPT POINT CALIBRATION
10
Patent #:
7759753
Issue Dt:
07/20/2010
Application #:
12030213
Filing Dt:
02/13/2008
Publication #:
US20090200562
Pub Dt:
08/13/2009
Title:
INTEGRATED CIRCUIT DIE, INTEGRATED CIRCUIT PACKAGE, AND PACKAGING METHOD
11
Patent #:
8977790
Issue Dt:
03/10/2015
Application #:
12032286
Filing Dt:
02/15/2008
Publication #:
US20090210590
Pub Dt:
08/20/2009
Title:
PERIPHERAL MODULE REGISTER ACCESS METHODS AND APPARATUS
12
Patent #:
7572680
Issue Dt:
08/11/2009
Application #:
12033716
Filing Dt:
02/19/2008
Publication #:
US20080136016
Pub Dt:
06/12/2008
Title:
PACKAGED INTEGRATED CIRCUIT WITH ENHANCED THERMAL DISSIPATION
13
Patent #:
7800974
Issue Dt:
09/21/2010
Application #:
12034888
Filing Dt:
02/21/2008
Publication #:
US20090213668
Pub Dt:
08/27/2009
Title:
ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT
14
Patent #:
8312253
Issue Dt:
11/13/2012
Application #:
12035961
Filing Dt:
02/22/2008
Publication #:
US20090217010
Pub Dt:
08/27/2009
Title:
DATA PROCESSOR DEVICE HAVING TRACE CAPABILITIES AND METHOD
15
Patent #:
10073797
Issue Dt:
09/11/2018
Application #:
12035967
Filing Dt:
02/22/2008
Publication #:
US20090217298
Pub Dt:
08/27/2009
Title:
DATA PROCESSOR DEVICE SUPPORTING SELECTABLE EXCEPTIONS AND METHOD THEREOF
16
Patent #:
8417924
Issue Dt:
04/09/2013
Application #:
12035969
Filing Dt:
02/22/2008
Publication #:
US20090217011
Pub Dt:
08/27/2009
Title:
DATA PROCESSING DEVICE AND METHOD OF HALTING EXCEPTION PROCESSING
17
Patent #:
7612588
Issue Dt:
11/03/2009
Application #:
12037094
Filing Dt:
02/26/2008
Publication #:
US20080218223
Pub Dt:
09/11/2008
Title:
POWER ON DETECTION CIRCUIT
18
Patent #:
7608893
Issue Dt:
10/27/2009
Application #:
12037147
Filing Dt:
02/26/2008
Publication #:
US20080142853
Pub Dt:
06/19/2008
Title:
MULTI-CHANNEL TRANSISTOR STRUCTURE AND METHOD OF MAKING THEREOF
19
Patent #:
7868393
Issue Dt:
01/11/2011
Application #:
12037280
Filing Dt:
02/26/2008
Publication #:
US20090212374
Pub Dt:
08/27/2009
Title:
SPACE EFFICIENT INTEGRATED CIRCUIT WITH PASSIVE DEVICES
20
Patent #:
7920987
Issue Dt:
04/05/2011
Application #:
12037333
Filing Dt:
02/26/2008
Publication #:
US20090216480
Pub Dt:
08/27/2009
Title:
DEVICE UNDER TEST DE-EMBEDDING
21
Patent #:
7911750
Issue Dt:
03/22/2011
Application #:
12038146
Filing Dt:
02/27/2008
Publication #:
US20090213506
Pub Dt:
08/27/2009
Title:
RESISTOR TRIGGERED ELECTROSTATIC DISCHARGE PROTECTION
22
Patent #:
7741183
Issue Dt:
06/22/2010
Application #:
12039361
Filing Dt:
02/28/2008
Publication #:
US20090221120
Pub Dt:
09/03/2009
Title:
METHOD OF FORMING A GATE DIELECTRIC
23
Patent #:
7573332
Issue Dt:
08/11/2009
Application #:
12039377
Filing Dt:
02/28/2008
Publication #:
US20090219093
Pub Dt:
09/03/2009
Title:
AMPLIFIER WITH ACTIVE INDUCTOR
24
Patent #:
8072062
Issue Dt:
12/06/2011
Application #:
12039434
Filing Dt:
02/28/2008
Publication #:
US20080142960
Pub Dt:
06/19/2008
Title:
CIRCUIT DEVICE WITH AT LEAST PARTIAL PACKAGING AND METHOD FOR FORMING
25
Patent #:
8168468
Issue Dt:
05/01/2012
Application #:
12039909
Filing Dt:
02/29/2008
Publication #:
US20090218567
Pub Dt:
09/03/2009
Title:
Method of making a semiconductor device including a bridgeable material
26
Patent #:
8609471
Issue Dt:
12/17/2013
Application #:
12039913
Filing Dt:
02/29/2008
Publication #:
US20090221114
Pub Dt:
09/03/2009
Title:
PACKAGING AN INTEGRATED CIRCUIT DIE USING COMPRESSION MOLDING
27
Patent #:
7895422
Issue Dt:
02/22/2011
Application #:
12040204
Filing Dt:
02/29/2008
Publication #:
US20090222648
Pub Dt:
09/03/2009
Title:
SELECTIVE POSTPONEMENT OF BRANCH TARGET BUFFER (BTB) ALLOCATION
28
Patent #:
7937573
Issue Dt:
05/03/2011
Application #:
12040210
Filing Dt:
02/29/2008
Publication #:
US20090222645
Pub Dt:
09/03/2009
Title:
METRIC FOR SELECTIVE BRANCH TARGET BUFFER (BTB) ALLOCATION
29
Patent #:
7602233
Issue Dt:
10/13/2009
Application #:
12040277
Filing Dt:
02/29/2008
Publication #:
US20090219077
Pub Dt:
09/03/2009
Title:
VOLTAGE MULTIPLIER WITH IMPROVED EFFICIENCY
30
Patent #:
7687354
Issue Dt:
03/30/2010
Application #:
12040394
Filing Dt:
02/29/2008
Publication #:
US20090221119
Pub Dt:
09/03/2009
Title:
FABRICATION OF A SEMICONDUCTOR DEVICE WITH STRESSOR
31
Patent #:
7804701
Issue Dt:
09/28/2010
Application #:
12040407
Filing Dt:
02/29/2008
Publication #:
US20090219747
Pub Dt:
09/03/2009
Title:
METHOD OF PROGRAMMING A MEMORY HAVING ELECTRICALLY PROGRAMMABLE FUSES
32
Patent #:
7893696
Issue Dt:
02/22/2011
Application #:
12040429
Filing Dt:
02/29/2008
Publication #:
US20090219038
Pub Dt:
09/03/2009
Title:
PULSE CIRCUIT USING A TRANSMISSION LINE
33
Patent #:
7829366
Issue Dt:
11/09/2010
Application #:
12040737
Filing Dt:
02/29/2008
Publication #:
US20090218642
Pub Dt:
09/03/2009
Title:
MICROELECTROMECHANICAL SYSTEMS COMPONENT AND METHOD OF MAKING SAME
34
Patent #:
7786809
Issue Dt:
08/31/2010
Application #:
12041687
Filing Dt:
03/04/2008
Title:
METHOD OF LOW POWER PLL FOR LOW JITTER DEMANDING APPLICATIONS
35
Patent #:
7667545
Issue Dt:
02/23/2010
Application #:
12042216
Filing Dt:
03/04/2008
Publication #:
US20090224838
Pub Dt:
09/10/2009
Title:
AUTOMATIC CALIBRATION LOCK LOOP CIRCUIT AND METHOD HAVING IMPROVED LOCK TIME
36
Patent #:
7595699
Issue Dt:
09/29/2009
Application #:
12042228
Filing Dt:
03/04/2008
Publication #:
US20090224839
Pub Dt:
09/10/2009
Title:
LOCK LOOP CIRCUIT AND METHOD HAVING IMPROVED LOCK TIME
37
Patent #:
7548093
Issue Dt:
06/16/2009
Application #:
12042351
Filing Dt:
03/05/2008
Title:
SCHEME OF LEVEL SHIFTER CELL
38
Patent #:
7991921
Issue Dt:
08/02/2011
Application #:
12046324
Filing Dt:
03/11/2008
Publication #:
US20090234989
Pub Dt:
09/17/2009
Title:
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY IN AN I/O CONTROLLER
39
Patent #:
7742340
Issue Dt:
06/22/2010
Application #:
12048683
Filing Dt:
03/14/2008
Publication #:
US20090231925
Pub Dt:
09/17/2009
Title:
READ REFERENCE TECHNIQUE WITH CURRENT DEGRADATION PROTECTION
40
Patent #:
8261047
Issue Dt:
09/04/2012
Application #:
12049984
Filing Dt:
03/17/2008
Publication #:
US20090235059
Pub Dt:
09/17/2009
Title:
QUALIFICATION OF CONDITIONAL DEBUG INSTRUCTIONS BASED ON ADDRESS
41
Patent #:
7692464
Issue Dt:
04/06/2010
Application #:
12050172
Filing Dt:
03/18/2008
Publication #:
US20080246523
Pub Dt:
10/09/2008
Title:
PULSE WIDTH MODULATION WAVE OUTPUT CIRCUIT
42
Patent #:
7701285
Issue Dt:
04/20/2010
Application #:
12051450
Filing Dt:
03/19/2008
Publication #:
US20090237156
Pub Dt:
09/24/2009
Title:
POWER AMPLIFIERS HAVING IMPROVED STARTUP LINEARIZATION AND RELATED OPERATING METHODS
43
Patent #:
7898301
Issue Dt:
03/01/2011
Application #:
12053250
Filing Dt:
03/21/2008
Publication #:
US20090237118
Pub Dt:
09/24/2009
Title:
ZERO INPUT CURRENT-DRAIN COMPARATOR WITH HIGH ACCURACY TRIP POINT ABOVE SUPPLY VOLTAGE
44
Patent #:
8117642
Issue Dt:
02/14/2012
Application #:
12053502
Filing Dt:
03/21/2008
Publication #:
US20090240923
Pub Dt:
09/24/2009
Title:
COMPUTING DEVICE WITH ENTRY AUTHENTICATION INTO TRUSTED EXECUTION ENVIRONMENT AND METHOD THEREFOR
45
Patent #:
7999581
Issue Dt:
08/16/2011
Application #:
12053601
Filing Dt:
03/23/2008
Title:
SYSTEM AND A METHOD FOR PROVIDING AN OUTPUT CLOCK SIGNAL
46
Patent #:
8050048
Issue Dt:
11/01/2011
Application #:
12053622
Filing Dt:
03/24/2008
Publication #:
US20080266828
Pub Dt:
10/30/2008
Title:
LEAD FRAME WITH SOLDER FLOW CONTROL
47
Patent #:
8667226
Issue Dt:
03/04/2014
Application #:
12053761
Filing Dt:
03/24/2008
Publication #:
US20090240892
Pub Dt:
09/24/2009
Title:
SELECTIVE INTERCONNECT TRANSACTION CONTROL FOR CACHE COHERENCY MAINTENANCE
48
Patent #:
7861200
Issue Dt:
12/28/2010
Application #:
12054015
Filing Dt:
03/24/2008
Publication #:
US20090241080
Pub Dt:
09/24/2009
Title:
SETUP AND HOLD TIME CHARACTERIZATION DEVICE AND METHOD
49
Patent #:
7778154
Issue Dt:
08/17/2010
Application #:
12054517
Filing Dt:
03/25/2008
Publication #:
US20090245288
Pub Dt:
10/01/2009
Title:
TECHNIQUES FOR REDUCING INTERFERENCE IN A COMMUNICATION SYSTEM
50
Patent #:
7863876
Issue Dt:
01/04/2011
Application #:
12055538
Filing Dt:
03/26/2008
Publication #:
US20090243571
Pub Dt:
10/01/2009
Title:
BUILT-IN SELF-CALIBRATION (BISC) TECHNIQUE FOR REGULATION CIRCUITS USED IN NON-VOLATILE MEMORY
51
Patent #:
7825610
Issue Dt:
11/02/2010
Application #:
12056237
Filing Dt:
03/26/2008
Publication #:
US20090230891
Pub Dt:
09/17/2009
Title:
LED DRIVER WITH DYNAMIC POWER MANAGEMENT
52
Patent #:
8077803
Issue Dt:
12/13/2011
Application #:
12056652
Filing Dt:
03/27/2008
Publication #:
US20090245420
Pub Dt:
10/01/2009
Title:
QUARTER DUTY CYCLE PULSE GENERATOR FOR INTERLEAVED SWITCHING MIXER
53
Patent #:
7793025
Issue Dt:
09/07/2010
Application #:
12057989
Filing Dt:
03/28/2008
Publication #:
US20090248935
Pub Dt:
10/01/2009
Title:
HARDWARE MANAGED CONTEXT SENSITIVE INTERRUPT PRIORITY LEVEL CONTROL
54
Patent #:
8122437
Issue Dt:
02/21/2012
Application #:
12058874
Filing Dt:
03/31/2008
Publication #:
US20090249302
Pub Dt:
10/01/2009
Title:
METHOD AND APPARATUS TO TRACE AND CORRELATE DATA TRACE AND INSTRUCTION TRACE FOR OUT-OF-ORDER PROCESSORS
55
Patent #:
7867858
Issue Dt:
01/11/2011
Application #:
12059006
Filing Dt:
03/31/2008
Publication #:
US20090242994
Pub Dt:
10/01/2009
Title:
HYBRID TRANSISTOR BASED POWER GATING SWITCH CIRCUIT AND METHOD
56
Patent #:
7969164
Issue Dt:
06/28/2011
Application #:
12059012
Filing Dt:
03/31/2008
Publication #:
US20090243629
Pub Dt:
10/01/2009
Title:
METHOD AND APPARATUS FOR MINI MODULE EMI SHIELDING EVALUATION
57
Patent #:
7803714
Issue Dt:
09/28/2010
Application #:
12059123
Filing Dt:
03/31/2008
Publication #:
US20090243074
Pub Dt:
10/01/2009
Title:
SEMICONDUCTOR THROUGH SILICON VIAS OF VARIABLE SIZE AND METHOD OF FORMATION
58
Patent #:
7858482
Issue Dt:
12/28/2010
Application #:
12059286
Filing Dt:
03/31/2008
Publication #:
US20090242944
Pub Dt:
10/01/2009
Title:
METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION
59
Patent #:
7688113
Issue Dt:
03/30/2010
Application #:
12059906
Filing Dt:
03/31/2008
Publication #:
US20090243655
Pub Dt:
10/01/2009
Title:
CURRENT DRIVER SUITABLE FOR USE IN A SHARED BUS ENVIRONMENT
60
Patent #:
7910991
Issue Dt:
03/22/2011
Application #:
12060105
Filing Dt:
03/31/2008
Publication #:
US20090244928
Pub Dt:
10/01/2009
Title:
DUAL GATE LATERAL DIFFUSED MOS TRANSISTOR
61
Patent #:
8415255
Issue Dt:
04/09/2013
Application #:
12063010
Filing Dt:
02/05/2008
Publication #:
US20080311752
Pub Dt:
12/18/2008
Title:
Pore Sealing and Cleaning Porous Low Dielectric Constant Structures
62
Patent #:
7605652
Issue Dt:
10/20/2009
Application #:
12063012
Filing Dt:
02/05/2008
Publication #:
US20080211575
Pub Dt:
09/04/2008
Title:
LOOP GAIN EQUALIZER FOR RF POWER AMPLIFIER
63
Patent #:
NONE
Issue Dt:
Application #:
12063422
Filing Dt:
02/08/2008
Publication #:
US20090154426
Pub Dt:
06/18/2009
Title:
HANDOVER BASED ON A QUALITY OF SERVICE METRIC OBTAINED FROM A MAC LAYER OF A RECEIVED SIGNAL
64
Patent #:
8188539
Issue Dt:
05/29/2012
Application #:
12063424
Filing Dt:
03/09/2010
Publication #:
US20100155828
Pub Dt:
06/24/2010
Title:
FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
65
Patent #:
7691756
Issue Dt:
04/06/2010
Application #:
12065179
Filing Dt:
02/28/2008
Publication #:
US20080197487
Pub Dt:
08/21/2008
Title:
SEMICONDUCTOR DEVICE INCLUDING A COUPLED DIELECTRIC LAYER AND METAL LAYER, METHOD OF FABRICATION THEREOF, AND MATERIAL FOR COUPLING A DIELECTRIC LAYER AND A METAL LAYER IN A SEMICONDUCTOR DEVICE
66
Patent #:
8263430
Issue Dt:
09/11/2012
Application #:
12065190
Filing Dt:
02/28/2008
Publication #:
US20080242110
Pub Dt:
10/02/2008
Title:
CAPPING LAYER FORMATION ONTO A DUAL DAMESCENE INTERCONNECT
67
Patent #:
7622387
Issue Dt:
11/24/2009
Application #:
12065256
Filing Dt:
02/28/2008
Publication #:
US20080197498
Pub Dt:
08/21/2008
Title:
GATE ELECTRODE SILICIDATION PROCESS
68
Patent #:
8065646
Issue Dt:
11/22/2011
Application #:
12066225
Filing Dt:
03/07/2008
Publication #:
US20080250372
Pub Dt:
10/09/2008
Title:
METHOD AND A COMPUTER READABLE MEDIUM FOR PERFORMING STATIC TIMING ANALYSIS OF A DESIGN OF AN INTEGRATED CIRCUIT
69
Patent #:
8139683
Issue Dt:
03/20/2012
Application #:
12066227
Filing Dt:
11/20/2008
Publication #:
US20090129489
Pub Dt:
05/21/2009
Title:
RECEIVER AND A METHOD FOR CHANNEL ESTIMATION
70
Patent #:
8307147
Issue Dt:
11/06/2012
Application #:
12066229
Filing Dt:
07/07/2008
Publication #:
US20080307145
Pub Dt:
12/11/2008
Title:
INTERCONNECT AND A METHOD FOR DESIGNING AN INTERCONNECT
71
Patent #:
8134941
Issue Dt:
03/13/2012
Application #:
12066436
Filing Dt:
08/11/2008
Publication #:
US20080301477
Pub Dt:
12/04/2008
Title:
POWER SAVING IN SIGNAL PROCESSING IN RECEIVERS
72
Patent #:
7867788
Issue Dt:
01/11/2011
Application #:
12067585
Filing Dt:
03/20/2008
Publication #:
US20090243007
Pub Dt:
10/01/2009
Title:
SPIN-DEPENDENT TUNNELLING CELL AND METHOD OF FORMATION THEREOF
73
Patent #:
NONE
Issue Dt:
Application #:
12067587
Filing Dt:
03/20/2008
Publication #:
US20080256551
Pub Dt:
10/16/2008
Title:
System and Method For Storing State Information
74
Patent #:
8461913
Issue Dt:
06/11/2013
Application #:
12067594
Filing Dt:
07/18/2008
Publication #:
US20090027018
Pub Dt:
01/29/2009
Title:
INTEGRATED CIRCUIT AND A METHOD FOR SELECTING A VOLTAGE IN AN INTEGRATED CIRCUIT
75
Patent #:
7616676
Issue Dt:
11/10/2009
Application #:
12068676
Filing Dt:
02/11/2008
Publication #:
US20080136644
Pub Dt:
06/12/2008
Title:
METHOD AND SYSTEM FOR PERFORMING DISTANCE MEASURING AND DIRECTION FINDING USING ULTRAWIDE BANDWITDH TRANSMISSIONS
76
Patent #:
7901852
Issue Dt:
03/08/2011
Application #:
12074148
Filing Dt:
02/29/2008
Publication #:
US20090220895
Pub Dt:
09/03/2009
Title:
METROLOGY OF BILAYER PHOTORESIST PROCESSES
77
Patent #:
8515372
Issue Dt:
08/20/2013
Application #:
12079106
Filing Dt:
03/24/2008
Publication #:
US20090239489
Pub Dt:
09/24/2009
Title:
RECEIVER CONFIGURABLE IN A PLURALITY OF MODES
78
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Title:
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Title:
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Assignor
1
CITIBANK, N.A.
Exec Dt:
12/07/2015
Assignee
1
MORGAN STANLEY SENIOR FUNDING, INC.
1300 THAMES STREET, 4TH FLOOR
BALTIMORE, MARYLAND 21231
Correspondence name and address
DARLENA BARI STARK
1025 VERMONT AVE NW, SUITE 1130
NATIONAL CORPORATE RESEARCH, LTD.
WASHINGTON, DC 20005

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