|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13681437
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
01/30/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGE WITH CAP ELEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
13681956
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
LOW-POWER VOLTAGE TAMPER DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2015
|
Application #:
|
13682350
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/2015
|
Application #:
|
13682367
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13682558
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUIT ELECTRICAL PROTECTION DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/06/2016
|
Application #:
|
13682604
|
Filing Dt:
|
11/20/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
TRIGGER CIRCUIT AND METHOD FOR IMPROVED TRANSIENT IMMUNITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2014
|
Application #:
|
13682749
|
Filing Dt:
|
11/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/06/2014
| | | | |
|
Title:
|
LOW POWER SCAN FLIP-FLOP CELL
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13682751
|
Filing Dt:
|
11/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/27/2014
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR DEBLOCK FILTERING CODED MACROBLOCKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2015
|
Application #:
|
13682755
|
Filing Dt:
|
11/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
SYSTEM FOR DATA TRANSFER BETWEEN ASYNCHRONOUS CLOCK DOMAINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2017
|
Application #:
|
13684840
|
Filing Dt:
|
11/26/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
|
Title:
|
TEST STRUCTURE ACTIVATED BY PROBE NEEDLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/2016
|
Application #:
|
13686102
|
Filing Dt:
|
11/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
ELECTRONIC DEVICES WITH CAVITY-TYPE, PERMEABLE MATERIAL FILLED PACKAGES, AND METHODS OF THEIR MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
13686889
|
Filing Dt:
|
11/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
VOLTAGE RAMP-UP PROTECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13686901
|
Filing Dt:
|
11/27/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
METHOD AND INTEGRATED CIRCUIT THAT PROVIDES TRACKING BETWEEN MULTIPLE REGULATED VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/10/2016
|
Application #:
|
13687299
|
Filing Dt:
|
11/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
INERTIAL SENSOR AND METHOD OF LEVITATION EFFECT COMPENSATION
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13687424
|
Filing Dt:
|
11/28/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
SPRING FOR MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/26/2016
|
Application #:
|
13688820
|
Filing Dt:
|
11/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
ELECTRONIC DEVICES WITH EMBEDDED DIE INTERCONNECT STRUCTURES, AND METHODS OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13689034
|
Filing Dt:
|
11/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2015
|
Application #:
|
13689037
|
Filing Dt:
|
11/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/04/2013
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR DELIVERING POWER IN RESPONSE TO A CONNECTION EVENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
13689043
|
Filing Dt:
|
11/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR CONTROLLING POWER IN SEMICONDUCTOR CIRCUITS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13689274
|
Filing Dt:
|
11/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/29/2014
| | | | |
|
Title:
|
METHODS FOR THE FABRICATION OF SEMICONDUCTOR DEVICES INCLUDING SUB-ISOLATION BURIED LAYERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2016
|
Application #:
|
13689331
|
Filing Dt:
|
11/29/2012
|
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
|
Title:
|
MEMORY COLUMN DROWSY CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2013
|
Application #:
|
13689424
|
Filing Dt:
|
11/29/2012
|
|
Title:
|
PROVIDING AN AUTOMATIC OPTICAL INSPECTION FEATURE FOR SOLDER JOINTS ON SEMICONDUCTOR PACKAGES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13689845
|
Filing Dt:
|
11/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGES PROVIDING ENHANCED EXPOSED TOE FILLETS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13690046
|
Filing Dt:
|
11/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/05/2014
| | | | |
|
Title:
|
OVER VOLTAGE PROTECTION FOR A THIN OXIDE LOAD CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
13690336
|
Filing Dt:
|
11/30/2012
|
|
Title:
|
AC COUPLED LEVEL SHIFTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2016
|
Application #:
|
13690888
|
Filing Dt:
|
11/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
02/20/2014
| | | | |
|
Title:
|
RANDOM ACCESS OF A CACHE PORTION USING AN ACCESS MODULE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
13695670
|
Filing Dt:
|
11/01/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND ESD PROTECTION THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13698122
|
Filing Dt:
|
11/15/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/07/2013
| | | | |
|
Title:
|
POWER SWITCHING APPARATUS AND METHOD FOR IMPROVING CURRENT SENSE ACCURACY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2015
|
Application #:
|
13701303
|
Filing Dt:
|
11/30/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2013
| | | | |
|
Title:
|
INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD FOR DETECTING TIMING VIOLATIONS WITHIN A CLOCK SIGNAL
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13709049
|
Filing Dt:
|
12/09/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2013
| | | | |
|
Title:
|
EMBEDDED LOGIC ANALYZER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2014
|
Application #:
|
13709103
|
Filing Dt:
|
12/10/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
|
Title:
|
REDUCING THE POWER CONSUMPTION OF MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2014
|
Application #:
|
13712051
|
Filing Dt:
|
12/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
|
Title:
|
INTEGRATED CIRCUITS INCLUDING INTEGRATED PASSIVE DEVICES AND METHODS OF MANUFACTURE THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/07/2015
|
Application #:
|
13712070
|
Filing Dt:
|
12/12/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/12/2014
| | | | |
|
Title:
|
SYSTEMS WITH ADJUSTABLE SAMPLING PARAMETERS AND METHODS OF THEIR OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13714415
|
Filing Dt:
|
12/14/2012
|
|
Publication #:
|
|
Pub Dt:
|
03/13/2014
| | | | |
|
Title:
|
BAND GAP REFERENCE VOLTAGE GENERATOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13716193
|
Filing Dt:
|
12/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/24/2014
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR CLEANING BOND WIRE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2014
|
Application #:
|
13716194
|
Filing Dt:
|
12/16/2012
|
|
Publication #:
|
|
Pub Dt:
|
05/22/2014
| | | | |
|
Title:
|
RAIL TO RAIL DIFFERENTIAL BUFFER INPUT STAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2013
|
Application #:
|
13717646
|
Filing Dt:
|
12/17/2012
|
|
Title:
|
MULTI-VOLTAGE DOMAIN CIRCUIT DESIGN VERIFICATION METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2015
|
Application #:
|
13718081
|
Filing Dt:
|
12/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE SIGNAL ROUTING USING CONDUCTIVE VIAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13718598
|
Filing Dt:
|
12/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
|
Title:
|
REDUCING MEMS STICTION BY INTRODUCTION OF A CARBON BARRIER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
13718614
|
Filing Dt:
|
12/18/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/19/2014
| | | | |
|
Title:
|
REDUCING MEMS STICTION BY DEPOSITION OF NANOCLUSTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2014
|
Application #:
|
13723207
|
Filing Dt:
|
12/21/2012
|
|
Publication #:
|
|
Pub Dt:
|
04/03/2014
| | | | |
|
Title:
|
SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13731242
|
Filing Dt:
|
12/31/2012
|
|
Publication #:
|
|
Pub Dt:
|
06/06/2013
| | | | |
|
Title:
|
METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13732533
|
Filing Dt:
|
01/02/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
|
Title:
|
SUPPRESSION OF REDUNDANT CACHE STATUS UPDATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
13735049
|
Filing Dt:
|
01/07/2013
|
|
Title:
|
SYSTEM FOR REDUCING POWER CONSUMPTION OF ELECTRONIC CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
|
Application #:
|
13735050
|
Filing Dt:
|
01/07/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
SYSTEM FOR MANAGING UPLINK QUALITY OF SERVICE (QOS) IN CELLULAR NETWORK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13735052
|
Filing Dt:
|
01/07/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
BOSE-CHAUDHURI-HOCQUENGHEM (BCH) DECODER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13735053
|
Filing Dt:
|
01/07/2013
|
|
Title:
|
CONFIGURABLE CIRCUIT AND MESH STRUCTURE FOR INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
13735054
|
Filing Dt:
|
01/07/2013
|
|
Title:
|
INTEGRATED CIRCUIT DESIGN VERIFICATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13736310
|
Filing Dt:
|
01/08/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
Memory Having Improved Reliability for Certain Data Types
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13736322
|
Filing Dt:
|
01/08/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/10/2014
| | | | |
|
Title:
|
Memory Using Voltage to Improve Reliability for Certain Data Types
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13736440
|
Filing Dt:
|
01/08/2013
|
|
Title:
|
SCHMITT TRIGGER CIRCUIT WITH NEAR RAIL-TO-RAIL HYSTERESIS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2015
|
Application #:
|
13739732
|
Filing Dt:
|
01/11/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR TESTING A RANDOM NUMBER GENERATOR TESTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2015
|
Application #:
|
13739749
|
Filing Dt:
|
01/11/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
BUS SIGNAL ENCODED WITH DATA AND CLOCK SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
13740404
|
Filing Dt:
|
01/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
Methods And Systems For Pushing Dirty Linefill Buffer Contents To External Bus Upon Linefill Request Failures
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2014
|
Application #:
|
13740823
|
Filing Dt:
|
01/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
TRANSMISSION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2014
|
Application #:
|
13740862
|
Filing Dt:
|
01/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
MULTIPORT MEMORY WITH MATCHING ADDRESS AND DATA LINE CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
13740868
|
Filing Dt:
|
01/14/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/2015
|
Application #:
|
13741743
|
Filing Dt:
|
01/15/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2014
|
Application #:
|
13742532
|
Filing Dt:
|
01/16/2013
|
|
Title:
|
DIGITAL TO ANALOG CONVERTER WITH CURRENT STEERING SOURCE FOR REDUCED GLITCH ENERGY ERROR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/22/2015
|
Application #:
|
13742540
|
Filing Dt:
|
01/16/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
REDUCING OUTPUT VOLTAGE RIPPLE OF POWER SUPPLIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13743323
|
Filing Dt:
|
01/16/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
CAPACITOR CHARGING CIRCUIT WITH LOW SUB-THRESHOLD TRANSISTOR LEAKAGE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13743324
|
Filing Dt:
|
01/16/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2015
|
Application #:
|
13745425
|
Filing Dt:
|
01/18/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
DMA-ASSISTED IRREGULAR SAMPLING SEQUENCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
13746840
|
Filing Dt:
|
01/22/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR REDUCED COUPLING BETWEEN DIGITAL SIGNAL LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2015
|
Application #:
|
13746841
|
Filing Dt:
|
01/22/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR ADAPTIVE SOFT PROGRAMMING FOR NON-VOLATILE MEMORY USING TEMPERATURE SENSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2014
|
Application #:
|
13746874
|
Filing Dt:
|
01/22/2013
|
|
Title:
|
DEVICES AND METHODS FOR CONFIGURING CONDUCTIVE ELEMENTS FOR A SEMICONDUCTOR PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
13746891
|
Filing Dt:
|
01/22/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
Vector Comparator System for Finding a Peak Number
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2014
|
Application #:
|
13747088
|
Filing Dt:
|
01/22/2013
|
|
Title:
|
FLASH MEMORY WITH BIAS VOLTAGE FOR WORD LINE/ROW DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2014
|
Application #:
|
13747094
|
Filing Dt:
|
01/22/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
13747504
|
Filing Dt:
|
01/23/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
DYNAMIC DETECTION METHOD FOR LATENT SLOW-TO-ERASE BIT FOR HIGH PERFORMANCE AND HIGH RELIABILITY FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2015
|
Application #:
|
13747608
|
Filing Dt:
|
01/23/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
|
Title:
|
MANUFACTURING METHODS FOR LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2016
|
Application #:
|
13748076
|
Filing Dt:
|
01/23/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH ENHANCED 3D RESURF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2014
|
Application #:
|
13748381
|
Filing Dt:
|
01/23/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
SYSTEMS AND METHOD FOR GYROSCOPE CALIBRATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/18/2014
|
Application #:
|
13748598
|
Filing Dt:
|
01/24/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
POWER SUPPLY FOR INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2014
|
Application #:
|
13748796
|
Filing Dt:
|
01/24/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
SIGMA-DELTA MODULATOR WITH TRIMMED REFERENCE VOLTAGE FOR QUANTIZER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13748798
|
Filing Dt:
|
01/24/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
METHODS AND STRUCTURES FOR DYNAMICALLY CALIBRATING REFERENCE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13748808
|
Filing Dt:
|
01/24/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
METHOD OF MAKING A NON-VOLATILE MEMORY (NVM) CELL STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/05/2016
|
Application #:
|
13749542
|
Filing Dt:
|
01/24/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/24/2014
| | | | |
|
Title:
|
VARIABLE DELAY AND SETUP TIME FLIP-FLOP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2015
|
Application #:
|
13750057
|
Filing Dt:
|
01/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
AREA-EFFICIENT HIGH VOLTAGE BIPOLAR-BASED ESD PROTECTION TARGETING NARROW DESIGN WINDOWS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13750419
|
Filing Dt:
|
01/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
10/31/2013
| | | | |
|
Title:
|
METHOD OF FORMING AN INTEGRATED CIRCUIT HAVING VARYING SUBSTRATE DEPTH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2015
|
Application #:
|
13750936
|
Filing Dt:
|
01/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
LAYOUT-OPTIMIZED RANDOM MASK DISTRIBUTION SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/20/2015
|
Application #:
|
13750956
|
Filing Dt:
|
01/25/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
CRYPTOGRAPHIC KEY DERIVATION DEVICE AND METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
|
Application #:
|
13751318
|
Filing Dt:
|
01/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2013
| | | | |
|
Title:
|
ELECTRONIC DEVICE MODULE WITH INTEGRATED ANTENNA STRUCTURE, AND RELATED MANUFACTURING METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13751548
|
Filing Dt:
|
01/28/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
PROGRAMMING A SPLIT GATE BIT CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13753034
|
Filing Dt:
|
01/29/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
MICROELECTROMECHANICAL SYSTEM DEVICES HAVING CRACK RESISTANT MEMBRANE STRUCTURES AND METHODS FOR THE FABRICATION THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13753047
|
Filing Dt:
|
01/29/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
Non-Volatile Memory Cells Having Carbon Impurities and Related Manufacturing Methods
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2014
|
Application #:
|
13753544
|
Filing Dt:
|
01/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
RELAXATION OSCILLATOR WITH SELF-BIASED COMPARATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2016
|
Application #:
|
13754086
|
Filing Dt:
|
01/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
SEMICONDUCITIVE CATECHOL GROUP ENCAPSULANT ADHESION PROMOTER FOR A PACKAGED ELECTRONIC DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/30/2014
|
Application #:
|
13754873
|
Filing Dt:
|
01/30/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
AMPLITUDE LOOP CONTROL FOR OSCILLATORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/2015
|
Application #:
|
13755606
|
Filing Dt:
|
01/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
|
Title:
|
Dynamic Healing Of Non-Volatile Memory Cells
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13755904
|
Filing Dt:
|
01/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
METHOD FOR FORMNG A SEMICONDUCTOR DEVICE ASSEMBLY HAVING A HEAT SPREADER
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13756248
|
Filing Dt:
|
01/31/2013
|
|
Publication #:
|
|
Pub Dt:
|
07/31/2014
| | | | |
|
Title:
|
NONVOLATILE MEMORY BITCELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2014
|
Application #:
|
13758263
|
Filing Dt:
|
02/04/2013
|
|
Title:
|
LEAD FRAME ARRAY PACKAGE WITH FLIP CHIP DIE ATTACH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2015
|
Application #:
|
13758268
|
Filing Dt:
|
02/04/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
Write Transaction Interpretation for Interrupt Assertion
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2014
|
Application #:
|
13759054
|
Filing Dt:
|
02/05/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
MEMORY ERROR MANAGEMENT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2015
|
Application #:
|
13759056
|
Filing Dt:
|
02/05/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
VOLTAGE SCALE-DOWN CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/18/2015
|
Application #:
|
13759241
|
Filing Dt:
|
02/05/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
ELECTROSTATIC DISCHARGE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2015
|
Application #:
|
13760109
|
Filing Dt:
|
02/06/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR MAINTAINING PACKET ORDER IN AN ORDERED DATA STREAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/2015
|
Application #:
|
13760465
|
Filing Dt:
|
02/06/2013
|
|
Publication #:
|
|
Pub Dt:
|
08/07/2014
| | | | |
|
Title:
|
STICTION RESISTANT MEMS DEVICE AND METHOD OF OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
13760882
|
Filing Dt:
|
02/06/2013
|
|
Publication #:
|
|
Pub Dt:
|
06/13/2013
| | | | |
|
Title:
|
METHODS FOR FABRICATING BIPOLAR TRANSISTORS WITH IMPROVED GAIN
|
|
