|
|
Patent #:
|
|
Issue Dt:
|
03/29/1994
|
Application #:
|
07295403
|
Filing Dt:
|
01/10/1989
|
Title:
|
CIRCUIT FOR PREVENTING FALSE PROGRAMMING OF ANTI-FUSE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/1991
|
Application #:
|
07379083
|
Filing Dt:
|
07/13/1989
|
Title:
|
METHOD AND APPARATUS FOR MAINTAINING ELECTRICALLY OPERATING DEVICE TEMPERATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/1992
|
Application #:
|
07609177
|
Filing Dt:
|
11/05/1990
|
Title:
|
MISALIGNMENT TOLERANT ANTIFUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/1992
|
Application #:
|
07633381
|
Filing Dt:
|
12/20/1990
|
Title:
|
METHOD AND APPARATUS FOR MAINTAINING ELECTRICALLY OPERATING DEVICE TEMPERATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/1992
|
Application #:
|
07638517
|
Filing Dt:
|
01/04/1991
|
Title:
|
APPARATUS FOR IMPROVING ANTIFUSE PROGRAMMING YIELD AND REDUCING ANTIFUSE PROGRAMMING TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1992
|
Application #:
|
07643384
|
Filing Dt:
|
01/18/1991
|
Title:
|
LOW VOLTAGE PROGRAMMING ANTIFUSE AND TRANSISTOR BREAKDOWN METHOD FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/21/1992
|
Application #:
|
07654966
|
Filing Dt:
|
02/13/1991
|
Title:
|
MIXED MODE ANALOG/DIGITAL PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/1992
|
Application #:
|
07687980
|
Filing Dt:
|
04/19/1991
|
Title:
|
CIRCUITS FOR PREVENTING BREAKDOWN OF LOW-VOLTAGE DEVICE INPUTS DURING HIGH VOLTAGE ANTIFUSE PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1993
|
Application #:
|
07743261
|
Filing Dt:
|
08/09/1991
|
Title:
|
ELECTRICALLY PROGRAMMABLE ANTIFUSE AND FABRICATION PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1993
|
Application #:
|
07773353
|
Filing Dt:
|
10/07/1991
|
Title:
|
LOGIC MODULE WITH CONFIGURABLE COMBINATIONAL AND SEQUENTIAL BLOCKS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/1995
|
Application #:
|
07790366
|
Filing Dt:
|
11/12/1991
|
Title:
|
ELECTRICALLY PROGRAMMABLE ANTIFUSE ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1993
|
Application #:
|
07817867
|
Filing Dt:
|
01/07/1992
|
Title:
|
MASK SURROGATE SEMICONDUCTOR PROCESS WITH POLYSILICON GATE PROTECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/1994
|
Application #:
|
07822490
|
Filing Dt:
|
01/14/1992
|
Title:
|
TESTABILITY ARCHITECTURE AND TECHNIQUES FOR PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1993
|
Application #:
|
07835221
|
Filing Dt:
|
02/13/1992
|
Title:
|
METHODS FOR PREVENTING DISTURBANCE OF ANTIFUSES DURING PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/1994
|
Application #:
|
07835711
|
Filing Dt:
|
02/12/1992
|
Title:
|
METHOD AND APPARATUS FOR MAINTAINING ELECTRICALLY OPERATING DEVICE TEMPERATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1993
|
Application #:
|
07852932
|
Filing Dt:
|
03/13/1992
|
Title:
|
IGBT PROCESS TO PRODUCE PLATINUM LIFETIME CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
02/16/1993
|
Application #:
|
07869488
|
Filing Dt:
|
04/15/1992
|
Title:
|
RECONFIGURABLE PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1998
|
Application #:
|
07877253
|
Filing Dt:
|
04/28/1992
|
Title:
|
PROCESS FOR FORMING OHMIC CONTACT FOR III-V SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/1992
|
Application #:
|
07888042
|
Filing Dt:
|
05/22/1992
|
Title:
|
PROCESS FOR FABRICATING ELECTRICALLY PROGRAMMABLE ANTIFUSE ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1993
|
Application #:
|
07889838
|
Filing Dt:
|
05/26/1992
|
Title:
|
TESTABILITY ARCHITECTURE AND TECHNIQUES FOR PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/15/1994
|
Application #:
|
07889839
|
Filing Dt:
|
05/26/1992
|
Title:
|
TESTABILITY ARCHITECTURE AND TECHNIQUES FOR PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1993
|
Application #:
|
07891969
|
Filing Dt:
|
05/26/1992
|
Title:
|
TESTABILITY ARCHITECTURE AND TECHNIQUES FOR PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1993
|
Application #:
|
07895620
|
Filing Dt:
|
06/09/1992
|
Title:
|
HIGH-YIELD METHODS FOR PROGRAMMING ANTIFUSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/1993
|
Application #:
|
07899729
|
Filing Dt:
|
06/17/1992
|
Title:
|
PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1993
|
Application #:
|
07901604
|
Filing Dt:
|
06/19/1992
|
Title:
|
CLOCK DISTRIBUTION SCHEME FOR USER-PROGRAMMABLE LOGIC ARRAY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/1994
|
Application #:
|
07901810
|
Filing Dt:
|
06/22/1992
|
Title:
|
VOLTAGE REFERENCE CIRCUIT WITH BREAKPOINT COMPENSATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1993
|
Application #:
|
07910422
|
Filing Dt:
|
07/08/1992
|
Title:
|
ELECTRICALLY-PROGRAMMABLE LOW-IMPEDANCE ANTI-FUSE ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1993
|
Application #:
|
07917524
|
Filing Dt:
|
07/17/1992
|
Title:
|
SEMICONDUCTOR DEVICE WITH DOPED ELECTRICAL BREAKDOWN CONTROL REGION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/1994
|
Application #:
|
07919605
|
Filing Dt:
|
07/24/1992
|
Title:
|
PROGRAMMABLE INTERCONNECT ARCHITECTURE EMPLOYING LEAKY PROGRAMMABLE ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/1994
|
Application #:
|
07927169
|
Filing Dt:
|
08/07/1992
|
Title:
|
HIGH DENSITY POWER DEVICE FABRICATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/1994
|
Application #:
|
07931717
|
Filing Dt:
|
08/18/1992
|
Title:
|
FPGA ARCHITECTURE INCLUDING DIRECT LOGIC FUNCTION CIRCUIT TO I/O INTERCONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/1994
|
Application #:
|
07945817
|
Filing Dt:
|
09/15/1992
|
Title:
|
IGBT DEVICE WITH PLATINUM LIFETIME CONTROL HAVING GRADIENT OR PROFILE TAILORED PLATINUM DIFFUSION REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/1994
|
Application #:
|
07947103
|
Filing Dt:
|
09/18/1992
|
Title:
|
METHODS FOR PROGRAMMING ANTIFUSES HAVING AT LEAST ONE METAL ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/1995
|
Application #:
|
07947275
|
Filing Dt:
|
09/18/1992
|
Title:
|
ELECTRICALLY PROGRAMMABLE ANTIFUSE HAVING A METAL TO METAL STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/1994
|
Application #:
|
07954111
|
Filing Dt:
|
09/30/1992
|
Title:
|
SERIES LINEAR ANTIFUSE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/1994
|
Application #:
|
07958879
|
Filing Dt:
|
10/07/1992
|
Title:
|
TESTABILITY ARCHITECTURE AND TECHNIQUES FOR PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/1994
|
Application #:
|
07971734
|
Filing Dt:
|
11/04/1992
|
Title:
|
ABOVE VIA METAL-TO-METAL ANTIFUSE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/1994
|
Application #:
|
07992055
|
Filing Dt:
|
12/17/1992
|
Title:
|
LOW-TEMPERATURE PROCESS METAL-TO-METAL ANTIFUSE EMPLOYING SILICON LINK
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/1994
|
Application #:
|
08002873
|
Filing Dt:
|
01/13/1993
|
Title:
|
PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/1995
|
Application #:
|
08004912
|
Filing Dt:
|
01/19/1993
|
Title:
|
ELECTRICALLY PROGRAMMABLE ANTIFUSE INCORPORATING DIELECTRIC AND AMORPHOUS SILICON INTERLAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/1995
|
Application #:
|
08028789
|
Filing Dt:
|
03/09/1993
|
Title:
|
LOGIC MODULE WITH CONFIGURABLE COMBINATIONAL AND SEQUENTIAL BLOCKS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/1995
|
Application #:
|
08030797
|
Filing Dt:
|
03/12/1993
|
Title:
|
METHOD FOR CONTROLLING ELECTRICAL BREAKDOWN IN SEMICONDUCTOR POWER DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/1994
|
Application #:
|
08038550
|
Filing Dt:
|
03/29/1993
|
Title:
|
LOW WATAGE DEVICE IN A HIGH VOLTAGE SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/1995
|
Application #:
|
08054612
|
Filing Dt:
|
04/29/1993
|
Title:
|
ELECTRICALLY-PROGRAMMABLE LOW-IMPEDANCE ANTI-FUSE ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/1994
|
Application #:
|
08058998
|
Filing Dt:
|
05/06/1993
|
Title:
|
METHODS FOR PROTECTING OUTPUTS OF LOW-VOLTAGE CIRCUITS FROM HIGH PROGRAMMING VOLTAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/06/1994
|
Application #:
|
08067381
|
Filing Dt:
|
05/26/1993
|
Title:
|
SIMULTANEOUS MULTIPLE ANTIFUSE PROGRAMMING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/29/1994
|
Application #:
|
08087942
|
Filing Dt:
|
07/07/1993
|
Title:
|
CIRCUITS FOR ESD PROTECTION OF METAL-TO-METAL ANTIFUSES DURING PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/21/1995
|
Application #:
|
08095264
|
Filing Dt:
|
07/21/1993
|
Title:
|
CLOCK DISTRIBUTION SCHEME FOR USER-PROGRAMMABLE LOGIC ARRAY ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/11/1995
|
Application #:
|
08102381
|
Filing Dt:
|
08/05/1993
|
Title:
|
TESTABILITY ARCHITECTURE AND TECHNIQUES FOR PROGRAMMABLE INTERCONNECT ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08106406
|
Filing Dt:
|
08/13/1993
|
Title:
|
SELF-ALIGNED POWER MOSFET DEVICE WITH RECESSED GATE AND SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/1995
|
Application #:
|
08109727
|
Filing Dt:
|
08/20/1993
|
Title:
|
FIELD PROGRAMMABLE DIGITAL SIGNAL PROCESSING ARRAY INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/1995
|
Application #:
|
08117955
|
Filing Dt:
|
09/08/1993
|
Title:
|
APPARATUS AND METHOD FOR MEASURING PROGRAMMED ANTIFUSE RESISTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/1997
|
Application #:
|
08126217
|
Filing Dt:
|
09/23/1993
|
Title:
|
ASSEMBLY, DISTRIBUTION, AND USE OF DIGITAL INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/1995
|
Application #:
|
08126545
|
Filing Dt:
|
09/24/1993
|
Title:
|
ANALOG-TO-DIGITAL CONVERTER WITH MULTI-LEVEL DITHER CURRENT INPUT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/1995
|
Application #:
|
08130636
|
Filing Dt:
|
10/01/1993
|
Title:
|
METHOD AND APPARATUS FOR PROTECTING CORDLESS TELEPHONE ACCOUNT AUTHENTICATION INFORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/1995
|
Application #:
|
08132548
|
Filing Dt:
|
10/06/1993
|
Title:
|
GRADUAL ON OUTPUT BUFFER CIRCUIT INCLUDING A REVERSE TURN-OFF APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/1996
|
Application #:
|
08140724
|
Filing Dt:
|
10/20/1993
|
Title:
|
FPGA ARCHITECTURE INCLUDING DIRECT LOGIC FUNCTION CIRCUIT TO I/O INTERCONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/1995
|
Application #:
|
08144452
|
Filing Dt:
|
10/27/1993
|
Title:
|
PROGRAMMABLE DEDICATED FPGA FUNCTIONAL BLOCKS FOR MULTIPLE WIDE-INPUT FUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/1995
|
Application #:
|
08146543
|
Filing Dt:
|
11/01/1993
|
Title:
|
LOW DISTORTION OPERATIONAL AMPLIFIER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/1995
|
Application #:
|
08149191
|
Filing Dt:
|
11/08/1993
|
Title:
|
FUSE TRIMMING IN PLASTIC PACKAGE DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/1996
|
Application #:
|
08151363
|
Filing Dt:
|
11/12/1993
|
Title:
|
BI-MODE CIRCUIT FOR DRIVING AN OUTPUT LOAD
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/1995
|
Application #:
|
08151512
|
Filing Dt:
|
11/12/1993
|
Title:
|
POWER SUPPLY CONTROLLER HAVING LOW STARTUP CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/1996
|
Application #:
|
08156612
|
Filing Dt:
|
11/22/1993
|
Title:
|
ANTIFUSE STRUCTURE SUITABLE FOR VLSI APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/1996
|
Application #:
|
08158977
|
Filing Dt:
|
11/30/1993
|
Title:
|
TESTABILITY CIRCUITS FOR LOGIC ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/1995
|
Application #:
|
08168103
|
Filing Dt:
|
12/14/1993
|
Title:
|
LOW DISTORTION OUTPUT STAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/1995
|
Application #:
|
08168628
|
Filing Dt:
|
12/16/1993
|
Title:
|
LOW NOISE APPARATUS FOR RECEIVING AN INPUT CURRENT AND PRODUCING AN OUTPUT CURRENT WHICH MIRRORS THE INPUT CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/10/1995
|
Application #:
|
08172132
|
Filing Dt:
|
12/21/1993
|
Title:
|
METAL-TO-METAL ANTIFUSE INCLUDING ETCH STOP LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/1995
|
Application #:
|
08174117
|
Filing Dt:
|
12/28/1993
|
Title:
|
BATTERY FEED FOR TELEPHONE LINE CARDS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/1995
|
Application #:
|
08184564
|
Filing Dt:
|
01/21/1994
|
Title:
|
METERING SIGNAL LEVEL CONTROL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/1997
|
Application #:
|
08190325
|
Filing Dt:
|
01/31/1994
|
Title:
|
HIGH DENSITY POWER DEVICE FABRICATION PROCESS USING UNDERCUT OXIDE SIDEWALLS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08191818
|
Filing Dt:
|
02/04/1994
|
Title:
|
METHOD AND APPARATUS FOR IMPROVED LINK ESTABLISHMENT AND MONITORING IN A COMMUNICATIONS SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/1997
|
Application #:
|
08191948
|
Filing Dt:
|
02/04/1994
|
Title:
|
INPUT/OUTPUT DATA PORT WITH A PARALLEL AND SERIAL INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08192046
|
Filing Dt:
|
02/04/1994
|
Title:
|
DUAL-MODE BASEBAND CONTROLLER FOR RADIO-FREQUENCY INTERFACES RELATING TO DIGITAL CORDLESS TELEPHONES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/18/1997
|
Application #:
|
08224148
|
Filing Dt:
|
04/07/1994
|
Title:
|
EMULATION SYSTEM EMPLOYING MOTHERBOARD AND FLEXIBLE DAUGHTERBOARDS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/1996
|
Application #:
|
08231634
|
Filing Dt:
|
04/22/1994
|
Title:
|
ELECTRICALLY PROGRAMMABLE ANTIFUSE INCORPORATING DIELECTRIC AND AMORPHOUS SILICON INTERLAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/1996
|
Application #:
|
08243001
|
Filing Dt:
|
06/01/1993
|
Title:
|
METHOD OF FORMING ANTIFUSES HAVING MINIMUM AREAS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/1995
|
Application #:
|
08246218
|
Filing Dt:
|
05/19/1994
|
Title:
|
PROGRAMMABLE LOGIC MODULE AND ARCHITECTURE FOR FIELD PROGRAMMABLE GATE ARRAY DEVICE
|
|
|
Patent #:
|
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Issue Dt:
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04/23/1996
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Application #:
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08247243
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Filing Dt:
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06/10/1993
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Title:
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METAL-TO-METAL ANTIFUSE WITH IMPROVED DIFFUSION BARRIER LAYER
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Patent #:
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Issue Dt:
|
05/07/1996
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Application #:
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08254660
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Filing Dt:
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06/03/1994
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Title:
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PULSE DETECTION AND CONDITIONING CIRCUIT
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Patent #:
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Issue Dt:
|
11/21/1995
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Application #:
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08255160
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Filing Dt:
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06/07/1994
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Title:
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APPARATUS AND METHOD FOR DETERMINING THE RESISTANCE OF ANTIFUSES IN AN ARRAY
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Patent #:
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Issue Dt:
|
07/09/1996
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Application #:
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08264883
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Filing Dt:
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06/24/1994
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Title:
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ANALOG INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
05/07/1996
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Application #:
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08265930
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Filing Dt:
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06/27/1994
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Title:
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DIGITAL REGENERATIVE COMPARATOR
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Patent #:
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|
Issue Dt:
|
12/02/1997
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Application #:
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08273572
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Filing Dt:
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07/11/1994
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Title:
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DISTRIBUTED RAMP DELAY GENERATOR
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Patent #:
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|
Issue Dt:
|
05/21/1996
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Application #:
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08277673
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Filing Dt:
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07/19/1994
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Title:
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CIRCUITS FOR ESD PROTECTION OF METAL-TO-METAL ANTIFUSES DURING PROCESSING
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Patent #:
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Issue Dt:
|
09/09/1997
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Application #:
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08278423
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Filing Dt:
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07/21/1994
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Title:
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DISCIPLINED TIME SCALE GENERATOR FOR PRIMARY REFERENCE CLOCKS
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Patent #:
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|
Issue Dt:
|
11/07/1995
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Application #:
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08282145
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Filing Dt:
|
07/28/1994
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Title:
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METHOD OF FABRICATING AN ANTIFUSE ELEMENT HAVING AN ETCH-STOP DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08284054
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Filing Dt:
|
08/01/1994
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Title:
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METAL-TO-METAL ANTIFUSE WITH CONDUCTIVE
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Patent #:
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|
Issue Dt:
|
03/25/1997
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Application #:
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08286359
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Filing Dt:
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08/05/1994
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Title:
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CURRENT SYNCHRONOUS ZERO VOLTAGE SWITCHING RESONANT TOPOLOGY
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Patent #:
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|
Issue Dt:
|
05/02/1995
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Application #:
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08287214
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Filing Dt:
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08/08/1994
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Title:
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FUSE TRIMMING IN PLASTIC PACKAGE DEVICES
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Patent #:
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|
Issue Dt:
|
01/09/1996
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Application #:
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08287724
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Filing Dt:
|
08/09/1994
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Title:
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LOW-TEMPERATURE PROCESS METAL-TO-METAL ANTIFUSE EMPLOYING SILICON LINK
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Patent #:
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|
Issue Dt:
|
12/03/1996
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Application #:
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08289114
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Filing Dt:
|
08/11/1994
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Title:
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DIELECTRIC-POLYSILICON-DIELECTRIC ANTIFUSE FOR FIELD PROGRAMMABLE LOGIC APPLICATIONS
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|
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Patent #:
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|
Issue Dt:
|
11/05/1996
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Application #:
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08289678
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Filing Dt:
|
08/12/1994
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Title:
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ESD PROTECTION DEVICE FOR ANTIFUSES WITH TOP POLYSILICON ELECTRODE
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|
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Patent #:
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|
Issue Dt:
|
03/12/1996
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Application #:
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08290029
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Filing Dt:
|
08/12/1994
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Title:
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PROCESS ESD PROTECTION DEVICES FOR USE WITH ANTIFUSES
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|
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Patent #:
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|
Issue Dt:
|
09/23/1997
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Application #:
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08291422
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Filing Dt:
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08/16/1994
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Title:
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ELECTRICALLY PROGRAMMABLE ANTIFUSE
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|
|
Patent #:
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|
Issue Dt:
|
08/27/1996
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Application #:
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08292801
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Filing Dt:
|
08/10/1994
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Title:
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ELECTRICALLY PROGRAMMABLE ANTIFUSE HAVING STAIR APERTURE
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|
|
Patent #:
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|
Issue Dt:
|
03/25/1997
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Application #:
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08303045
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Filing Dt:
|
09/08/1994
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Title:
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TESTABILITY CIRCUITS FOR LOGIC CIRCUIT ARRAYS
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Patent #:
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|
Issue Dt:
|
06/18/1996
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Application #:
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08314101
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Filing Dt:
|
09/28/1994
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Title:
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TELEPHONE BATTERY FEED CIRCUIT INCLUDING NOISE REDUCTION CIRCUIT
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Patent #:
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|
Issue Dt:
|
07/23/1996
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Application #:
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08315829
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Filing Dt:
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09/30/1994
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Title:
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TRANSIENT VOLTAGE SUPPRESSOR APPARATUS
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|
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Patent #:
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|
Issue Dt:
|
07/16/1996
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Application #:
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08316022
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Filing Dt:
|
09/30/1994
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Title:
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ANTIFUSE-BASED FPGA ARCHITECTURE WITHOUT HIGH-VOLTAGE ISOLATION TRANSISTORS
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|
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Patent #:
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|
Issue Dt:
|
07/30/1996
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Application #:
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08319170
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Filing Dt:
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10/06/1994
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Title:
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METAL TO METAL ANTIFUSE
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|