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Reel/Frame:037684/0039   Pages: 448
Recorded: 02/02/2016
Attorney Dkt #:040981-0072
Conveyance: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031)
Total properties: 11127
Page 95 of 112
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112
1
Patent #:
8566496
Issue Dt:
10/22/2013
Application #:
12960118
Filing Dt:
12/03/2010
Publication #:
US20120144082
Pub Dt:
06/07/2012
Title:
DATA PREFETCH IN SAS EXPANDERS
2
Patent #:
8856439
Issue Dt:
10/07/2014
Application #:
12960214
Filing Dt:
12/03/2010
Publication #:
US20120144111
Pub Dt:
06/07/2012
Title:
METHOD AND DEVICE FOR UTILIZING APPLICATION-LEVEL PRIOR KNOWLEDGE FOR SELECTIVELY STORING DATA IN HIGHER PERFORMANCE MEDIA
3
Patent #:
8854983
Issue Dt:
10/07/2014
Application #:
12960279
Filing Dt:
12/03/2010
Publication #:
US20120140840
Pub Dt:
06/07/2012
Title:
DATA PATH UTILIZATION FOR LOW LEVEL PATTERN GENERATION AND CHECKIING
4
Patent #:
8527698
Issue Dt:
09/03/2013
Application #:
12963048
Filing Dt:
12/08/2010
Publication #:
US20110314218
Pub Dt:
12/22/2011
Title:
PARITY-BASED RAID SYSTEM CONFIGURED TO PROTECT AGAINST DATA CORRUPTION CAUSED BY THE OCCURRENCE OF WRITE HOLES
5
Patent #:
8499137
Issue Dt:
07/30/2013
Application #:
12963895
Filing Dt:
12/09/2010
Publication #:
US20110225376
Pub Dt:
09/15/2011
Title:
MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
6
Patent #:
8289643
Issue Dt:
10/16/2012
Application #:
12964431
Filing Dt:
12/09/2010
Publication #:
US20120147493
Pub Dt:
06/14/2012
Title:
PHASE CALIBRATION SYSTEM FOR DISK DRIVES
7
Patent #:
NONE
Issue Dt:
Application #:
12965136
Filing Dt:
12/10/2010
Publication #:
US20120151150
Pub Dt:
06/14/2012
Title:
Cache Line Fetching and Fetch Ahead Control Using Post Modification Information
8
Patent #:
8446896
Issue Dt:
05/21/2013
Application #:
12965969
Filing Dt:
12/13/2010
Publication #:
US20110261917
Pub Dt:
10/27/2011
Title:
Time Synchronization Using Packet-Layer and Physical-Layer Protocols
9
Patent #:
8583874
Issue Dt:
11/12/2013
Application #:
12967155
Filing Dt:
12/14/2010
Publication #:
US20120151149
Pub Dt:
06/14/2012
Title:
Method and Apparatus for Caching Prefetched Data
10
Patent #:
NONE
Issue Dt:
Application #:
12968297
Filing Dt:
12/15/2010
Publication #:
US20120158652
Pub Dt:
06/21/2012
Title:
SYSTEM AND METHOD FOR ENSURING CONSISTENCY IN RAID STORAGE ARRAY METADATA
11
Patent #:
8532240
Issue Dt:
09/10/2013
Application #:
12968538
Filing Dt:
01/03/2011
Publication #:
US20120170621
Pub Dt:
07/05/2012
Title:
DECOUPLING SAMPLING CLOCK AND ERROR CLOCK IN A DATA EYE
12
Patent #:
7944237
Issue Dt:
05/17/2011
Application #:
12969424
Filing Dt:
12/15/2010
Publication #:
US20110084726
Pub Dt:
04/14/2011
Title:
ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS
13
Patent #:
8473648
Issue Dt:
06/25/2013
Application #:
12969601
Filing Dt:
12/16/2010
Publication #:
US20120159474
Pub Dt:
06/21/2012
Title:
SYSTEM AND METHOD OF I/O PATH VIRTUALIZATION BETWEEN A RAID CONTROLLER AND AN ENVIRONMENT SERVICE MODULE IN A STORAGE AREA NETWORK
14
Patent #:
8987137
Issue Dt:
03/24/2015
Application #:
12969836
Filing Dt:
12/16/2010
Publication #:
US20120153492
Pub Dt:
06/21/2012
Title:
METHOD OF FABRICATION OF THROUGH-SUBSTRATE VIAS
15
Patent #:
8742535
Issue Dt:
06/03/2014
Application #:
12969852
Filing Dt:
12/16/2010
Publication #:
US20120153430
Pub Dt:
06/21/2012
Title:
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
16
Patent #:
8324927
Issue Dt:
12/04/2012
Application #:
12970071
Filing Dt:
12/16/2010
Publication #:
US20110084725
Pub Dt:
04/14/2011
Title:
HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
17
Patent #:
9292562
Issue Dt:
03/22/2016
Application #:
12971355
Filing Dt:
12/17/2010
Publication #:
US20120158682
Pub Dt:
06/21/2012
Title:
SCATTER-GATHER LIST USAGE FOR A CONFIGURATION DATABASE RETRIEVE AND RESTORE FUNCTION AND DATABASE BLOCKING AND CONFIGURATION CHANGES DURING A DATABASE RESTORE PROCESS
18
Patent #:
8943507
Issue Dt:
01/27/2015
Application #:
12971742
Filing Dt:
12/17/2010
Publication #:
US20110222540
Pub Dt:
09/15/2011
Title:
PACKET ASSEMBLY MODULE FOR MULTI-CORE, MULTI-THREAD NETWORK PROCESSORS
19
Patent #:
8463992
Issue Dt:
06/11/2013
Application #:
12972427
Filing Dt:
12/18/2010
Publication #:
US20120159067
Pub Dt:
06/21/2012
Title:
SYSTEM AND METHOD FOR HANDLING IO TO DRIVES IN A RAID SYSTEM BASED ON STRIP SIZE
20
Patent #:
8397023
Issue Dt:
03/12/2013
Application #:
12972432
Filing Dt:
12/18/2010
Publication #:
US20120159070
Pub Dt:
06/21/2012
Title:
SYSTEM AND METHOD FOR HANDLING IO TO DRIVES IN A MEMORY CONSTRAINED ENVIRONMENT
21
Patent #:
8577402
Issue Dt:
11/05/2013
Application #:
12972692
Filing Dt:
12/20/2010
Publication #:
US20120157008
Pub Dt:
06/21/2012
Title:
METHOD FOR AVOIDING OVERFLOW OF MULTIPLICATION OF ROOTS-OF-UNITY BY USING OVERFLOW SAFE APPROXIMATED VALUES TABLE
22
Patent #:
8411385
Issue Dt:
04/02/2013
Application #:
12972904
Filing Dt:
12/20/2010
Publication #:
US20120155587
Pub Dt:
06/21/2012
Title:
SYSTEMS AND METHODS FOR IMPROVED TIMING RECOVERY
23
Patent #:
8838660
Issue Dt:
09/16/2014
Application #:
12972942
Filing Dt:
12/20/2010
Publication #:
US20120158810
Pub Dt:
06/21/2012
Title:
Systems and Methods for Reducing Filter Sensitivities
24
Patent #:
8704506
Issue Dt:
04/22/2014
Application #:
12973098
Filing Dt:
12/20/2010
Publication #:
US20120153924
Pub Dt:
06/21/2012
Title:
VOLTAGE REGULATOR SOFT-START CIRCUIT PROVIDING REFERENCE VOLTAGE RAMP-UP
25
Patent #:
8738818
Issue Dt:
05/27/2014
Application #:
12973906
Filing Dt:
12/21/2010
Publication #:
US20120159007
Pub Dt:
06/21/2012
Title:
APPARATUS AND METHOD FOR ANALYZING BIDIRECTIONAL DATA EXCHANGED BETWEEN TWO ELECTRONIC DEVICES
26
Patent #:
8503584
Issue Dt:
08/06/2013
Application #:
12974039
Filing Dt:
12/21/2010
Publication #:
US20120155579
Pub Dt:
06/21/2012
Title:
EFFICIENT IMPLEMENTATION OF M-ALGORITHM BASED ON QR DECOMPOSITION FOR HIGHER-ORDER CONSTELLATIONS
27
Patent #:
NONE
Issue Dt:
Application #:
12974096
Filing Dt:
12/21/2010
Publication #:
US20120158684
Pub Dt:
06/21/2012
Title:
PERFORMANCE ENHANCED SYNCHRONIZATION MECHANISM WITH INTENSITY-ORIENTED READER API
28
Patent #:
8441842
Issue Dt:
05/14/2013
Application #:
12974441
Filing Dt:
12/21/2010
Publication #:
US20120155151
Pub Dt:
06/21/2012
Title:
MEMORY DEVICE HAVING MEMORY CELLS WITH ENHANCED LOW VOLTAGE WRITE CAPABILITY
29
Patent #:
8910171
Issue Dt:
12/09/2014
Application #:
12974477
Filing Dt:
12/21/2010
Publication #:
US20110222552
Pub Dt:
09/15/2011
Title:
THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
30
Patent #:
9166774
Issue Dt:
10/20/2015
Application #:
12974601
Filing Dt:
12/21/2010
Publication #:
US20120155530
Pub Dt:
06/21/2012
Title:
DECOUPLING BANG-BANG CDR AND DFE
31
Patent #:
8594172
Issue Dt:
11/26/2013
Application #:
12974678
Filing Dt:
12/21/2010
Publication #:
US20120155528
Pub Dt:
06/21/2012
Title:
ADAPTATION OF BASELINE WANDER CORRECTION LOOP GAIN SETTINGS
32
Patent #:
8959291
Issue Dt:
02/17/2015
Application #:
12974943
Filing Dt:
12/21/2010
Publication #:
US20110302376
Pub Dt:
12/08/2011
Title:
TWO-PORT MEMORY CAPABLE OF SIMULTANEOUS READ AND WRITE
33
Patent #:
8505013
Issue Dt:
08/06/2013
Application #:
12975823
Filing Dt:
12/22/2010
Publication #:
US20110225588
Pub Dt:
09/15/2011
Title:
REDUCING DATA READ LATENCY IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
34
Patent #:
8514874
Issue Dt:
08/20/2013
Application #:
12975880
Filing Dt:
12/22/2010
Publication #:
US20110222553
Pub Dt:
09/15/2011
Title:
THREAD SYNCHRONIZATION IN A MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
35
Patent #:
8464257
Issue Dt:
06/11/2013
Application #:
12976021
Filing Dt:
12/22/2010
Publication #:
US20120167079
Pub Dt:
06/28/2012
Title:
METHOD AND SYSTEM FOR REDUCING POWER LOSS TO BACKUP IO START TIME OF A STORAGE DEVICE IN A STORAGE VIRTUALIZATION ENVIRONMENT
36
Patent #:
8868889
Issue Dt:
10/21/2014
Application #:
12976045
Filing Dt:
12/22/2010
Publication #:
US20110225394
Pub Dt:
09/15/2011
Title:
INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
37
Patent #:
8935483
Issue Dt:
01/13/2015
Application #:
12976228
Filing Dt:
12/22/2010
Publication #:
US20110225372
Pub Dt:
09/15/2011
Title:
CONCURRENT, COHERENT CACHE ACCESS FOR MULTIPLE THREADS IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR
38
Patent #:
8819700
Issue Dt:
08/26/2014
Application #:
12976418
Filing Dt:
12/22/2010
Publication #:
US20120167115
Pub Dt:
06/28/2012
Title:
SYSTEM AND METHOD FOR SYNCHRONOUS INTER-THREAD COMMUNICATION
39
Patent #:
8387871
Issue Dt:
03/05/2013
Application #:
12976788
Filing Dt:
12/22/2010
Publication #:
US20120160914
Pub Dt:
06/28/2012
Title:
TAMPER RESISTANT RFID TAG CIRCUIT APPARATUS AND METHOD
40
Patent #:
8484416
Issue Dt:
07/09/2013
Application #:
12978165
Filing Dt:
12/23/2010
Publication #:
US20120166724
Pub Dt:
06/28/2012
Title:
HIGH AVAILABILITY RAID USING LOW-COST DIRECT ATTACHED RAID CONTROLLERS
41
Patent #:
8510493
Issue Dt:
08/13/2013
Application #:
12978719
Filing Dt:
12/27/2010
Publication #:
US20120166730
Pub Dt:
06/28/2012
Title:
CIRCUIT TO EFFICIENTLY HANDLE DATA MOVEMENT WITHIN A CACHE CONTROLLER OR ON-CHIP MEMORY PERIPHERAL
42
Patent #:
8671245
Issue Dt:
03/11/2014
Application #:
12978810
Filing Dt:
12/27/2010
Publication #:
US20120166694
Pub Dt:
06/28/2012
Title:
USING IDENTIFICATION IN CACHE MEMORY FOR PARALLEL REQUESTS
43
Patent #:
8489791
Issue Dt:
07/16/2013
Application #:
12979551
Filing Dt:
12/28/2010
Publication #:
US20120005391
Pub Dt:
01/05/2012
Title:
PROCESSOR BUS BRIDGE SECURITY FEATURE FOR NETWORK PROCESSORS OR THE LIKE
44
Patent #:
8489792
Issue Dt:
07/16/2013
Application #:
12979665
Filing Dt:
12/28/2010
Publication #:
US20110225337
Pub Dt:
09/15/2011
Title:
TRANSACTION PERFORMANCE MONITORING IN A PROCESSOR BUS BRIDGE
45
Patent #:
8638136
Issue Dt:
01/28/2014
Application #:
12979705
Filing Dt:
12/28/2010
Publication #:
US20120161825
Pub Dt:
06/28/2012
Title:
START-UP SYSTEM AND METHOD FOR SWITCHING VOLTAGE REGULATOR
46
Patent #:
8489794
Issue Dt:
07/16/2013
Application #:
12979800
Filing Dt:
12/28/2010
Publication #:
US20110225334
Pub Dt:
09/15/2011
Title:
PROCESSOR BUS BRIDGE FOR NETWORK PROCESSORS OR THE LIKE
47
Patent #:
8438641
Issue Dt:
05/07/2013
Application #:
12980489
Filing Dt:
12/29/2010
Publication #:
US20120174216
Pub Dt:
07/05/2012
Title:
SECURITY PROTOCOL PROCESSING FOR ANTI-REPLAY PROTECTION
48
Patent #:
8924778
Issue Dt:
12/30/2014
Application #:
12981355
Filing Dt:
12/29/2010
Publication #:
US20120173953
Pub Dt:
07/05/2012
Title:
METHOD TO SYNCHRONIZE A REPLACEMENT CONTROLLER'S FIRMWARE VERSION TO THE NATIVE CONFIGURATION DATABASE VERSION ON A SIMPLEX ARRAY
49
Patent #:
8397025
Issue Dt:
03/12/2013
Application #:
12981486
Filing Dt:
12/30/2010
Publication #:
US20120173844
Pub Dt:
07/05/2012
Title:
APPARATUS AND METHOD FOR DETERMINING A CACHE LINE IN AN N-WAY SET ASSOCIATIVE CACHE USING HASH FUNCTIONS
50
Patent #:
8521931
Issue Dt:
08/27/2013
Application #:
12981847
Filing Dt:
12/30/2010
Publication #:
US20120173783
Pub Dt:
07/05/2012
Title:
SERIAL INPUT OUTPUT (SIO) PORT EXPANSION APPARATUS AND METHOD
51
Patent #:
8521933
Issue Dt:
08/27/2013
Application #:
12982104
Filing Dt:
12/30/2010
Publication #:
US20120173781
Pub Dt:
07/05/2012
Title:
ROUND ROBIN ARBITER WITH MASK AND RESET MASK
52
Patent #:
8599959
Issue Dt:
12/03/2013
Application #:
12982129
Filing Dt:
12/30/2010
Publication #:
US20120170678
Pub Dt:
07/05/2012
Title:
METHODS AND APPARATUS FOR TRELLIS-BASED MODULATION ENCODING
53
Patent #:
8693593
Issue Dt:
04/08/2014
Application #:
12982220
Filing Dt:
12/30/2010
Publication #:
US20120170695
Pub Dt:
07/05/2012
Title:
METHODS AND APPARATUS FOR AUTOMATIC GAIN CONTROL USING SAMPLES TAKEN AT DESIRED SAMPLING PHASE AND TARGET VOLTAGE LEVEL
54
Patent #:
8707078
Issue Dt:
04/22/2014
Application #:
12982240
Filing Dt:
12/30/2010
Publication #:
US20120173914
Pub Dt:
07/05/2012
Title:
Methods and Apparatus for Trimming of CDR Clock Buffer Using Histogram of Clock-Like Data Pattern
55
Patent #:
NONE
Issue Dt:
Application #:
12982430
Filing Dt:
12/30/2010
Publication #:
US20120173812
Pub Dt:
07/05/2012
Title:
METHOD AND SYSTEM FOR DATA DISTRIBUTION ACROSS AN ARRAY OF DRIVES
56
Patent #:
8656233
Issue Dt:
02/18/2014
Application #:
12982642
Filing Dt:
12/30/2010
Publication #:
US20120173939
Pub Dt:
07/05/2012
Title:
SCAN CELL DESIGNS WITH SERIAL AND PARALLEL LOADING OF TEST DATA
57
Patent #:
NONE
Issue Dt:
Application #:
12983080
Filing Dt:
12/31/2010
Publication #:
US20120173840
Pub Dt:
07/05/2012
Title:
SAS EXPANDER CONNECTION ROUTING TECHNIQUES
58
Patent #:
8489935
Issue Dt:
07/16/2013
Application #:
12983996
Filing Dt:
01/04/2011
Publication #:
US20110099426
Pub Dt:
04/28/2011
Title:
SYSTEM FOR INJECTING PROTOCOL SPECIFIC ERRORS DURING THE CERTIFICATION OF COMPONENTS IN A STORAGE AREA NETWORK
59
Patent #:
8223264
Issue Dt:
07/17/2012
Application #:
12983999
Filing Dt:
01/04/2011
Publication #:
US20110096231
Pub Dt:
04/28/2011
Title:
METHOD FOR VIDEO DEINTERLACING AND FORMAT CONVERSION
60
Patent #:
8473792
Issue Dt:
06/25/2013
Application #:
12985604
Filing Dt:
01/06/2011
Publication #:
US20120179946
Pub Dt:
07/12/2012
Title:
LOGIC BIST FOR SYSTEM TESTING USING STORED PATTERNS
61
Patent #:
NONE
Issue Dt:
Application #:
12985850
Filing Dt:
01/06/2011
Publication #:
US20110099454
Pub Dt:
04/28/2011
Title:
Low Complexity LDPC Encoding Algorithm
62
Patent #:
8498073
Issue Dt:
07/30/2013
Application #:
12992929
Filing Dt:
11/16/2010
Publication #:
US20120019946
Pub Dt:
01/26/2012
Title:
SYSTEMS AND METHODS FOR ADAPTIVE BASELINE COMPENSATION
63
Patent #:
8675298
Issue Dt:
03/18/2014
Application #:
12992933
Filing Dt:
11/16/2010
Publication #:
US20110093517
Pub Dt:
04/21/2011
Title:
SYSTEMS AND METHODS FOR ADAPTIVE TARGET SEARCH
64
Patent #:
8462455
Issue Dt:
06/11/2013
Application #:
12992940
Filing Dt:
11/16/2010
Publication #:
US20110063746
Pub Dt:
03/17/2011
Title:
SYSTEMS AND METHODS FOR IMPROVED SERVO DATA OPERATION
65
Patent #:
8441753
Issue Dt:
05/14/2013
Application #:
12992943
Filing Dt:
11/16/2010
Publication #:
US20110164332
Pub Dt:
07/07/2011
Title:
SYSTEMS AND METHODS FOR REDUCING LOW FREQUENCY LOSS IN A MAGNETIC STORAGE DEVICE
66
Patent #:
8484535
Issue Dt:
07/09/2013
Application #:
12994288
Filing Dt:
11/23/2010
Publication #:
US20120030539
Pub Dt:
02/02/2012
Title:
ERROR-FLOOR MITIGATION OF CODES USING WRITE VERIFICATION
67
Patent #:
8539218
Issue Dt:
09/17/2013
Application #:
12995225
Filing Dt:
11/30/2010
Publication #:
US20110078433
Pub Dt:
03/31/2011
Title:
SYSTEMS AND METHODS FOR USING AN INSTALLATION SCRIPT TO CREATE A HIDDEN BOOT PARTITION TO INSTALL A BOOTABLE VIRTUAL STORAGE APPLIANCE ON A VIRTUALIZED SERVER PLATFORM
68
Patent #:
8713267
Issue Dt:
04/29/2014
Application #:
12995792
Filing Dt:
12/02/2010
Publication #:
US20110078398
Pub Dt:
03/31/2011
Title:
METHOD AND SYSTEM FOR DYNAMIC STORAGE TIERING USING ALLOCATE-ON-WRITE SNAPSHOTS
69
Patent #:
8462549
Issue Dt:
06/11/2013
Application #:
13001278
Filing Dt:
02/25/2011
Publication #:
US20110141815
Pub Dt:
06/16/2011
Title:
METHODS AND APPARATUS FOR READ-SIDE INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES
70
Patent #:
8526230
Issue Dt:
09/03/2013
Application #:
13001286
Filing Dt:
03/09/2011
Publication #:
US20110149657
Pub Dt:
06/23/2011
Title:
METHODS AND APPARATUS FOR WRITE-SIDE INTERCELL INTERFERENCE MITIGATION IN FLASH MEMORIES
71
Patent #:
8634250
Issue Dt:
01/21/2014
Application #:
13001295
Filing Dt:
02/25/2011
Publication #:
US20110141808
Pub Dt:
06/16/2011
Title:
Methods and Apparatus for Programming Multiple Program Values Per Signal Level in Flash Memories
72
Patent #:
8677056
Issue Dt:
03/18/2014
Application #:
13001300
Filing Dt:
02/25/2011
Publication #:
US20110138114
Pub Dt:
06/09/2011
Title:
METHODS AND APPARATUS FOR INTERFACING BETWEEN A FLASH MEMORY CONTROLLER AND A FLASH MEMORY ARRAY
73
Patent #:
8797795
Issue Dt:
08/05/2014
Application #:
13001310
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Title:
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Assignor
1
DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Exec Dt:
02/01/2016
Assignees
1
LSI CORPORATION
1320 RIDDER PARK DRIVE
SAN JOSE, CALIFORNIA 95131
2
AGERE SYSTEMS LLC
1110 AMERICAN PARKWAY NE
ALLENTOWN, PENNSYLVANIA 18109
Correspondence name and address
LATHAM & WATKINS LLP
650 TOWN CENTER DRIVE, SUITE 2000
COSTA MESA, CA 92626

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