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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
10/08/2002
Application #:
09141841
Filing Dt:
08/27/1998
Title:
APPARATUS AND METHOD FOR FORMING FEATURES ON A SUBSTRATE
2
Patent #:
Issue Dt:
06/05/2001
Application #:
09141866
Filing Dt:
08/28/1998
Title:
SUPERCRITICAL COMPOSITIONS FOR REMOVAL OF ORGANIC MATERIAL AND METHODS OF USING SAME
3
Patent #:
Issue Dt:
03/28/2000
Application #:
09143044
Filing Dt:
08/28/1998
Title:
SEMICONDUCTOR WAFER ALIGNMENT PROCESSES
4
Patent #:
Issue Dt:
08/29/2000
Application #:
09143164
Filing Dt:
08/28/1998
Title:
MEMORY CIRCUIT HAVING IMPROVED SENSE-AMPLIFIER BLOCK AND METHOD FOR FORMING SAME
5
Patent #:
Issue Dt:
10/26/1999
Application #:
09143229
Filing Dt:
08/28/1998
Title:
ANTI-FUSE PROGRAMMING PATH
6
Patent #:
Issue Dt:
11/21/2000
Application #:
09143289
Filing Dt:
08/28/1998
Title:
PLASMA TREATMENT OF AN INTERCONNECT SURFACE DURING FORMATION OF AN INTERLAYER DIELECTRIC
7
Patent #:
Issue Dt:
01/02/2001
Application #:
09143526
Filing Dt:
08/28/1998
Title:
APPARATUS FOR ELECTRICALLY COUPLING BOND OF A MICROELECTRONIC DEVICE
8
Patent #:
Issue Dt:
08/24/2004
Application #:
09143585
Filing Dt:
08/31/1998
Title:
SELECTIVELY DOPED TRENCH DEVICE ISOLATION
9
Patent #:
Issue Dt:
11/02/1999
Application #:
09143602
Filing Dt:
08/31/1998
Title:
ELECTRICALLY CONDUCTIVE SUBSTRATE INTERCONNECT CONTINUITY REGION AND METHOD OF FORMING SAME WITH AN ANGLED IMPLANT
10
Patent #:
Issue Dt:
12/12/2000
Application #:
09143604
Filing Dt:
08/31/1998
Title:
ENBEDDED MEMORY ASSEMBLY
11
Patent #:
Issue Dt:
08/08/2000
Application #:
09143631
Filing Dt:
08/28/1998
Title:
METHOD AND APPARATUS FOR ALIGNING AND ATTACHING BALLS TO A SUBSTRATE
12
Patent #:
Issue Dt:
04/17/2001
Application #:
09143729
Filing Dt:
08/31/1998
Title:
STRUCTURE AND METHOD FOR AN ELECTRONIC ASSEMBLY
13
Patent #:
Issue Dt:
09/18/2001
Application #:
09143765
Filing Dt:
08/31/1998
Title:
METHOD AND APPARATUS FOR A SEMICONDUCTOR PACKAGE FOR VERTICAL SURFACE MOUNTING
14
Patent #:
Issue Dt:
05/21/2002
Application #:
09143880
Filing Dt:
08/31/1998
Title:
SILICON INTERPOSER WITH OPTICAL CONNECTIONS
15
Patent #:
Issue Dt:
02/20/2001
Application #:
09143996
Filing Dt:
08/31/1998
Title:
METHOD OF FORMING A SOLDER BALL
16
Patent #:
Issue Dt:
08/28/2001
Application #:
09144290
Filing Dt:
08/31/1998
Title:
STRUCTURE AND METHOD FOR A HIGH PERFORMANCE ELECTRONIC PACKAGING ASSEMBLY
17
Patent #:
Issue Dt:
07/01/2003
Application #:
09144307
Filing Dt:
08/31/1998
Title:
COMPACT SYSTEM MODULE WITH BUILT-IN THERMOELECTRIC COOLING
18
Patent #:
Issue Dt:
08/28/2001
Application #:
09144308
Filing Dt:
08/31/1998
Title:
ERROR CORRECTION CHIP FOR MEMORY APPLICATIONS
19
Patent #:
Issue Dt:
08/17/1999
Application #:
09144457
Filing Dt:
09/01/1998
Title:
STRAPPED WORDLINE ARCHITECTURE FOR SEMICONDUCTOR MEMORY
20
Patent #:
Issue Dt:
12/19/2000
Application #:
09144484
Filing Dt:
08/31/1998
Title:
METHOD OF INHIBITING DEPOSITION OF MATERIAL ON AN INTERNAL WALL OF A CHEMICAL VAPOR DEPOSITION REACTOR
21
Patent #:
Issue Dt:
05/16/2000
Application #:
09144512
Filing Dt:
08/31/1998
Title:
TRANSISTOR DEVICE STRUCTURES, AND METHODS FOR FORMING SUCH STRUCTURES
22
Patent #:
Issue Dt:
09/26/2000
Application #:
09144536
Filing Dt:
08/31/1998
Title:
SLURRIES FOR MECHANICAL OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC-DEVICE SUBSTRATE ASSEMBLIES, AND METHODS AND APPARATUSES FOR MAKING AND USING SUCH SLURRIES
23
Patent #:
Issue Dt:
03/27/2001
Application #:
09144546
Filing Dt:
09/01/1998
Title:
METHOD AND APPARATUS FOR PERFORMING ERROR CORRECTION ON DATA READ FROM A MULTISTATE MEMORY
24
Patent #:
Issue Dt:
08/31/1999
Application #:
09144736
Filing Dt:
09/01/1998
Title:
VOLTAGE GENERATOR METHODS AND APPARATUS
25
Patent #:
Issue Dt:
05/01/2001
Application #:
09144745
Filing Dt:
09/01/1998
Title:
METHOD FOR FORMING METAL-CONTAINING FILMS USING METAL COMPLEXES WITH CHELATING O- AND/OR N-DONOR LIGANDS
26
Patent #:
Issue Dt:
09/14/1999
Application #:
09144807
Filing Dt:
09/01/1998
Title:
SEMICONDUCTOR PROGRAMMABLE TEST ARRANGEMENT SUCH AS AN ANTIFUSE ID CIRCUIT HAVING COMMON ACCESS SWITCHES AND/OR COMMON PROGRAMMING SWITCHES
27
Patent #:
Issue Dt:
12/19/2000
Application #:
09144857
Filing Dt:
09/01/1998
Title:
CLEANING COMPOSITIONS FOR HIGH DIELECTRIC STRUCTURES AND METHODS OF USING SAME
28
Patent #:
Issue Dt:
04/10/2001
Application #:
09144912
Filing Dt:
09/01/1998
Title:
METAL COMPLEXES WITH CHELATING C-, N-DONOR LIGANDS FOR FORMING METAL- CONTAINING FILMS
29
Patent #:
Issue Dt:
10/03/2000
Application #:
09145065
Filing Dt:
09/01/1998
Title:
METHOD AND APPARATUS FOR REDUCING INDUCED SWITCHING TRANSIENTS
30
Patent #:
Issue Dt:
08/10/1999
Application #:
09145099
Filing Dt:
09/01/1998
Title:
SYSTEM AND METHOD FOR AN ANTIFUSE BANK
31
Patent #:
Issue Dt:
02/04/2003
Application #:
09145106
Filing Dt:
09/02/1998
Title:
PASSIVATION LAYER FOR PACKAGED INTEGRATED CIRCUITS
32
Patent #:
Issue Dt:
08/15/2000
Application #:
09145373
Filing Dt:
09/02/1998
Title:
ISOLATED INTERCONNECT STUDS AND METHOD FOR FORMING THE SAME
33
Patent #:
Issue Dt:
08/27/2002
Application #:
09145400
Filing Dt:
09/01/1998
Publication #:
Pub Dt:
11/22/2001
Title:
MICROELECTRONIC SUBSTRATE ASSEMBLY PLANARIZING MACHINES AND METHODS OF MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATE ASSEMBLIES
34
Patent #:
Issue Dt:
08/14/2001
Application #:
09145437
Filing Dt:
09/02/1998
Title:
METAL CONTACT AND PROCESS
35
Patent #:
Issue Dt:
03/14/2000
Application #:
09145488
Filing Dt:
09/01/1998
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES AND METHODS OF FORMING FIELD EMISSION DISPLAYS
36
Patent #:
Issue Dt:
09/12/2000
Application #:
09145491
Filing Dt:
09/01/1998
Title:
SEMICONDUCTOR ETCHING METHODS
37
Patent #:
Issue Dt:
05/30/2000
Application #:
09145492
Filing Dt:
09/01/1998
Title:
SEMICONDUCTOR WAFER ALIGNMENT METHODS
38
Patent #:
Issue Dt:
06/06/2000
Application #:
09145582
Filing Dt:
09/02/1998
Title:
CIRCUIT AND METHOD FOR A MEMORY CELL USING REVERSE BASE CURRENT EFFECT
39
Patent #:
Issue Dt:
08/20/2002
Application #:
09145720
Filing Dt:
09/02/1998
Publication #:
Pub Dt:
01/10/2002
Title:
ADJUSTABLE I/O TIMING FROM EXTERNALLY APPLIED VOLTAGE
40
Patent #:
Issue Dt:
06/18/2002
Application #:
09145722
Filing Dt:
09/02/1998
Publication #:
Pub Dt:
02/07/2002
Title:
FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM FLOATING GATE
41
Patent #:
Issue Dt:
08/31/1999
Application #:
09145734
Filing Dt:
09/02/1998
Title:
SYSTEM AND METHOD FOR CHANGING THE CONNECTED BEHAVIOR OF A CIRCUIT DESIGN SCHEMATIC
42
Patent #:
Issue Dt:
12/26/2000
Application #:
09145744
Filing Dt:
09/02/1998
Title:
METHOD AND APPARATUS FOR CONTROLLING TIMING OF DIGITAL COMPONENTS
43
Patent #:
Issue Dt:
09/19/2000
Application #:
09145758
Filing Dt:
09/02/1998
Title:
METHOD OF SORTING A GROUP OF INTEGRATED CIRCUIT DEVICES FOR THOSE DEVICES REQUIRING SPECIAL TESTING
44
Patent #:
Issue Dt:
04/03/2001
Application #:
09145784
Filing Dt:
09/02/1998
Title:
FORMING METAL SILICIDE RESISTANT TO SUBSEQUENT THERMAL PROCESSING
45
Patent #:
Issue Dt:
09/19/2000
Application #:
09145832
Filing Dt:
09/02/1998
Title:
METHOD AND PROCESS OF CONTACT TO A HEAT SOFTENED SOLDER BALL ARRAY
46
Patent #:
Issue Dt:
12/07/1999
Application #:
09145849
Filing Dt:
09/02/1998
Title:
METHOD AND APPARATUS FOR STRESS TESTING A SEMICONDUCTOR MEMORY
47
Patent #:
Issue Dt:
02/08/2000
Application #:
09145865
Filing Dt:
09/02/1998
Title:
METHOD AND APPARATUS FOR MULTIPLE ROW ACTIVATION IN MEMORY DEVICES
48
Patent #:
Issue Dt:
10/10/2000
Application #:
09145866
Filing Dt:
09/02/1998
Title:
METHOD AND CIRCUIT FOR PROVIDING A MEMORY DEVICE HAVING HIDDEN ROW ACCESS AND ROW PRECHARGE TIMES
49
Patent #:
Issue Dt:
08/28/2001
Application #:
09146003
Filing Dt:
09/02/1998
Title:
METHODS AND SYSTEMS FOR FORMING METAL-CONTAINING FILMS ON SUBSTRATES
50
Patent #:
Issue Dt:
08/22/2000
Application #:
09146056
Filing Dt:
09/02/1998
Title:
METHODS OF MANUFACTURING MICORELECTRONIC SUSBSTRATE ASSEMBLIES FOR USE IN PLANARIZATION PROCESSES
51
Patent #:
Issue Dt:
08/21/2001
Application #:
09146113
Filing Dt:
09/02/1998
Title:
SEMICONDUCTOR PROCESSING METHODS AND INTEGRATED CIRCUITRY
52
Patent #:
Issue Dt:
10/31/2000
Application #:
09146117
Filing Dt:
09/02/1998
Title:
METHODS OF FORMING VOID REGIONS DIELECTRIC REGIONS AND CAPACITOR CONSTRUCTIONS
53
Patent #:
Issue Dt:
07/17/2001
Application #:
09146292
Filing Dt:
09/03/1998
Title:
DIRECT WRITING OF LOW CARBON CONDUCTIVE MATERIAL
54
Patent #:
Issue Dt:
09/25/2001
Application #:
09146293
Filing Dt:
09/03/1998
Title:
ANTI-REFLECTIVE COATINGS AND METHODS FOR FORMING AND USING SAME
55
Patent #:
Issue Dt:
04/18/2000
Application #:
09146295
Filing Dt:
09/03/1998
Title:
CIRCUIT AND METHOD FOR PERFORMING TEST ON MEMORY ARRAY CELLS USING EXTERNAL SENSE AMPLIFIER REFERENCE CURRENT
56
Patent #:
Issue Dt:
04/29/2003
Application #:
09146296
Filing Dt:
09/03/1998
Title:
METHODS OF PASSIVATING AN OXIDE SURFACE SUBJECTED TO A CONDUCTIVE MATERIAL ANNEAL
57
Patent #:
Issue Dt:
09/04/2001
Application #:
09146297
Filing Dt:
09/03/1998
Title:
METHOD FOR PRODUCING LOW CARBON/OXYGEN CONDUCTIVE LAYERS
58
Patent #:
Issue Dt:
02/20/2001
Application #:
09146298
Filing Dt:
09/03/1998
Title:
MINI FLASH PROCESS AND CIRCUIT
59
Patent #:
Issue Dt:
03/20/2001
Application #:
09146300
Filing Dt:
09/03/1998
Title:
LOW TEMPERATURE DEPOSITION OF BARRIER LAYERS
60
Patent #:
Issue Dt:
12/05/2000
Application #:
09146301
Filing Dt:
09/03/1998
Title:
COMPACT SOI BODY CONTACT LINK
61
Patent #:
Issue Dt:
04/04/2000
Application #:
09146330
Filing Dt:
09/02/1998
Title:
METHOD AND APPARATUS FOR ENDPOINTING MECHANICAL AND CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATES
62
Patent #:
Issue Dt:
11/07/2000
Application #:
09146365
Filing Dt:
09/03/1998
Title:
RUTHENIUM AND RUTHENIUM DIOXIDE REMOVAL METHOD AND MATERIAL
63
Patent #:
Issue Dt:
04/17/2001
Application #:
09146408
Filing Dt:
09/03/1998
Title:
METHOD OF PATTERNING METAL LAYERS BY ANNEALING A METAL LAYER FORMED OVER A PATTERNED METAL-CONTAINING ADHESION LAYER
64
Patent #:
Issue Dt:
05/22/2001
Application #:
09146417
Filing Dt:
09/03/1998
Title:
SEMICONDUCTOR DEVICE HAVING A BUILT-IN HEAT SINK AND PROCESS OF MANUFACTURING SAME
65
Patent #:
Issue Dt:
01/23/2001
Application #:
09146447
Filing Dt:
09/03/1998
Title:
METHOD AND APPARATUS FOR PERFORMING ERROR CORRECTION ON DATA READ FROM A MULTISTATE MEMORY
66
Patent #:
Issue Dt:
04/17/2001
Application #:
09146472
Filing Dt:
09/03/1998
Title:
MEMORY DEVICE WITH LOCAL WRITE DATA LATCHES
67
Patent #:
Issue Dt:
05/28/2002
Application #:
09146488
Filing Dt:
09/03/1998
Title:
SEMICONDUCTOR DEVICE WITH HEAT-DISSIPATING LEAD-FRAME AND PROCESS OF MANUFACTURING SAME
68
Patent #:
Issue Dt:
02/13/2001
Application #:
09146509
Filing Dt:
09/03/1998
Title:
SMALL GRAIN SIZE, CONFORMAL ALUMINUM INTERCONNECTS AND METHOD FOR THEIR FORMATION
69
Patent #:
Issue Dt:
08/07/2001
Application #:
09146556
Filing Dt:
09/03/1998
Title:
METHODS FOR FORMING RHODIUM-CONTAINING LAYERS SUCH AS PLATINUM-RHODIUM BARRIER LAYERS
70
Patent #:
Issue Dt:
09/14/1999
Application #:
09146586
Filing Dt:
09/03/1998
Title:
METHOD AND APPARATUS FOR REMAPPING ADDRESSES FOR REDUNDANCY
71
Patent #:
Issue Dt:
10/24/2000
Application #:
09146622
Filing Dt:
09/03/1998
Title:
METHODS FOR FORMING PHOSPHORUS- AND/OR BORON-CONTAINING SILICA LAYERS ON SUBSTRATES
72
Patent #:
Issue Dt:
04/16/2002
Application #:
09146629
Filing Dt:
09/03/1998
Title:
CIRCUIT, SYSTEM AND METHOD FOR ARRANGING DATA OUTPUT BY SEMICONDUCTOR TESTERS TO PACKET-BASED DEVICES UNDER TEST
73
Patent #:
Issue Dt:
11/26/2002
Application #:
09146639
Filing Dt:
09/03/1998
Publication #:
Pub Dt:
01/03/2002
Title:
LOW RESISTANCE SEMICONDUCTOR PROCESS AND STRUCTURES
74
Patent #:
Issue Dt:
11/16/1999
Application #:
09146640
Filing Dt:
09/03/1998
Title:
METHOD FOR PULSED-PLASMA ENHANCED VAPOR DEPOSITION
75
Patent #:
Issue Dt:
07/04/2000
Application #:
09146643
Filing Dt:
09/03/1998
Title:
CAVITY BALL GRID ARRAY APPARATUS
76
Patent #:
Issue Dt:
04/30/2002
Application #:
09146674
Filing Dt:
09/03/1998
Title:
TREATMENT FOR FILM SURFACE TO REDUCE PHOTO FOOTING
77
Patent #:
Issue Dt:
07/23/2002
Application #:
09146688
Filing Dt:
09/03/1998
Publication #:
Pub Dt:
01/10/2002
Title:
APPARATUS AND METHOD FOR TESTING FUSES
78
Patent #:
Issue Dt:
01/02/2001
Application #:
09146689
Filing Dt:
09/03/1998
Title:
SPIN COATING BOWL
79
Patent #:
Issue Dt:
10/31/2000
Application #:
09146691
Filing Dt:
09/03/1998
Title:
SPIN COATING BOWL
80
Patent #:
Issue Dt:
06/11/2002
Application #:
09146695
Filing Dt:
09/03/1998
Publication #:
Pub Dt:
11/01/2001
Title:
HEAT DISSIPATING MICROELECTRONIC PACKAGE
81
Patent #:
Issue Dt:
02/29/2000
Application #:
09146702
Filing Dt:
09/03/1998
Title:
BELT-FEED TRIM AND FORM APPARATUS
82
Patent #:
Issue Dt:
08/29/2000
Application #:
09146709
Filing Dt:
09/03/1998
Title:
METHODS FOR SIMULTANEOUSLY ELECTRICALLY AND MECHANICALLY ATTACHING LEAD FRAMES TO SEMICONDUCTOR DICE AND THE RESULTING ELEMENTS
83
Patent #:
Issue Dt:
03/27/2001
Application #:
09146715
Filing Dt:
09/03/1998
Title:
TEST CARRIER FOR PACKAGING SEMICONDUCTOR COMPONENTS HAVING CONTACT BALLS AND CALIBRATION CARRIER FOR CALIBRATING SEMICONDUCTOR TEST SYSTEMS
84
Patent #:
Issue Dt:
08/14/2001
Application #:
09146730
Filing Dt:
09/03/1998
Title:
METHODS OF FORMING MATERIALS WITHIN OPENINGS, AND METHOD OF FORMING ISOLATION REGIONS
85
Patent #:
Issue Dt:
05/30/2000
Application #:
09146731
Filing Dt:
09/03/1998
Title:
METHODS OF FORMING LAYERS OF PARTICULATES ON SUBSTRATES
86
Patent #:
Issue Dt:
03/20/2001
Application #:
09146733
Filing Dt:
09/03/1998
Title:
METHOD AND APPARATUS FOR INCREASING CHEMICAL-MECHANICAL-POLISING SELECTIVITY
87
Patent #:
Issue Dt:
09/12/2000
Application #:
09146744
Filing Dt:
09/03/1998
Title:
USING SILICIDE CAP AS AN ETCH STOP FOR MULTILAYER METAL PROCESS AND STRUCTURES SO FORMED
88
Patent #:
Issue Dt:
06/05/2001
Application #:
09146840
Filing Dt:
09/03/1998
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING CONTACT OPENINGS METHODS OF FORMING ELECTRICAL CONNECTIONS AND INTERCONNECTIONS AND INTEGRATED CIRCUITRY
89
Patent #:
Issue Dt:
07/31/2001
Application #:
09146841
Filing Dt:
09/03/1998
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING AND UTILIZING ANTIREFLECTIVE MATERIAL LAYERS, AND METHODS OF FORMING TRANSISTOR GATE STACKS
90
Patent #:
Issue Dt:
08/28/2001
Application #:
09146842
Filing Dt:
09/03/1998
Title:
SEMICONDUCTOR PROCESSING METHODS
91
Patent #:
Issue Dt:
02/15/2000
Application #:
09146844
Filing Dt:
09/03/1998
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING SUBSTRATE FEATURES, INCLUDING CONTACT OPENINGS
92
Patent #:
Issue Dt:
05/29/2001
Application #:
09146850
Filing Dt:
09/03/1998
Title:
SACRIFICIAL GERMANIUM LAYER FOR FORMATION OF A CONTACT
93
Patent #:
Issue Dt:
09/12/2000
Application #:
09146945
Filing Dt:
09/03/1998
Title:
ATTACHMENT METHOD FOR HEAT SINKS AND DEVICES INVOLVING REMOVAL OF MISPLACED ENCAPSULANT
94
Patent #:
Issue Dt:
08/13/2002
Application #:
09146946
Filing Dt:
09/03/1998
Title:
METHOD AND APPARATUS FOR COUPLING SIGNALS ACROSS DIFFERENT CLOCK DOMAINS, AND MEMORY DEVICE AND COMPUTER SYSTEM USING SAME
95
Patent #:
Issue Dt:
05/29/2001
Application #:
09148089
Filing Dt:
09/03/1998
Title:
METHODS FOR FORMING IRIDIUM-CONTAINING FILMS ON SUBSTRATES
96
Patent #:
Issue Dt:
01/02/2001
Application #:
09148371
Filing Dt:
09/04/1998
Title:
CHEMICAL VAPOR DEPOSITIONS PROCESS FOR DEPOSITING TITANIUM SILICIDE FILMS FROM AN ORGANOMETALLIC COMPOUND
97
Patent #:
Issue Dt:
08/22/2000
Application #:
09149514
Filing Dt:
09/08/1998
Title:
PACKAGING FOR BARE DICE EMPLOYING EMR-SENSITIVE ADHESIVES
98
Patent #:
Issue Dt:
04/18/2000
Application #:
09149705
Filing Dt:
09/08/1998
Title:
DEPOSITION CHAMBER WITH A BIASED SUBSTRATE CONFIGURATION
99
Patent #:
Issue Dt:
10/03/2000
Application #:
09150289
Filing Dt:
09/09/1998
Title:
System For Optimizing The Testing And Repair Time Of A Defective Intergrated Circuit
100
Patent #:
Issue Dt:
10/24/2000
Application #:
09150858
Filing Dt:
09/10/1998
Title:
SEMICONDUCTOR WAFER, WAFER ALIGNMENT PATTERNS AND METHOD OF FORMING WAFER ALIGNMENT PATTERNS
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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