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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:038669/0001   Pages: 961
Recorded: 05/12/2016
Attorney Dkt #:4816.228
Conveyance: SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
02/29/2000
Application #:
09208041
Filing Dt:
12/09/1998
Title:
MEMBRANE-ACTUATED CHARGE CONTROLLED MIRROR (CCM) PROJECTION DISPLAY
2
Patent #:
Issue Dt:
09/19/2000
Application #:
09208146
Filing Dt:
12/09/1998
Title:
FAST, LOW POWER, WRITE SCHEME FOR MEMORY CIRCUITS USING PULSED OFF ISOLATION DEVICE
3
Patent #:
Issue Dt:
01/30/2001
Application #:
09208679
Filing Dt:
12/10/1998
Title:
APPARATUS FOR FILLING A GAP BETWEEN SPACED LAYERS OF A SEMICONDUCTOR
4
Patent #:
Issue Dt:
09/26/2000
Application #:
09208907
Filing Dt:
12/10/1998
Title:
DEVICE ASSEMBLY FACILITATING GAP FILLING BETWEEN SPACED LAYERS OF SEMICONDUCTOR SUBSTRATES
5
Patent #:
Issue Dt:
01/30/2001
Application #:
09209210
Filing Dt:
12/10/1998
Title:
DEVICE AND METHOD FOR ELECTROSTATIC DISCHARGE PROTECTION OF A CIRCUIT DEVICE
6
Patent #:
Issue Dt:
04/25/2000
Application #:
09209319
Filing Dt:
12/09/1998
Title:
SENSING CIRCUITRY FOR READING AND VERIFYING THE CONTENTS OF ELECTRICALLY PROGRAMMABLE/ERASABLE NON-VOLATILE MEMORY CELLS
7
Patent #:
Issue Dt:
03/20/2001
Application #:
09209325
Filing Dt:
12/11/1998
Title:
MULTIPLE IMPLANTATION AND GRAIN GROWTH METHOD
8
Patent #:
Issue Dt:
10/31/2000
Application #:
09209330
Filing Dt:
12/11/1998
Title:
LOW POWER SUPPLY CMOS DIFFERENTIAL AMPLIFIER TOPOLOGY
9
Patent #:
Issue Dt:
12/19/2000
Application #:
09210013
Filing Dt:
12/11/1998
Title:
DIE PADDLE CLAMPING METHOD FOR WIRE BOND ENHANCEMENT
10
Patent #:
Issue Dt:
07/04/2000
Application #:
09211662
Filing Dt:
12/15/1998
Title:
BI-LEVEL DIGIT LINE ARCHITECTURE FOR HIGH DENSITY DRAMS
11
Patent #:
Issue Dt:
08/14/2001
Application #:
09212896
Filing Dt:
12/16/1998
Title:
SELF-TEST AND CORRECTION OF LOSS OF CHARGE ERRORS IN A FLASH MEMORY, ERASABLE AND PROGRAMMABLE BY SECTORS THEREOF
12
Patent #:
Issue Dt:
07/03/2001
Application #:
09213220
Filing Dt:
12/17/1998
Title:
CYCLIC MULTICASTING OR ASYNCHRONOUS BROADCASTING OF COMPUTER FILES
13
Patent #:
Issue Dt:
07/02/2002
Application #:
09213573
Filing Dt:
12/17/1998
Publication #:
Pub Dt:
12/13/2001
Title:
INTERCONNECT FOR TESTING SEMICONDUCTOR DICE HAVING RAISED BOND PADS
14
Patent #:
Issue Dt:
04/01/2003
Application #:
09213697
Filing Dt:
12/17/1998
Title:
INTERCONNECT ALLOYS AND METHODS AND APPARATUS USING SAME
15
Patent #:
Issue Dt:
03/13/2001
Application #:
09213742
Filing Dt:
12/17/1998
Title:
STEPPED PHOTORESIST PROFILE AND OPENING FORMED USING THE PROFILE
16
Patent #:
Issue Dt:
02/05/2002
Application #:
09214726
Filing Dt:
02/16/1999
Title:
DEFECTIVE MEMORY BLOCK HANDLING SYSTEM BY ADDRESSING A GROUP OF MEMORY BLOCKS FOR ERASURE AND CHANGING THE CONTENT THEREAFTER
17
Patent #:
Issue Dt:
12/11/2001
Application #:
09215270
Filing Dt:
12/18/1998
Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
18
Patent #:
Issue Dt:
02/04/2003
Application #:
09216580
Filing Dt:
12/18/1998
Title:
TACTILE TRACKING SYSTEMS AND METHODS
19
Patent #:
Issue Dt:
01/02/2001
Application #:
09216661
Filing Dt:
12/18/1998
Title:
METHOD OF MAKING A METALLIZED RECESS IN A SUBSTRATE
20
Patent #:
Issue Dt:
06/12/2001
Application #:
09217032
Filing Dt:
12/21/1998
Title:
CONTROLLED MOTION LIFT MECHANISM
21
Patent #:
Issue Dt:
07/17/2001
Application #:
09217039
Filing Dt:
12/21/1998
Title:
LASER MARKING STATION WITH ENCLOSURE AND METHOD OF OPERATION
22
Patent #:
Issue Dt:
07/09/2002
Application #:
09217040
Filing Dt:
12/21/1998
Title:
LASER MARKING SYSTEM FOR DICE CARRIED IN TRAYS AND METHOD OF OPERATION
23
Patent #:
Issue Dt:
09/12/2000
Application #:
09217321
Filing Dt:
12/21/1998
Title:
APPARATUS AND METHOD FOR SWITCHING BETWEEN TWO POWER SUPPLIES OF AN INTEGRATED CIRCUIT
24
Patent #:
Issue Dt:
07/04/2000
Application #:
09217323
Filing Dt:
12/21/1998
Title:
METHOD AND APPARATUS FOR INCREASING COMPARATOR GAIN WITHOUT AFFECTING STANDBY CURRENT
25
Patent #:
Issue Dt:
08/08/2000
Application #:
09218791
Filing Dt:
12/21/1998
Title:
FORMATION OF A SELF-ALIGNED INTEGRATED CIRCUIT STRUCTURE USING PLANARIZATION TO FORM A TOP SURFACE
26
Patent #:
Issue Dt:
02/06/2001
Application #:
09218860
Filing Dt:
12/22/1998
Title:
METHOD FOR FORMING A FLOATING GATE SEMICONDUCTOR DEVICE HAVING A PORTION WITHIN A RECESS.
27
Patent #:
Issue Dt:
04/03/2001
Application #:
09219181
Filing Dt:
12/22/1998
Title:
LASER ABLATIVE REMOVAL OF PHOTORESIST
28
Patent #:
Issue Dt:
06/05/2001
Application #:
09219501
Filing Dt:
12/21/1998
Title:
SHUTTLE ASSEMBLY FOR TRAY HANDLING
29
Patent #:
Issue Dt:
09/04/2001
Application #:
09220127
Filing Dt:
12/23/1998
Title:
DATA PROTECTION METHOD FOR A SEMICONDUCTOR MEMORY AND CORRESPONDING PROTECTED MEMORY DEVICE
30
Patent #:
Issue Dt:
09/05/2000
Application #:
09220892
Filing Dt:
12/28/1998
Title:
METHOD FOR REPAIRING PHASE SHIFTING MASKS
31
Patent #:
Issue Dt:
08/01/2000
Application #:
09220893
Filing Dt:
12/28/1998
Title:
METHOD FOR REPAIRING ALTERNATING PHASE SHIFTING MASKS
32
Patent #:
Issue Dt:
08/21/2001
Application #:
09220895
Filing Dt:
12/28/1998
Title:
METHOD FOR REPAIRING MOSI ATTENUATED PHASE SHIFT MASKS.
33
Patent #:
Issue Dt:
11/13/2007
Application #:
09220910
Filing Dt:
12/24/1998
Publication #:
Pub Dt:
08/08/2002
Title:
SYSTEM AND METHOD FOR AUTOMATICALLY IDENTIFYING AND ATTACHING RELATED DOCUMENTS
34
Patent #:
Issue Dt:
05/14/2002
Application #:
09221210
Filing Dt:
12/23/1998
Publication #:
Pub Dt:
01/10/2002
Title:
METHOD FOR CONTROLLING OUT OF ORDER ACCESSING TO A MULTIBANK MEMORY
35
Patent #:
Issue Dt:
05/09/2000
Application #:
09221233
Filing Dt:
12/23/1998
Title:
QUANTUM MAGNETIC MEMORY
36
Patent #:
Issue Dt:
05/13/2003
Application #:
09221301
Filing Dt:
12/23/1998
Publication #:
Pub Dt:
01/03/2002
Title:
APPARATUS FOR CONTROLLING A MULTIBANK MEMORY DEVICE
37
Patent #:
Issue Dt:
05/23/2000
Application #:
09221451
Filing Dt:
12/28/1998
Title:
COMBINED CACHE TAG AND DATA MEMORY ARCHITECTURE
38
Patent #:
Issue Dt:
06/25/2002
Application #:
09221537
Filing Dt:
12/28/1998
Title:
REMOVING HEAT FROM INTEGRATED CIRCUIT DEVICES MOUNTED ON A SUPPORT STRUCTURE
39
Patent #:
Issue Dt:
03/20/2001
Application #:
09221861
Filing Dt:
12/29/1998
Title:
NUCLEATION AND DEPOSITION OF PT FILMS USING ULTRAVIOLET IRRADIATION
40
Patent #:
Issue Dt:
05/30/2000
Application #:
09222022
Filing Dt:
12/29/1998
Title:
ROW DECODER CIRCUIT FOR AN ELECTRONIC MEMORY DEVICE, PARTICULARLY FOR LOW VOLTAGE APPLICATIONS
41
Patent #:
Issue Dt:
05/22/2001
Application #:
09222070
Filing Dt:
12/29/1998
Title:
METHOD AND A RELATED CIRCUIT FOR ADJUSTING THE DURATION OF A SYNCHRONIZATION SIGNAL ATD FOR TIMING THE ACCESS TO A NON-VOLATILE MEMORY
42
Patent #:
Issue Dt:
09/05/2000
Application #:
09222521
Filing Dt:
12/29/1998
Title:
HEALING CELLS IN A MEMORY DEVICE
43
Patent #:
Issue Dt:
08/22/2000
Application #:
09222565
Filing Dt:
12/29/1998
Title:
METHOD FOR IMPROVING THICKNESS UNIFORMITY OF DEPOSITED OZONE-TEOS SILICATE GLASS LAYERS
44
Patent #:
Issue Dt:
03/27/2001
Application #:
09222572
Filing Dt:
12/28/1998
Title:
METHOD AND APPARATUS FOR STOPPING MECHANICAL AND CHEMICAL MECHANICAL PLANARIZATION OF SUBTRATES AT DESIRED ENDPOINTS
45
Patent #:
Issue Dt:
12/12/2000
Application #:
09222674
Filing Dt:
12/29/1998
Title:
APPARATUS AMD METHOD FOR DISABLING AND RE-ENABLING ACCESS TO IC TEST FUNCTIONS
46
Patent #:
Issue Dt:
08/15/2000
Application #:
09223000
Filing Dt:
12/30/1998
Title:
METHOD FOR REPAIRING BUMP AND DIVOT DEFECTS IN A PHASE SHIFTING MASK
47
Patent #:
Issue Dt:
09/24/2002
Application #:
09223059
Filing Dt:
12/30/1998
Title:
METHOD OF FABRICATING TAPE ATTACHMENT CHIP-ON-BOARD ASSEMBLIES
48
Patent #:
Issue Dt:
07/24/2001
Application #:
09223621
Filing Dt:
12/30/1998
Title:
ESD PROTECTION NETWORK FOR CIRCUIT STRUCTURES FORMED IN A SEMICONDUCTOR
49
Patent #:
Issue Dt:
12/19/2000
Application #:
09223811
Filing Dt:
12/31/1998
Title:
HOT PLUG STRUCTURE AND METHOD FOR ENGAGING/DISENGAGING PCI COMPLIANT CARD
50
Patent #:
Issue Dt:
08/07/2001
Application #:
09224030
Filing Dt:
12/31/1998
Title:
ARRANGEMENT AND METHOD FOR PROVIDING FLEXIBLE MANAGEMENT OF A NETWORK
51
Patent #:
Issue Dt:
02/22/2000
Application #:
09224330
Filing Dt:
12/31/1998
Title:
HIGH VOLTAGE DRIVER CIRCUIT FOR A DECODING CIRCUIT IN MULTILEVEL NON-VOLATILE MEMORY DEVICES
52
Patent #:
Issue Dt:
07/17/2001
Application #:
09224924
Filing Dt:
01/04/1999
Title:
INTERCONNECT WITH PRESSURE SENSING MECHANISM FOR TESTING SEMICONDUCTOR WAFERS
53
Patent #:
Issue Dt:
04/25/2000
Application #:
09225133
Filing Dt:
01/04/1999
Title:
METHOD AND APPARATUS FOR LEAKAGE BLOCKING
54
Patent #:
Issue Dt:
11/30/1999
Application #:
09225277
Filing Dt:
01/05/1999
Title:
APPARATUS AND METHOD FOR FACILITATING CIRCUIT BOARD PROCESSING
55
Patent #:
Issue Dt:
05/09/2000
Application #:
09225593
Filing Dt:
01/06/1999
Title:
SELF-ALIGNED CONTACT PLUGS
56
Patent #:
Issue Dt:
10/03/2000
Application #:
09225811
Filing Dt:
01/05/1999
Title:
CANCELLATION OF REDUNDANT ELEMENTS WITH A CANCEL BANK
57
Patent #:
Issue Dt:
06/18/2002
Application #:
09225893
Filing Dt:
01/04/1999
Publication #:
Pub Dt:
01/31/2002
Title:
METHOD OF FORMING FLASH MEMORY, METHOD OF FORMING FLASH MEMORY AND SRAM CIRCUITRY, AND ETCHING METHODS
58
Patent #:
Issue Dt:
12/19/2000
Application #:
09225927
Filing Dt:
01/05/1999
Title:
MEMORY CARD WHICH IS THERMALLY CONTROLLED
59
Patent #:
Issue Dt:
07/04/2000
Application #:
09225938
Filing Dt:
01/06/1999
Title:
SYNCHRONOUS MEMORY WITH PROGRAMMABLE READ LATENCY
60
Patent #:
Issue Dt:
02/29/2000
Application #:
09225939
Filing Dt:
01/06/1999
Title:
SYNCHRONOUS MEMORY WITH PROGRAMMABLE READ LATENCY
61
Patent #:
Issue Dt:
05/15/2001
Application #:
09226052
Filing Dt:
01/05/1999
Title:
INTERCONNECT HAVING RECESSED CONTACT MEMBERS WITH PENETRATING BLADES FOR TESTING SEMICONDUCTOR DICE AND PACKAGES WITH CONTACT BUMPS
62
Patent #:
Issue Dt:
03/20/2001
Application #:
09226053
Filing Dt:
01/05/1999
Title:
METHOD OF DEPOSITING A SMOOTH CONFORMAL ALUMINUM FILM ON A REFRACTORY METAL NITRIDE LAYER
63
Patent #:
Issue Dt:
04/09/2002
Application #:
09226804
Filing Dt:
01/06/1999
Title:
DATA-FLOW METHOD OF ANALYZING DEFINITIONS AND USES OF L VALUES IN PROGRAMS
64
Patent #:
Issue Dt:
01/09/2001
Application #:
09226924
Filing Dt:
01/06/1999
Title:
UNIVERSAL PULSE SYNCHRONIZER
65
Patent #:
Issue Dt:
12/12/2000
Application #:
09227072
Filing Dt:
01/05/1999
Title:
USE OF PALLADIUM IN IC MANUFACTURING
66
Patent #:
Issue Dt:
11/30/1999
Application #:
09227391
Filing Dt:
01/08/1999
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING A CONTACT OPENING TO A SEMICONDUCTOR SUBSTRATE
67
Patent #:
Issue Dt:
09/12/2000
Application #:
09227483
Filing Dt:
01/07/1999
Title:
APPARATUS FOR TESTING REDUNDANT ELEMENTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
68
Patent #:
Issue Dt:
02/27/2001
Application #:
09228293
Filing Dt:
01/08/1999
Title:
METHOD FOR IMPROVING THE SIDEWALL STOICHIOMETRY OF THIN FILM CAPACITORS
69
Patent #:
Issue Dt:
08/10/1999
Application #:
09228342
Filing Dt:
01/11/1999
Title:
N-CHANNEL VOLTAGE REGULATOR
70
Patent #:
Issue Dt:
03/07/2000
Application #:
09228581
Filing Dt:
01/11/1999
Title:
MEMORY WITH VARIABLE WRITE DRIVER OPERATION
71
Patent #:
Issue Dt:
03/06/2001
Application #:
09228595
Filing Dt:
01/12/1999
Title:
METHOD OF MANUFACTURING A SINGLE DEPOSITION LAYER METAL DYNAMIC RANDOM ACCESS MEMORY
72
Patent #:
Issue Dt:
11/16/1999
Application #:
09228725
Filing Dt:
01/12/1999
Title:
FACET ETCH FOR IMPROVED STEP COVERAGE OF INTEGRATED CIRCUIT CONTACTS
73
Patent #:
Issue Dt:
06/20/2000
Application #:
09229373
Filing Dt:
01/13/1999
Title:
UTILIZATION OF DIE REPATTERN LAYERS FOR DIE INTERNAL CONNECTIONS
74
Patent #:
Issue Dt:
08/08/2000
Application #:
09229474
Filing Dt:
01/13/1999
Title:
OPERATING VOLTAGE SELECTION CIRCUIT FOR NON-VOLATILE SEMICONDUCTOR MEMORIES
75
Patent #:
Issue Dt:
11/02/1999
Application #:
09229476
Filing Dt:
01/13/1999
Title:
POLISHING PAD WITH INCOMPRESSIBLE HIGHL SOLUBLE PARTICLES FOR CHEMICAL-MECHANICAL PLANARIZATION OF SEMICONDUCTOR WAFERS
76
Patent #:
Issue Dt:
03/20/2001
Application #:
09229487
Filing Dt:
01/13/1999
Title:
APPARATUS AND METHODS FOR CONDITIONING POLISHING PADS IN MECHANICAL AND/OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC-DEVICE SUBSTRATE ASSEMBLIES
77
Patent #:
Issue Dt:
08/28/2001
Application #:
09229518
Filing Dt:
01/13/1999
Title:
SEMICONDUCTOR CIRCUIT COMPONENTS AND CAPACITORS
78
Patent #:
Issue Dt:
04/11/2000
Application #:
09229891
Filing Dt:
01/14/1999
Title:
LARGE GRAIN SINGLE CRYSTAL VERTICAL THIN FILM POLYSILICON MOSFETS
79
Patent #:
Issue Dt:
06/05/2001
Application #:
09231129
Filing Dt:
12/30/1998
Title:
METHOD AND A CIRCUIT FOR IMPROVING THE EFFECTIVENESS OF ESD PROTECTION IN CIRCUIT STRUCTURES FORMED IN A SEMICONDUCTOR
80
Patent #:
Issue Dt:
10/24/2000
Application #:
09231137
Filing Dt:
01/15/1999
Title:
WELL RESISTOR FOR ESD PROTECTION OF CMOS CIRCUITS
81
Patent #:
Issue Dt:
08/27/2002
Application #:
09231158
Filing Dt:
01/15/1999
Title:
METHOD AND SYSTEM FOR CENTRALIZED STORAGE AND MANAGEMENT OF ELECTRONIC MESSAGES
82
Patent #:
Issue Dt:
01/23/2001
Application #:
09231176
Filing Dt:
01/14/1999
Title:
A METHOD FOR MAKING A TRENCH ISOLATION FOR SEMICONDUCTOR DEVICES
83
Patent #:
Issue Dt:
02/13/2001
Application #:
09231306
Filing Dt:
01/13/1999
Title:
CIRCUIT BOARD GROUNDING AND SUPPORT STRUCTURE APPARATUS AND METHOD
84
Patent #:
Issue Dt:
09/19/2000
Application #:
09231346
Filing Dt:
01/13/1999
Title:
SEMICONDUCTOR DEVICE HAVING A SUBSTRATE, AN UNDOPED SILICON OXIDE STRUCTURE, AND AN OVERLYING DOPED SILICON OXIDE STRUCTURE WITH A SIDE WALL TERMINATING AT THE UNDOPED SILICON OXIDE STRUCTURE
85
Patent #:
Issue Dt:
06/13/2000
Application #:
09231725
Filing Dt:
01/15/1999
Title:
SIGNAL TRANSITION DETECTOR FOR ASYNCHRONOUS CIRCUITS
86
Patent #:
Issue Dt:
12/07/1999
Application #:
09231853
Filing Dt:
01/14/1999
Title:
LOW-TO-HIGH VOLTAGE CMOS DRIVER CIRCUIT FOR DRIVING CAPACTIVE LOADS
87
Patent #:
Issue Dt:
04/24/2001
Application #:
09232442
Filing Dt:
01/15/1999
Title:
METHOD AND SYSTEM FOR ATTACHING SEMICONDUCTOR DICE TO SUBSTRATES
88
Patent #:
Issue Dt:
02/05/2002
Application #:
09233299
Filing Dt:
01/19/1999
Title:
TRI-STATING ADDRESS INPUT CIRCUIT
89
Patent #:
Issue Dt:
04/09/2002
Application #:
09233313
Filing Dt:
01/19/1999
Publication #:
Pub Dt:
01/17/2002
Title:
METHOD AND COMPOSITE FOR DECREASING CHARGE LEAKAGE
90
Patent #:
Issue Dt:
06/04/2002
Application #:
09233358
Filing Dt:
01/19/1999
Title:
METHOD AND APPARATUS FOR PACKAGING FLIP CHIP BARE DIE ON PRINTED CIRCUIT BOARDS
91
Patent #:
Issue Dt:
01/11/2005
Application #:
09233377
Filing Dt:
01/18/1999
Publication #:
Pub Dt:
03/07/2002
Title:
METHOD OF FORMING A REFRACTORY METAL SILICIDE
92
Patent #:
Issue Dt:
09/11/2001
Application #:
09233774
Filing Dt:
01/19/1999
Title:
INTEGRATED CIRCUIT HAVING AN ON-BOARD REFERENCE GENERATOR
93
Patent #:
Issue Dt:
12/26/2000
Application #:
09233871
Filing Dt:
01/20/1999
Title:
LATERAL BIPOLAR TRANSISTORS AND SYSTEMS USING SUCH
94
Patent #:
Issue Dt:
10/24/2000
Application #:
09233930
Filing Dt:
01/20/1999
Title:
METHOD OF PATTERNING SUBSTRATES USING MULTILAYER RESIST PROCESSING
95
Patent #:
Issue Dt:
07/25/2000
Application #:
09233938
Filing Dt:
01/20/1999
Title:
EQUILIBRATE CIRCUIT FOR DYNAMIC PLATE SENSING MEMORIES
96
Patent #:
Issue Dt:
04/18/2000
Application #:
09233997
Filing Dt:
01/19/1999
Title:
METHOD OF CONSTRUCTING STACKED PACKAGES
97
Patent #:
Issue Dt:
05/30/2000
Application #:
09234003
Filing Dt:
01/19/1999
Title:
FACEPLATES HAVING BLACK MATRIX MATERIAL
98
Patent #:
Issue Dt:
12/05/2000
Application #:
09234016
Filing Dt:
01/19/1999
Title:
DRIVING CIRCUIT WITH THREE OUTPUT LEVELS, ONE OUTPUT LEVEL BEING A BOOSTED LEVEL
99
Patent #:
Issue Dt:
10/31/2000
Application #:
09234194
Filing Dt:
01/20/1999
Title:
DEVICE FOR DEMODULATING A BINARY PHASE-SHIFT KEYED SIGNAL
100
Patent #:
Issue Dt:
06/26/2007
Application #:
09234233
Filing Dt:
01/20/1999
Title:
SEMICONDUCTOR PROCESSING METHODS
Assignor
1
Exec Dt:
04/26/2016
Assignee
1
633 WEST FIFTH STREET, 24TH FLOOR
LOS ANGELES, CALIFORNIA 90071
Correspondence name and address
WSGR, C/O QUI LU, SENIOR PARALEGAL
650 PAGE MILL ROAD
FH 2-1 P12
PALO ALTO, CA 94304

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